INDIANA UNIVERSITY, DEPT.

OF PHYSICS, P400/540 LABORATORY

FALL 2008

Laboratory #9: Continued Fun with Flip-Flops

Goal: Learn about and build the three main types of flip-flops and use them in
useful circuits as latches, counters, shift registers, and one-shots.


1. D-Type Flip-Flop or Clocked Flip-Flop

The simplest of the clocked flip-flop types, the D-type, simply saves at its output
(Q) what it saw at its input (D) just before the last clocking edge. The particular D-type
flip-flop used below, the 74HC74, responds to a rising edge.

The D-type is actually used much more often than the fancier J -K flip-flop that we will
encounter next.


(a) Basic Operation: Saving a Level; Reset.

Feed the D input from a breadboard slide switch. Clock the flip-flop with a
"debounced" pushbutton (the buttons on the left side of the breadboard remember that
these switch terminals need pull-up resistors, i.e., see the diagram below...). "Dis-assert"
RESET AND SET (sometimes called CLEAR and PRESET) by tying them to +5 V.
2
4
1
+5 V
+5 V
5
1/2 of 74LS74
cc
V =14
Gnd =7
From "debounced"
pushbutton
"Data" from slide
switch
6
3
D
CLK >
Q
Q
S
R


+5 V
+5 V
Debouncer
Pullup resistors
that need adding
if want logic
HIGH also
"NO"
(normally open)
10k
10k
"NC"
(normally closed)


o Confirm that the D-type flip-flop ignores information presented to its input
(D, for "data") until the flip-flop is clocked.
o Try asserting RESET. You can do this with a wire to ground; bounce is
harmless here. (Why?) What happens if you try to clock in a HIGH at D
while asserting RESET?
o Try asserting SET and RESET at the same time (something you would never
do on purpose in a useful circuit!). What happens? Look at both outputs.
What determines what state the flip-flop rests in after you release both?
Does this answer provide a clue why you would not want to assert both at
the same time in a circuit?


(b) Toggle Connection: Using Feedback

The feedback in the circuit below may make you uneasy. However, the clock
makes this circuit easy to analyze since it breaks the feedback path. Build this circuit and
try it.
2
4
1
+5 V
+5 V
5
6
3
CLK
D
>
Q
Q
S
R


o First clock the circuit manually (using the pushbutton).
o Then clock it with a square wave from an external function generator (that can go
to higher frequency than the lowly breadboard function generator). Watch CLOCK
and Q on the scope. What is the relation between f
clock
and f
Q
? Now you know
why this little baby is sometimes given the fancy name "divide-by-two".
o Crank up the clock rate to the function generators maximum, and measure the
flip-flop's propagation time. To do this, consider what voltages IN and OUT to
use, as you measure the time elapsed. You can settle that by asking yourself just
what it is that is propagating?


2. J-K Type Flip-Flop (another Clocked Flip-Flop)

The J -K flip-flop's strength is its versatility. It can mimic the other important flip-
flop types: the D or T (toggle)-type.

(a) Checkout: Verify the J -K flip-flop's behavior (described in lecture and in your text).

Dis-assert SET and RESET ; drive the J and K inputs from slide switches; clock the
flip-flop with a debounced signal from the pushbuttons.
3
4
15
+5 V
+5 V
5
1/2 of 74LS112
cc
V =16
Gnd =8
From "debounced"
pushbutton
6
1
J
CLK >
2
K
Q
Q
S
R

Fill out the operation table:

J K Q
n+1

0 0
0 1
1 0
1 1



(b) Applications: Mimicking Others

Try these two variations, and determine which is a D-type and which is a T-
type.
J
CLK
>
K
Q J
CLK
>
K
Q


In Q
n+1

0
1

In Q
n+1

0
1


3. J-K Flip-Flop in Counters

(a) Ripple Counter

The preceding J -K circuit, like the earlier D-type-with-feedback, can be made to
toggle on every clock, or "divide-by-two".

Cascading two such circuits allows you to divide by four, and so on. Build this
circuit:
J
3
5
1
2
+5 V
CLK
>
K
Q
0
J
11
13
Dis-assert S and R on both as usual
12
9
+5 V
CLK
>
K
Q
1

o Watch the counter's output on two LEDs while clocking the circuit at a few
Hz. Does it "divide by four"? If not, your circuit or your understanding of
this phrase may be faulty. Fix whichever one needs fixing.
o Now clock the counter as fast as you can, and watch CLK and first Q
0
and
then Q
1
on the scope. Trigger on Q
1
.
o Watch the two Q's together and see if you can spot the "rippling" effect
that gives the circuit its name: a lag between changes at Q
0
and then Q
1
.


(b) Synchronous Counter

Now alter the circuit to the form shown below. This is a synchronous counter.

J
3
5
1
2
+5 V
CLK
>
K
Q
0 0
0
CLK
J
11
13
Dis-assert S and R on both as usual
12
9
CLK
>
K
Q
1 1
1
74LS112


Note the negation on the CLK input of the second flip-flop (i.e., use a inverter
gate or tweaked NAND gate to get it).

See if you can use the scope to confirm that the ripple delay that you saw before
is now gone.

6. Shift Register

The shift register below delays the signal called "IN", and synchronizes it to the
clock. Both effects can be useful. You will use this circuit in a bit as a one-shot, that is, a
circuit that generates a single pulse in response to a "Trigger" input (here the signal
called "IN").

4
9
1
+5 V
2
3
CLK
CLK
IN
74LS175
D
>
Q
Q
R
5 7
6
CLK
D
>
Q
Q
R
12 13 10
11
CLK
D
>
Q
Q
R
15
14
CLK
D
>
Q
Q
R
cc
V =16
Gnd =8


(a) Slow-motion: first use a manual switch to drive "IN", and set the clock rate to
a few Hz (using either an external function generator or the breadboard generator).
Watch the Q outputs for each flip-flop using the breadboard LEDs. Watch your input bit
"march through" the flip-flops as they are clocked.

(b) Now clock the circuit with a logic signal from an external function generator,
and use the breadboard's oscillator to provide "IN". Let f
clock
be at least 10 f
in
. Watch the
outputs from each flip-flop on the scope.
Add NAND Gates: Digitally-timed (synchronous) Double-Barreled One-Shot

Add two NAND gates, as shown below, and watch those gates' outputs along
with TRIG. Note the effect of altering f
clock
.
4
9
1
+5 V
2
3
CLK
CLK
TRIG
74LS175
D
>
Q
Q
R
5 7
6
CLK
D
>
Q
Q
R
12 13 10
11
CLK
D
>
Q
Q
R
15
Out A
Out B
1/4 74LS00
1/4 74LS00
14
CLK
D
>
Q
Q
R
cc
V =16
Gnd =8


(a) Slow-motion: again, first use a manual switch to drive TRIG, and set the clock rate to
a few Hz. Watch the one-shot outputs on two of the breadboard's buffered LEDs. Take
TRIG low for a second or so, then high. You should see first one LED then the other
wink low, in response to this low-to-high transition.

(b) Full-speed: when you are satisfied that the circuit works, drive TRIG with a square
wave from one function generator (the breadboard's) while clocking the device with an
external function generator (at a higher rate).

To make sure you understand what this circuit is doing, make a timing diagram
as shown on page 341 of your lab manual. Keep this circuit mounted on your
breadboard.