Parametric Optimization of Multistage Operational Amplifiers by Using Imperialist

Competitive Algorithm

Abstract This work presents a computer-aided design (CAD)
tool for parametric optimization of multistage operational
amplifiers (Op-Amps). This tool uses imperialist competitive
algorithm (ICA) in order to determine the device sizes that
optimize the performance objectives while satisfying the
constraint specifications. ICA is a novel global search heuristic
algorithm that is generally inspired by modeling the natural
processes and other aspects of species evolution, especially
human evolution. This algorithm uses socio-political evolution
of human as a source of inspiration for developing a powerful
optimization strategy. To evaluate the tool, typical and hard-
to-design examples with stringent design requirements are
presented in 0.18 m CMOS technology. Simulation results
confirm the efficiency of the proposed method for analog
circuits design.
Keywords- computer-aided design;analog integrated circuits;
multistage operational amplifiers; imperialist competitive
algorithm; optimization
I. INTRODUCTION
VLSI technology is now maturing rapidly with a current
emphasis towards the integration of whole systems on a
single chip. For many applications, in telecommunications,
instrumentation, and image and signal processing, integrated
VLSI systems require the implementation of both analog
and digital functions on the same integrated circuit (IC)
using the same technology. Although typically only a small
portion of these systems are analog, the relative complexity
of analog circuits, coupled with the lack of sophisticated
CAD tools, make analog circuit design difficult, iterative
and hence time-consuming. Therefore, the design time of
mixed analog-digital systems is primarily dominated by the
design time of the analog parts, because digital parts are
now synthesized rapidly using the well established CAD
tools available for digital circuits. The best way to design
such mixed systems rapidly is to develop CAD tools that
can automatically design analog cells [1].
Analog circuit design is generally achieved through the
following steps: Topology selection, Parametric optimization
and Layout generation.
First, the designer selects an appropriate circuit topology
among various possible architectures and topologies, to
achieve higher performances for a particular application. The
second step is sizing devices (widths and lengths of the MOS
transistors, resistors and capacitors values as well as bias
voltages and currents). The optimized circuit then needs to
be transformed into a layout [2].
This sizing process usually needs several iterations, tries
and errors with computer simulations. Soft computing
methods can be used to decrease the design time, increase
the design accuracy and allow nonexperts to design complex
analog circuits [2], [3].
One of those methods, called imperialist competitive
algorithm (ICA) is a global search heuristic [4]-[6], which
models the process of the natural evolution in order to find a
set of circuit parameters (or design variables) such that the
design objectives are optimized while satisfying performance
constraints for multistage operational amplifiers.
The paper is organized as follows. Section II reviews
recent efforts in parametric optimization. An overview of
imperialist competitive algorithm is presented in Section III.
Section IV describes design procedure which uses proposed
evolutionary optimization algorithm for circuits sizing.
Simulation results are provided in Section V to verify the
performance and capability of the proposed method. Finally,
Section VI presents some concluding remarks.
II. PREVIOUS EFFORTS
In recent years, several prototype design automation
(DA) systems have been proposed to automate the design of
cell-level analog circuits. Most of these systems concern
parametric optimization. Two approaches have been used.
1) Knowledge-based approach.
2) Optimization-based approach.
The basic idea of knowledge-based approach is to
formulate design equations in such a way that given the
performance characteristics, the design parameters can be
calculated. In these tools, the quality of the solutions in terms
of both accuracy and robustness is not acceptable since the
concept of knowledge-based sizing forces the design
equations to be simple. Other drawbacks are the large
preparatory time/effort required to develop design plans or
equations, the difficulty in using them in a different
technology, and the limitation to a fixed set of circuits. Some
of the systems reported in the literature that follow this
approach are IDAC [7], OASYS [8], and OAC [9].
A. Jafari
Dep. of Electrical Engineering
Islamic Azad University
Member of IEEE and Scientific Society
Bushehr, Iran
Ajafari@iaubushehr.ac.ir


E. Bijami
Dep. of Electrical Engineering
Isfahan University of Technology
Student Member of IEEE
Isfahan, Iran
e.bijami@ec.iut.ac.ir

M. Zekri
Dep. of Electrical Engineering
Isfahan University of Technology
Isfahan, Iran
mzekri@cc.iut.ac.ir
2010 3rd International Conference on Computer and Electrical Engineering (ICCEE 2010)
V2-339
C 978-1-4244-7224-6 /10/$26.00 2010 IEEE
The optimization-based design approach uses recent
advances in the optimization theory and algorithms, and
relates these to the parametric optimization of analog ICs.
The synthesis problem is formulated as one of mathematical
programming. The circuit performances are considered to be
the objective functions, which are to be minimized or
maximized subject to a set of specification constraints.
Optimization-based design approaches can be broadly
classified into two categories: a) Simulation-based
optimization, b) Analytical equation based optimization.
Historically, the very first attempts towards analog DA were
numerical optimization based. Systems such as
DELIGHT.SPICE [10], ECSTACY [11], ADOPT [12], and
ASTRX/OBLX [13] consider the sizing of the individual
transistors in a given circuit topology as an optimization
problem [14].
Typically, these systems employ optimization algorithms,
which iteratively adjust the individual transistor sizes in
order to meet the constraints and objectives specified by the
user. A simulator is used within the optimization loop to
assess the performance of the circuit during each iteration.
These design approaches are referred to as simulation-based
optimization.
The time consuming and expensive simulator inside the
optimization loop is avoided by using simplified analytical
models that predict circuit performances and this approach is
referred to as analytical equation based optimization [2]. A
number of prototypes have evolved out in recent times,
which use this technique, e.g., OPASYN [15], STAIC [16],
FPAD [1], FASY [3].
The main goal of this work is to propose a new approach
that combines imperialist competitive algorithm (ICA) and
equation based optimization to produce an accurate CAD
tool in order to determine the device sizes in an analog
circuit. The proposed approach has the following advantages
over previous automation systems.
Some capabilities of ICA such as fast convergence
and better global minimum cause to decrease the
design time; consequently, this approach can be
used for online designs.

Using this approach causes to avoid a simulator in
the optimization loop and therefore avoid the cost of
repeated simulation, and speed up the approach in
order to make it interactive.
III. OVERVIEW OF ICA
Imperialist competitive algorithm (ICA) is one of the
evolutionary optimization algorithms that has been
introduced for dealing with different optimization problems
[17]-[19]. The ICA is a new socio-politically motivated
global search strategy that is derived from competition
process among imperialists and colonies. Flowchart of the
ICA is illustrated in Fig. 1.
Like other evolutionary ones, this algorithm begins with
an initial population. In this algorithm any individual of the
population is called a country. Some of the best countries
are selected to be the imperialist states and all the other
countries form the colonies of these imperialists. All the
colonies of initial population are divided among the
mentioned imperialists based on their power.


Figure 1. General principle of the ICA
After dividing all colonies among imperialists and
creating the initial empires, these colonies start moving
toward their relevant imperialist state. This movement is a
simple model of assimilation policy that was pursued by
some imperialist states. Fig. 2 shows the movement of a
No
Yes
Is there a colony in an
empire which
has lower cost than that
imperialist?
No
Yes
Yes
Begin
Initialize the empires
Move the colonies toward
their relevant imperialist
Pick the weakest colony from the weakest
empire and give it to the empire that has the
most likelihood to possess it
End
Exchange the positions of
that imperialist and colony
Compute the total cost of all empires
Eliminate this empire
Is there an empire
with no colonies?
Stop condition
satisfied?
No
2010 3rd International Conference on Computer and Electrical Engineering (ICCEE 2010)
V2-340
colony towards the imperialist. In this movement, and x are
random numbers with uniform distribution as illustrated in (1)
and d is the distance between colony and the imperialist.

x ~ U (0,d ) (1)

, )

where and are arbitrary numbers that modify the area
that colonies randomly search around the imperialist.
The total power of an empire depends on both the power
of the imperialist country and the power of its colonies. In
this algorithm, this fact is modeled by defining the total
power of an empire by the power of imperialist state plus a
percentage of the mean power of its colonies.
In imperialistic competition, all empires try to take
possession of colonies of other empires and control them.
This competition gradually brings about a decrease in the
power of weaker empires and an increase in the power of
more powerful ones.

Figure 2. Motion of colonies toward their relevant imperialist
This competition is modeled by just picking some
(usually one) of the weakest colonies of the weakest empires
and making a competition among all empires to possess
these (this) colonies. Based on their total power, in this
competition, each of empires will have a likelihood of taking
possession of the mentioned colonies. The more powerful
empire, the more likely it will possess these colonies. In
other words, these colonies will not be certainly possessed by
the most powerful empires, but these empires will be more
likely to process them. Any empire that is not able to succeed
in imperialist competition and cannot increase its power (or
at least prevent decreasing its power) will be eliminated.
The imperialistic competition will gradually result in an
increase in the power of great empires and a decrease in the
power of weaker ones. Weak empires will lose their power
gradually and they will collapse ultimately.
The movement of colonies toward their relevant
imperialists along with competition among empires and also
collapse mechanism will hopefully cause all the countries to
converge to a state in which there exist just one empire in the
world and all the other countries are its colonies. In this ideal
new world, colonies have the same position and power as the
imperialist [4], [20].
IV. DESIGN PROCEDURE
This section describes the optimization procedure.
A. Initialization
In this section ICA generates a random population of
individuals with values that are chosen for the circuit
parameters. These parameters could be lengths, widths and
overdrive voltages of the MOS transistors, resistors and
capacitors values, bias voltages and currents or etc.
Also, analytical equations of the analog circuits can be
found in [21], [22].
B. Fitness Function
Fitness is a single numerical quantity describing how
well an individual meets predefined design objectives and
constraints. In other words, the total performance of a circuit
is evaluated by fitness function. For fitness evaluation in a
multiobjective problem, several methods can be used. Here,
the fitness function (ff) is defined as

=
=
m
i
i i
f W 1 ff
1
/ (2)
f
i
= desired value for object i
w
i
= weight coefficient of object i
m = number of objects

C. ICA Operation
Some important parameters to implement the ICA are
assimilation coefficient, and . In most of implementations
a value of about 2 for and about /4 (Rad) for results in
good convergence of countries to the global minimum [5].

D. Halt Condition
ICA needs a halt condition to end the generation process.
Imperialistic competitions converge to a state in which there
exists only one empire, which is optimum solution; also, a
desired fitness value within some percentage of accuracy
can keep as halt condition.
E. Evaluation
In order to evaluate optimization algorithm, by using
variables obtained from previous steps, the multistage Op-
Amp circuits are simulated by using HSPICE program in
0.18 m CMOS technology.
V. SIMULATION RESULTS
In order to validate the proposed analog circuit design
approach, two detailed design examples in two different
topologies are presented. The first example concerns the
design of a two-stage CMOS operational amplifier (miller
compensated Op-Amp) circuit and the second example
involves the design of a three-stage CMOS operational
amplifier (nested miller compensated Op-Amp) circuit.
2010 3rd International Conference on Computer and Electrical Engineering (ICCEE 2010)
V2-341
~ U (-
A. Example 1: Design of a two-stage Op-Amp
The schematic of the basic two-stage CMOS Op-Amp is
shown in Fig. 3 and it is widely used because of its simple
structure and robustness. The design variables for this circuit
are the lengths (L), widths (W) and over drive voltages of all
transistors and compensation capacitor C
m
. The supply
voltages Vdd

and Vss and the load capacitance (C
L
) are taken
as constants specified by the user. In order to get the
independent design variables, which are to be varied during
the optimization process, it is assumed perfect matching
between transistors, as required by symmetry of the circuit.
Thus, the independent design variables of the circuit
topology shown in Fig. 3 are: X
N
, X
P
, W
1
, L
1
, W
3
, L
3
, W
5
, L
5
,
W
6
, L
6
, W
7
, L
7
, W
8
, L
8
and C
m
.


Figure 3. Schematic of the two-stage CMOS operational amplifier
The simulation of imperialist competitive algorithm was
performed in the MATLAB environment and the two-stage
Op-Amp shown in Fig. 3 was optimized for a set of circuit
specifications shown in Table I. After using the ICA, the
performance characteristics that were even better than the
desired objects were obtained. The circuit size vector and the
performance characteristics are shown in Tables II and III,
respectively.
The ICA is run for 10 independent runs under different
random countries. For the designed circuit, the average best-
so-far in each run is recorded and averaged over 10
independent runs. To have a better clarity, the convergence
characteristic in finding the best values for a set of circuit
specifications based on the objective function (2) is given in
Fig. 4.
TABLE I. SPECIFICATION OF TWO-STAGE CMOS OP-AMP
Electrical parameters Expected
Supply voltages (V) 0.75
Load capacitance: C
L
(pF) 3
DC gain: A
0
(dB) > 70
Gain-band width: GBW (MHz) > 5
Phase margin: PM (deg.) > 60
Slew rate: SR (V/sec) > 5
Power dissipation (W) < 500

TABLE II. OPTIMUM VALUES OBTAINED BY ICA
Parameter Value Unit
(W/L)
1,2
4.95 m/m
(W/L)
3,4
6.82 m/m
(W/L)
5
0.83 m/m
(W/L)
6
33.35 m/m
(W/L)
7

(W/L)
8

V
bias

Cm
1.74
2.88
-0.068
1.45
m/m
m/m
V
pF
TABLE III. SIMULATION RESULTS IN MATLAB AND HSPICE
Performance
specification
Value in
MATLAB
Value in
HSPICE
A
0
(dB) 82 84.8
GBW (MHz) 7.2 7.07
PM (deg.) 66 64
SR (V/sec) 5.4 5.14
Pdiss. (W) 43.4 35.27
Output swing (V) 1.24 1.17
Total area (m
2
) 230 230

As it can be seen, algorithm is converged to the
optimized point, after 25 iterations. Thus, all the given
specifications are satisfied and total fitness function is equal
to minimum.
Moreover, in order to evaluate optimization algorithm, by
using variables obtained from ICA, the two-stage Op-Amp
circuit is simulated by using HSPICE program in 0.18 m
CMOS technology and simulation results are shown in Table
III and Fig. 5.
0 10 20 30 40 50 60 70 80 90 100
1
1.05
1.1
1.15
1.2
1.25
iteration
a
v
e
r
a
g
e

b
e
s
t

s
o

f
a
r

Figure 4. Convergence characteristics of ICA on the average best-so-far
in finding the parameters of circuit for two-stage CMOS Op-Amp
2010 3rd International Conference on Computer and Electrical Engineering (ICCEE 2010)
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Figure 5. Frequency response of the two-stage Op-Amp
B. Example 2: Design of a three-stage Op-Amp

The voltage gain can be further increased by additional
gain stages. In this case, Fig. 6 depicts the schematic of a
three-stage CMOS Op-Amp (NMC) which is an extended
version of miller compensated Op-Amp, is used to achieve
the stability. Theoretically, NMC can be extended to infinite
number of stages. Nevertheless, no more than four stages
have been reported because of the reduction of bandwidth,
impractical large DC gain and higher power dissipation
required [23], [26]. Hence, only three-stage NMC amplifier
is discussed in this section. The design variables for this
circuit are the lengths (L), widths (W) and over drive
voltages of all transistors and compensation capacitors C
m1
and C
m2
. It is assumed perfect matching between transistors,
as required by symmetry of the circuit. The independent
design variables of the circuit topology shown in Fig. 6 are:
X
N
, X
P
, W
1
, L
1
, W
3
, L
3
, W
5
, L
5
, W
6
, L
6
, W
7
, L
7
, W
9
, L
9
, W
10
,
L
10
, W
11
, L
11
, C
m1
and C
m2.




Figure 6. Schematic of the three-stage CMOS operational amplifier
The simulation of imperialist competitive algorithm was
performed in the MATLAB environment and the three-stage
Op-Amp shown in Fig. 6 was optimized for a set of circuit
specifications shown in Table IV. The circuit size vector and
the performance characteristics are computed by means of
ICA and optimization results are shown in Tables V and VI,
respectively.
The convergence characteristic of ICA in finding the
best values of the circuit parameters for three-stage CMOS
Op-Amp is shown in Fig. 7.
TABLE IV. SPECIFICATION OF THREE-STAGE CMOS OP-AMP
Electrical parameters Expected
Supply voltages (V)
Load capacitance: C
L
(pF)
DC gain: A
0
(dB)
Gain-band width: GBW (MHz)
Phase margin: PM (deg.)
Slew rate: SR (V/sec)
Power dissipation (W)
0.75
100
> 100
> 0.1
> 60
> 0.1
< 500
TABLE V. OPTIMUM VALUES OBTAINED BY ICA
Parameter Value Unit
(W/L)
1

(W/L)
2,3

(W/L)
4,5

(W/L)
6

(W/L)
7,8

(W/L)
9

(W/L)
10

(W/L)
11

V
bias1

V
bias2

C
m1

C
m2

50.3
8
11.3
3.4
9.23
0.72
31
11.5
+0.25
- 0.15
98
30
m/m
m/m
m/m
m/m
m/m
m/m
m/m
m/m
V
V
pF
pF
TABLE VI. SIMULATION RESULTS IN MATLAB AND HSPICE
Performance
specification
Value in
MATLAB
Value in
HSPICE
A0 (dB)
GBW (MHz)
PM (deg.)
SR (V/sec)
Pdiss. (W)
Output swing (V)
Total area (m2)
105.2
0.21
63
0.17
65
1.32
436
103
0.16
61
0.13
88
1.28
436
The ICA is run for 10 independent runs under different
random countries. For the designed circuit, the average best-
so-far in each run is recorded and averaged over 10
2010 3rd International Conference on Computer and Electrical Engineering (ICCEE 2010)
V2-343
independent runs. More clearly, algorithm is converged to
the optimized point after 52 iterations. Hence, all the given
specifications are satisfied and total fitness function is equal
to minimum.
0 10 20 30 40 50 60 70 80 90 100
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
iteration
a
v
e
r
a
g
e

b
e
s
t

s
o

f
a
r

Figure 7. Convergence characteristics of ICA on the average best-so-far
in finding the parameters of circuit for three-stage CMOS Op-Amp

Furthermore, the obtained output results from the
optimization algorithm (ICA) are used in order to simulate
three-stage Op-Amp by using HSPICE program in 0.18 m
CMOS technology and simulation results are shown in Table
VI and Fig. 8.

Figure 8. Frequency response of the three-stage Op-Amp
The obtained results by using MATLAB and HSPICE
simulations for two different circuit topologies, confirm that
all the specifications are fully satisfied and output results
obtained from optimization algorithm match reasonably with
the results obtained from HSPICE simulations. This
substantiates the validity of presented algorithm for
parametric optimization of multistage Op-Amps.
Additionally, a comparison has been made between the
results of presented algorithm in this work and references
[24], [25], [26], [27], for both of two-stage and three-stage
Op-Amp circuits in Tables VII and VIII, respectively.
Also, two Figures of Merits (FOM) are indicated in
Tables VII and VIII as a criterion for comparing the total
performance of the amplifiers. One FOM is in small signal is
given by:

FOM
S
=GBWCL / Power (3)

And another FOM is in large signal is given by:

FOM
L
=SRCL / Power (4)

The larger FOM indicates better topology for
compensation in multistage amplifiers.
As it can be seen, the results obtained by this work are
better than other works in the most specifications.
TABLE VII. COMPARISON WITH PREVIOUS WORKS
Performance specification [24] [25] This work
A
0
(dB)
GBW (MHz)
PM (deg.)
SR (V/sec)
Pdiss. (W)
Total area (m2)
C
L
(pF)
FOMS
FOM
L

Process (m)
83.1
5.44
67
5.86
394
1220
5
69
74
0.5
76.48
2.06
55.94
1.52
731
933
30
84
62
0.25
84.8
7.07
64
5.14
35.27
230
3
606
440
0.18
TABLE VIII. COMPARISON WITH PREVIOUS WORKS
Performance specification [26] [27] This work
A0 (dB)
GBW (MHz)
PM (deg.)
SR (V/sec)
Pdiss. (W)
Total area (m2)
CL (pF)
FOMS
FOM
L

Process (m)
100
0.59
43
0.23
400
230
100
147
57
0.8
100
0.22
68
0.22
345
*
100
63
63
0.35
103
0.16
61
0.13
88
436
100
181
148
0.18
VI. CONCLUSION
This paper has presented a CAD tool for automatic
design of analog integrated circuits. Imperialist competitive
algorithm and equation based optimization were combined
in order to deduce the device sizes in the multistage CMOS
operational amplifiers. To validate the proposed method,
2010 3rd International Conference on Computer and Electrical Engineering (ICCEE 2010)
V2-344
two practical design examples were provided. Optimization
algorithm was performed in MATLAB environment and
Op-Amp circuits were optimized for a set of circuit
specifications. In addition, by using variables obtained from
ICA, the circuits were simulated by using HSPICE program
in 0.18 m CMOS technology. The simulation results for
different circuit topologies, verify efficiency of proposed
method to design and optimize the multistage operational
amplifiers. Note finally that, the proposed approach is a
general method and can be used to design of other types of
analog circuits.
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