Simulating Xilinx FPGA timing in Cadence

From LaPET electronics

What NETGEN does
Timing Simulation Post-Place and Route Full Timing (Block and Net Delays) may include:
Gate-level netlist containing SIMPRIM library components
Standard Delay Format (SDF) files
SecureIP
After your design has completed the Place and Route process in ISE Design Suite, a timing simulation netlist can be created. You now begin to see
how your design behaves in the actual circuit. The overall functionality of the design was defined in the beginning, but timing information can not be
accurately calculated until the design has been placed and routed.
The previous simulations that used NetGen created a structural netlist based on SIMPRIM models. This netlist comes from the placed and routed
Native Circuit Description (NCD) file. This netlist has Global Set/Reset (GSR) and Global Tristate (GTS) nets that must be initialized. For more
information on initializing the GSR and GTS nets, see Global Reset and Tristate for Simulation.
When you run timing simulation, a Standard Delay Format (SDF) file is created as with the post-Map simulation. This SDF file contains all block and
routing delays for the design.
Xilinx highly recommends running this flow. For more information, see Importance of Timing Simulation.
(as found on www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/sim.pdf )
What NGD2VER does
(note: it seems NGD2VER is no longer in use)
The NGD2VER program translates your design into a Verilog HDL file containing a netlist description of the design in terms of Xilinx simulation
primitives. Use the Verilog file to perform a simulation with the Verilog-XL Cadence simulator. For functional simulation and post-map timing
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simulation, you must use NGD2VER with the -tf and -ul options to create the appropriate files for use with the Cadence Verilog-XL simulator. Use
NG2VER to perform post-NGDBuild functional simulation, post-Map timing simulation, and post-route timing simulation. For post-implementation
simulation, you must also use the -pf option to create a PIN file if you wish to integrate your design into a Concept board level simulation.
quoted from http://www.xilinx.com/itp/data/alliance/cad/app2.htm
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This page was last modified on 12 November 2010, at 13:50.
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