8086 Microprocessor Complete: Bus Interface Unit (BIU)

8086 Microprocessor
Complete
Saturday, 8 December 2012
Bus Interface Unit (BIU)

The Bus Interface unit (BIU):-

This unit handles all transfer of data and addresses on the buses for the EU(execution unit). This unit sends out
addresses, fetches instructions from memory, reads data from ports and memory and writes data to ports and memory.

Different Parts of BIU:
a.Segment Register
b.Instruction Pointer
c.The Queue

1.)Segment Register:- BIU contains four 16-bit segment registers as follows:

Code segment (CS) register
Stack segment (SS) register
Extra segment (ES) register
Data segment (DS) register

Function of Segment Register:-

In 8086 complete 1MB memory is divided into 16 logical segments.
Each segment thus contains 64 KB of memory.
While addressing any location in the memory bank, the Physical address is calculated from two parts, the first part is
Segment address, and the second is Offset.
The segment registers contain 16-bit segment base addresses related to different segments.
Thus the CS, DS, ES, SS segment registers, respectively contain the segment addresses for the Code, Data, Extra and
Stack segments.
They may or may not be physical separated.
Each segment register contains a 16-bit base address that points to the lowest-addressed byte of that particular
segment in memory.

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Memory Address generation:-Now i am going to tell you about how physical memory addresses is determined. For this
bus interface unit has used an adder. You will understand the idea for finding the physical address with the help of
example.

Generation of physical address:-

Segment address- 1005H
Offset address - 5555H
Segment address-1005H- 0001 0000 0000 0101
Shifted by 4-bit positions-0001 0000 0000 0101 0000
+
Offset address - 0101 0101 0101 0101
Physical address -0001 0101 0101 1010 0101
1

Instruction Pointer:-
It is 16-bit register, which identifies the location of the next word of instruction code that is to be fetched in the current
code segment.
IP contains an offset instead of the actual address of the next instruction.
The 20-bit address produced after addition of the offset stored in IP to segment base address in the CS is called the
Physical address of the code byte.

Now i am going to tell you about how physical memory addresses is determined. For this
0001 0000 0000 0101
0001 0000 0000 0101 0000
0101 0101 0101 0101
0001 0101 0101 1010 0101
5 5 A 5
bit register, which identifies the location of the next word of instruction code that is to be fetched in the current
IP contains an offset instead of the actual address of the next instruction.
ddress produced after addition of the offset stored in IP to segment base address in the CS is called the
Now i am going to tell you about how physical memory addresses is determined. For this
bit register, which identifies the location of the next word of instruction code that is to be fetched in the current
ddress produced after addition of the offset stored in IP to segment base address in the CS is called the

The Queue:-
The last section of BIU is the FIFO group of registers called a queue. It is basically a grou
This arrangement makes possible for the BIU to fetch the instruction byte while EU is decoding an instruction or
executing an instruction which does not require use of buses.
This arrangement is called pipelining.
This is done to speed up the program execution.
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8086 Microprocessor Internal Architecture Diagram

8086 internal architecture:

BIU (Bus Interface Unit):-
It sends out tasks.
It fetches instructions from memory.
It reads data from memory and ports.
It also writes data from memory and ports.
So BIU takes care of all the address and data transfers on the buses.

The last section of BIU is the FIFO group of registers called a queue. It is basically a group of registers.
executing an instruction which does not require use of buses.
This arrangement is called pipelining.
is done to speed up the program execution.
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8086 Microprocessor Internal Architecture Diagram
ctions from memory.
It reads data from memory and ports.
It also writes data from memory and ports.
So BIU takes care of all the address and data transfers on the buses.
p of registers.

Execution Unit:-
It tells the BIU, from where to fetch the instruction or data.
It decodes the fetched instructions.
It executes the fetched instructions.
EU takes care of performing operations on data.
Important Features of 8086 Microprocessor

Basic features:-

1.It is 16 bit processor. So that it has 16 bit ALU, 16 bit registers and internal data bus and 16 bit external data bus. It make
s faster processing.

2.It has three version based on the frequency of operation:
a)8086 -> 5MHz
b)8086-2 ->8MHz
c)8086-1 ->10 MHz

3.8086 has 20 bit address lines to access memory. Hence it can access
2^20 = 1 MB memory location.

4.8086 has 16-bit address lines to access I/O devices, hence it can access
2^16 = 64K I/O location

5.Pipelining:-8086 uses two stage of pipelining. First is Fetch Stage and the second is Execute Stage.

Fetch stage that prefetch upto 6 bytes of instructions stores them in the queue.
Execute stage that executes these instructions.
Pipelining improves the performance of the processor so that operation is faster.

6.Operates in two modes:-8086 operates in two modes:
a)Minimum Mode: A system with only one microprocessor.
b)Maximum Mode:-A system with multiprocessor.

7.8086 uses memory banks:-The 8086 uses a memory banking system. It means entire data is not stored sequentially in a
single memory of 1 MB but memory is divided into two banks of 512KB.

8.Interrupts:-8086 has 256 vectored interrupts.

9.Multiplication And Division:-8086 has a powerful innstrction set. So that it supports Multiply and Divide operation.
Comparison of 8085 and 8086 Microprocessor

There are some of the difference mentioned below:

1.Size:-
8085 is 8 bit microprocessor whereas 8086 is 16 bit microprocessor.

2.Address Bus:-
8085 has 16 bit address bus and 8086 has 20 bit addres bus.

3.Memory:-
8085 can access upto 2^16 = 64 Kb of memory whereas 8086 can access upto
2^20 = 1 MB of memory.

4.Instruction Queue:-
8085 doesn't have an instruction queue whereas 8086 has instruction queue.

5.Pipelining:-
8085 does not support pipelined architechture whereas 8086 supports pipelined architechture.

6.Multiprocessing Support:-
8085 does not support multiprocessing support whereas 8086 supports.

7.I/O:-
8085 can address 2^8 = 256 I/O's and 8086 can access 2^16 = 65,536 I/O's

8.Airthmetic Support:-
8085 only supports integer and decimal whereas 8086 supports integer, decimal and ASCII arithmetic.

9.Multiplication and Division:-
8085 doesn't support whereas 8086 supports.

10. Operating Modes:-
8085 supports only single operating mode whereas 8086 operates in two modes.

11.External Hardware:-
8085 requires less external hardware whereas 8086 requires more external hardware.

12.Cost:-
The cost of 8085 is low and 8086 is high.

13.Memory Segmentation:-
In 8085, memory space is not segmented but in 8086, memory space is segmented.
Introduction to 8086 Microprocessor

INTRODUCTION:

8086 is an enhanced version of 8085 that has been developed by Intel in 1976.
It is a 16 bit Microprocessor. It has a powerful instruction set and it is capable to providing multiplication and division
operations directly. It has 20 address lines and 16 data lines. So it can access upto 1 MB of memory.
It supports two modes of operation: first is maximum mode and second is minimum mode. Minimum mode is applicable
for system that have a single processor and maximum mode is used for the multiprocessor system.
8086 provides an additional features that it has an instruction queue capable to store six instruction bytes from the
memory. The next instruction is fetched while the present instruction is being executed. So it makes the processor fast.

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8086 Microprocessor architecture (fully explained)
March 12, 2013 by Rohit 4 Comments
An Introduction to Microprocessor Architecture
(8086)
In this article you will learn about 8086 microprocessor architecture, along with its important features, the
concept of memorysegmentation and flag register used in 8086 microprocessor architecture. I will tell you
about the disadvantages of 8086 microprocessor architecture and also 8086 microprocessor features.
Read also: addressing modes of 8086 microprocessor

Features of 8086 microprocessor Architecture
It needs 5-MHz for 8086, 8-MHz for 8086-2 and 10-MHz for 8086-1
It is possible to perform bit, byte word and block operation in 8086. It performs the arithmetic
and logic operations on bit, byte and decimal numbers including multiply and divide.
The Intel 8086 microprocessor architecture is designed to two modes namely the minimum mode and the
maximum mode. When only one 8086 CPU is to be used in a microcomputer system the 8086 is used in
the minimum mode. In this mode the CPU issues the control signals required by memory and I/O device.
In multiprocessor system if operates in maximum mode, in this mode the control signals are generated
with the help of external bus controller (8288).
The INTEL 8086 microprocessor architecture supports Multi-programming.
In 8086 microprocessor architecture it pre-fetches up to six instruction bytes from memory and queues
them in order to increase the speed of execution.
8086 microprocessor architecture provides the powerful instruction set.

8086 Microprocessor architecture
The 8086 Microprocessor architecture consists of two sections
1. Bus Interface Unit (BIU)
2. Execution unit(EU)
Execution Unit
Execution unit in the microprocessor architecture does the following action
It informs B.I.U(bus interface unit) from where to fetch instruction of data and where to store the data.
It decodes the op-codes which is fetched from queue register and then execute that instruction
The important blocks are:
a). ID(Instruction decoder), Control Unit, ALU:
ID decodes the op-code which is fetched from Queue Register. Then the control unit will generate proper
control signals to execute that instruction. The ALU is 16-bit, i.e. it can perform arithmetic and logic operation
on 16-bit as well as 8-bit data.
b). Data Group (Arithmetic Register):
It has 8-general purpose register, denoted by AH, AL, BL, CH, CL, DH & DL. The width of each register is 8 bit.
They are used for 8-bit data. For 16-bit data we have to use AX, BX, CX, and DX. Here AX- register is known
as Accumulator. BX Register also used to sore the 16-bit effective address. CX register is also used as
implied counter for some instruction. DX register also used.
1. To store I/O address for some instructions, and
2. To store some part of result after performing multiplication and division.
c) Pointer and index register:
In this microprocessor architecture Pointer and index register are used to store 16-bit offset address. They are
SP (Stack Pointer), BP (Base Pointer), SI (Source Index Register), DI (Destination Index Register).
d) Flag Register in 8086 microprocessor architecture:
It is a 16-bit register, but in 8086 microprocessor architecture there are only 9-flags. So, only 9-bits are used.
All 9 flags Divided into two groups.
1. Conditional Flags: They are used to indicate some condition produced after executing aninstruction.
For this purpose 6-flags are used.
2. Control flags: they are used to control some operation of microprocessor. For that purpose 3 flags are
used.
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BIU (Bus Interface unit)
It is 8086 microprocessor architecture interface to the outside world. It provides the 16-bit
bidirectional data bus and 20 bit address bus. This unit is responsible for performing all external bus
operations.
1. It gives address of memory or I/O.
2. It fetches opcode from memory.
3. It read data from memory or I/O port.
4. It writes data into memory or I/O port.
5. It supports instruction queuing.
The important blocks in the BIU are:
Instruction pointer
It is a 16-bit register. It is used to store 16
20-bit physical address (PA) by using base address and effective address.
For E.g. - content of CS is 4000H and content of IP is 1250H. Now the physical address is given as.

Segment register
We have a 4-segment register known as CS
Register), SS Register (Stack Segment Register), and ES Register (Extra Segment Register).
In 8086 microprocessor architecture the width of each register
address of memory segment. This address is known as Base address.
Queue register (Instruction Register)
It is a 6-byte register. It is used to store 6
this register in FIFO form. The BIU fetches this when EU is executing the currentinstruction. When EU is ready
for next instruction, it simply reads from queue register instead of from memory. Therefore speed is increased.
This technique is known as pipeline. This is the advantage of the queue register.
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Memory Segmentation in 8086 microprocessor
architecture and its Advantages
It gives address of memory or I/O.
from memory.
It read data from memory or I/O port.
data into memory or I/O port.
queuing.
The important blocks in the BIU are:
Instruction pointer
bit register. It is used to store 16-bit effective address or logical address) for CS register.
l address (PA) by using base address and effective address.
content of CS is 4000H and content of IP is 1250H. Now the physical address is given as.

Segment register
segment register known as CS- register (Code Segment register), DS- register (data Segment
architecture the width of each register is 16- bit, it is used to store upper 16
address of memory segment. This address is known as Base address.
Queue register (Instruction Register)
byte register. It is used to store 6-bytes which are fetched from CS memory. The 6
FIFO form. The BIU fetches this when EU is executing the currentinstruction. When EU is ready
instruction, it simply reads from queue register instead of from memory. Therefore speed is increased.
s known as pipeline. This is the advantage of the queue register.
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and its Advantages
bit effective address or logical address) for CS register. BIU generates
content of CS is 4000H and content of IP is 1250H. Now the physical address is given as.
register (data Segment
bit, it is used to store upper 16- bit starting
bytes which are fetched from CS memory. The 6-bytes are stored in
FIFO form. The BIU fetches this when EU is executing the currentinstruction. When EU is ready
instruction, it simply reads from queue register instead of from memory. Therefore speed is increased.
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Physical address of 8086 is 20 bit wide. So it can access 1 MB memory (2^20*8=1 MB or 16*64 KB). This 1 MB
memory is divided into 16 Segment memories. The capacity of each memory segment is 64 KB. But 8086 can
access at a time only memory segment. They are CS memory, DS memory, SS memory and ES memory.
Instruction fetch operations are performed in DS memory. String operations are performed in ES memory.
For the selection of each segment memory, 8086 has 4- segment registers. They are known as CS Register, DS
Register, SS Register, and SS Register. The content of each segment register is known as the Base Register. BIU
generates 20-bit physical Address by using Base Address and Effective Address.
Advantages of Memory segmentation
In 8086 microprocessor architecture It permits its programmer to access 1MB memory even though
address associated with the Instruction is 16 bit.
Instruction, data, sack of a program can be more than 64KB memory in8086 microprocessor architecture
8086 microprocessor architecture permits separate memory area for instruction, data and stack. So one
program can work on different sets of data.
This method is very useful during the multitasking in 8086 microprocessor architecture
Disadvantage: Even though memory capacity is 16*64KB,
microprocessor can access at a time only 4*64 KB of memory.
Flag Register in 8086 microprocessor architecture

1. Conditional flags in 8086 microprocessor architecture:
1. Carry flag: this flag is set whenever there is an overflow from MSB after performing arithmetic
operation, otherwise it is reset. For 8-bit operation overflow is from B7 bit for 16-bit operation overflow is from
B15 bit.
2. Parity Flag: This flag is set if lower order 8-bit of the result consists of even number of 1s, otherwise it is
reset.
3. Auxiliary Carry flag: This flag is set if there is overflow from lower 4-bits after performing arithmetic
operation, otherwise it is reset.
4. Zero Flag: this flag is set if the result is zero after performing ALU operation, otherwise it is reset.
5. Sign flag: It is set if MSB of the result is equal to 1 after performing ALU operation, otherwise it is reset.
(for 8-bit data it is set when B7=1, for 16-bit data it is set when B15=1),
6. Overflow Flag: this flag is set, if the result cannot be stored in destination location, otherwise it is reset.
This flag is checked during signed arithmetic. This flag can be checked by using aninstruction INTO.
It will set when
Overflow from B6 to B7, AND no overflow from B7(for 8-bit operation)
Overflow from B14 to B15 AND no overflow from B15(for 16-bit operation)
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2. Control flag
A) Trap Flag: When this flag is set, 8086 enters into single stepping mode. In this mode system will execute
one instruction and wait for further direction from the programmer. It is used to debug the program. If it is
reset, control continues sequentially
B) Interrupt Enable Flag: When it is set, 8086 recognizes interrupt INTR. If it is reset it will not
recognize interrupt INTR i.e. INTR is maskable interrupt.
C) Directional Flag: When it is set, content of SI or DI or both automatically decremented (by 1 or 2) after
executing the string instruction. If it is reset, content of SI or DI or both areautomatically incremented (by 1 or
2) after executing the string instruction.
So, this article is dedicated to the 8086 Microprocessor architecture, in the next article we will discuss about
the addressing modes of 8086 and instructions set of 8086 microprocessor. if you have any query
regarding 8086 Microprocessor architecture, then you can comment below, I will surely respond to your
comment with appropriate answer.:)

8086 Microprocessor Complete: Bus Interface Unit (BIU)

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