Chapter 2 - Analog Integrated Circuit Design by John Choma

LECTURE SUPPLEMENT #2 . . .
[LS #2]
CHAPTER #02

The PN Junction Diode

Dr. John Choma
Professor of Electrical Engineering
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Los Angeles, California 900890271
2137404692 [USC Office]
2137407581 [USC Fax]
8183841552 [Cell]
johnc@usc.edu

PRELUDE:
We address the fundamental physical properties, volt-ampere characteristics, and
circuit level models of the semiconductor PN junction diode in this chapter. While
PN junction diodes are commonly fabricated in either silicon or germanium
semiconductor technologies, most of the disclosures in this chapter focus on sili-
con diodes. Also discussed are a few practical applications of the diode, includ-
ing half wave and full wave rectifiers, logarithmic amplifiers, and limiters.

May 2013
Chapter 2 PN J unction Diode

- 89 -

2.1.0. INTRODUCTION
The semiconductor PN junction diode is the simplest of solid-state circuit elements. Its
simplicity belies its critical importance to the state of the electronics. This importance stems
from the fact that an understanding of the physical properties and operation of a junction diode
promotes an insightful comprehension of the operation and general behavior of more complex
electronic devices. The most notable of these complex solid state devices are the bipolar junc-
tion transistor (BJT) and the metal-oxide-semiconductor field effect transistor (MOSFET). How-
ever, the diode is more than a mere crutch for understanding complex intricate devices in that the
PN junction diode itself boasts utility in numerous applications. Included among these applica-
tions are voltage references capable of sustaining relatively constant voltages in the face of
temperature increases and/or variations in power supply voltages. Yet another application of the
diode is the rectifier (or AC -to- DC converter) that converts periodic voltage waveforms having
zero average values (and hence no DC values) to unidirectional energy offering nonzero DC
voltage levels. This conversion capability is foundational to transforming the alternating line
voltages supplied to private and commercial establishments by local power companies to the
constant, time invariant voltages mandated by non-portable electronic systems.
x
0 W
n
W
p
H
L
M
e
t
a
l
C
o
n
t
a
c
t
i (t)
d
i (t)
d
+ v (t)
d
+ v (t)
d
PN Junction
(a).
(b).

Figure (2.1). (a). Physical abstraction of a PN junction semiconductor diode. (b). Electrical schematic
symbol of the PN junction diode.
Figure (2.1a) is a simplified physical representation of a PN junction diode, while Fig-
ure (2.1b) depicts the corresponding electrical schematic symbol. The diode is a physical struc-
ture formed by p-type and n-type semiconductor crystals, such that at their common physical
boundary, which is termed the semiconductor junction, or PN junction, an almost abrupt transi-

- 90 -

tion from p-type -to- n-type semiconductor is achieved. The p-type region is doped with accep-
tor impurities at an average concentration of N
A
(in units of atoms -per- cm
3
), while the n-type
volume has an average donor impurity concentration of N
D
. Generally, we find that N
A
is around
four or five orders of magnitude smaller than is N
D
, which is of the order 10
20
-to- 10
21

atoms/cm
3
. Thus, the n-type region is doped very strongly and actually near its solid solubility
limit, which is to say that this region is doped to nearly its maximum impurity capacity. Al-
though the impurity concentration profiles in either diode region are rarely constant, independent
of position variable x in the diagram, we can garner the salient features of diode operation by
assuming that these doping concentrations are constant at their respective average, or at least at
some appropriately weighted average, values.
The thickness of the p-region is noted as W
p
, while that of the n-type crystal is W
n
.
Both of these dimensions are of the order of microns
1
, with W
p
being roughly half that of W
n
.
Dimensions L and H define the cross section junction area, A
e
, as A
e
= LH. In a monolithic
realization of a diode destined for high-speed signal processing applications, L is usually about a
micron or even smaller. Depending on the current level that we wish the diode to conduct with-
out causing thermal stress, H is typically a designable variable that can be several times -to- sev-
eral tens or even hundreds of times larger than L. The area, A
e
, in question is the junction cross
section pierced orthogonally by the diode current, i
d
(t), which flows in response to an applied
diode voltage, v
d
(t). We posture i
d
(t) as a positive current that flows from the p-type region to
the n-type region, while we consider v
d
(t) to be a positive voltage when it raises the potential of
the p-side of the junction above that of the n-side.
Let us assume that the implanted or diffused dopants atoms of both impurities are com-
pletely ionized, which is a reasonable, but slightly flawed, presumption. The concentration of
free and mobile hole charge on the p-side of the junction follows as qN
A
, where q is the magni-
tude of electron charge
2
. On the n-side of the junction, the concentration of mobile electron
charge is qN
D
. When the diode in question is connected into a circuit that establishes v
d
(t) > 0,
we say that the diode is forward biased. Under this biasing condition, the injection of free elec-
trons from the n-type region, across the semiconductor junction, and into the p-type volume is
encouraged. Of course, hole injection from the p-side of the PN junction -to- the n-side is also
promoted. But in view of the fact that the acceptor impurity concentration is orders of magni-
tude smaller than the donor impurity concentration, the injected charge observed across a for-
ward biased PN junction is dominated by electrons. This electron dominance arguably supports
high-speed signal processing capabilities in a diode since the mobility (ability to move in re-
sponse to biasing conditions) of transported electrons is at least twice as large as the mobility of
holes. Since the time rate of change of charge through a cross section constitutes a current and
since electrons carry negative charge, this electron injection manifests a positive diode current;
that is a current whose directional flow mirrors that of the indicated p-region -to- n-region diode
current, i
d
(t). While hole injection is anemic in comparison to electron injection, the positive na-
ture of transported hole charge produces a diode current whose directional flow mirrors that
associated with electron transport across the semiconductor junction. In short, a diode that oper-
ates in its forward bias regime can conduct potentially large currents because of the simultaneous
(and dominant) injection of majority charge (charge due to electrons from the n-type region and
charge due to holes from the p-type volume) across the diode PN junction.
In contrast to forward diode biasing, the reverse biased diode, whose basic operating re-

1
One micron (1 m) is equivalent to 10
4
centimeter (10
4
cm).
2
The magnitude of electron charge, q, is q = 1.6(10
19
) coulombs.

- 91 -

quirement is v
d
(t) < 0, moves free electrons further away from the junction and toward the metal
contact at the end of the n-type region where positive potential prevails. The negative diode
junction voltage also displaces free holes away from the junction and toward the metal contact at
the end of the p-type volume where negative potential is witnessed. Reverse biasing is therefore
seen as inhibiting majority charge injection across the semiconductor junction, thereby ensuring
current turn off of the diode, in the sense of zero current conduction precipitated by majority
charge transport across the PN junction of the diode. Although zero diode current is usually a
reasonable approximation under reverse bias conditions, the reverse biased diode current, i
d
(t), is
not quite zero. It is actually nominally constant at the small negative value, I
o
, where I
o
is
known as the diode saturation or leakage current.
The foregoing leakage current is manifested by the fact that although the mobile charge
on the p-side of the junction is dominated by holes, a small, but assuredly nonzero, concentration
of electrons prevails therein. Similarly, a small, but nonzero, concentration of holes permeates
the n-side of the PN junction. These contentions stem from the fact that in the charge neutral re-
gions of a semiconductor volume, the product of mobile hole and mobile electron concentrations
is a constant given by the square of the intrinsic carrier concentration, n
i
. At a junction tempera-
ture of 27 C, parameter n
i
is about 10
10
carriers/cm
3
in silicon. While n
i
is a constant that is
independent of doping concentrations, applied voltage levels, and observed current densities, it
does vary with operating temperature, nominally doubling to quadrupling for every 10 C rise in
junction temperature. Thus, in the p-volume where the hole concentration is essentially the
acceptor doping concentration, N
A
, the electron concentration is a small number proportional to
the square of the intrinsic carrier concentration and inversely proportional to the acceptor doping
concentration. Analogously, we can postulate that in the n-volume, the hole concentration is a
very small number (because of the high donor impurity concentration) given by the ratio of the
intrinsic carrier concentration squared to the donor concentration, N
D
. A studious inspection of
the diode abstracted in Figure (2.1a) for the specific case of v
d
(t) < 0 confirms the injection
across the PN junction of minority carriers. And as is the case for forward biasing, electrons
dominate minority carrier injection because of the relatively low acceptor concentration in the p-
type volume. We further note that the transport of an electron from the p-side of the junction to
the n-side supports current flowing from the n-side to the p-side, as does hole injection across the
junction from the n-side to the p-side. The superposition of the electrical effects of this low level
of minority carrier injection comprises the leakage current, I
o
, where the minus sign serves to
remind us that current I
o
flows the wrong way; that is, from the n-side of the junction to the p-
side. In short, diode current i
d
(t) is small (because of the low concentrations of minority carriers
on either side of the PN junction), but nonzero. Specifically, i
d
(t) ~ I
o
for values of reverse bi-
ased diode voltages that are reasonable in the sense that they do not exceed device breakdown
limitations. For minimal area diodes intended for high-speed signal processing utilization, I
o
is
as small as several femtoamperes
3
. Current I
o
is proportional to junction area A
e
, so that larger
diodes destined for high current applications have proportionately larger I
o
.
2.2.0. PN JUNCTION DIODE FUNDAMENTALS
Our initial foray into the world of electrical circuits likely initiated with a stipulation of
Ohms law, which effectively defined the volt-ampere characteristics of a simple two terminal
resistor. Coalescing this trivial volt-ampere relationship with a few fundamental circuit theory

3
Be advised that one femtoampere (1 fA) is equivalent to 10
15
ampere (10
15
A).

- 92 -

concepts, such as the Kirchhoff laws, superposition, and substitution, enabled out computation of
branch currents and voltages established by one or more energy sources applied to memoryless
networks; that is, circuit structures that are divorced of branch capacitances and inductances. In
somewhat of an analogous fashion, our introduction into the world of electronic circuits is a
disclosure of the low frequency volt-ampere properties of the semiconductor PN junction diode.
This volt-ampere characteristic equation is more complex than is Ohms law, if for no other rea-
son than the junction diode is an inherently nonlinear branch element. When coupled with clas-
sic circuit theories and such fundamental semiconductor concepts and issues as the junction
depletion region, junction transition capacitance, diode diffusion capacitance, built-in junction
potential, and charge transport and injection, the diode volt-ampere model enables the creative
exploitation of the PN junction diode in numerous applications, inclusive of those circuits and
systems that boast memory elements. It also helps to forge an insightful understanding of basic
semiconductor principles.
2.2.1. VOLT-AMPERE CHARACTERISTIC
If the diode depicted in either of the two diagrams of Figure (2.1) is inserted in a net-
work that is energized by only low frequency voltages or currents, the diode current, i
d
(t), relates
to the diode voltage, v
d
(t), in accordance with the nonlinear expression,
d T
v (t) nV
d o
i (t) I 1 , e
(
=

(2-1)
where the current, I
o
, is the diode saturation current introduced earlier in the context of diode re-
verse biasing. We note, in fact, that if v
d
(t) is strongly negative, (2-1) projects i
d
(t) ~ I
o
, as al-
rea. In (2-1), parameter n, which is known as the junction injection coefficient, is ideally one
and rarely larger than about 1.1. Moreover, the Boltzmann voltage, V
T
, is
T
kT
V ,
q
= (2-2)
where k = 1.38(10
23
) joules/K is Boltzmanns constant, T is the absolute temperature (meas-
ured in Kelvin degrees) of the semiconductor junction, and q is the magnitude of electron charge.
At T = 27 C = 300.16 K, V
T
= 25.89 mV, or about 26 mV. A temperature of 27 C is tradition-
ally adopted as the reference temperature for electronic circuit analyses. It is often referred to as
room temperature, even though 27 C is equivalent to an uncomfortably warm room held at a
temperature of about 81 F. It can be argued, however, that the internal junction of a diode,
which endures the thermal stress of power dissipation imposed by the high current densities con-
ducted by very small junction cross sections, operates at temperatures of at least 10 F -to- 15 F
above room ambient.
2.2.1.1. Static Volt-Ampere Model
Under static (DC) or low signal frequency operating conditions, the time dependence
of the diode voltage, v
d
(t), in (2-1) can be represented by simply a time-invariant voltage, V
d
.
Correspondingly, we can supplant the time domain diode current, i
d
(t), by the constant current
notation, I
d
. Accordingly, (2-1) assumes the slightly simpler form,
( )
d T
V nV
d o
I I 1 , e = (2-3)
which is plotted in Figure (2.2) for representative silicon and germanium PN junction diodes
operated at 27 C. The saturation current, I
o
, of the silicon diode in Figure (2.2) is taken as 2
fA, while the corresponding saturation current for the germanium unit is 1 A. For both diodes,

- 93 -

parameter n is taken to be unity. The huge disparity between I
o
values of silicon and germa-
nium diodes is typical. Observe that in both the silicon and germanium samples, the diode cur-
rent remains essentially zero despite positive, but small, values of the diode voltage. For the
subject germanium device, significant current is not observed until its diode voltage reaches a
level of nominally 200 mV, which might be interpreted as a turn on voltage, say V
on
, for the
device. On the other hand, about 700 mV of forward bias turn on is required for observable
current flow in the silicon unit. These differences in the diode voltage commensurate with
significant current flow can be attributed directly to the differences in the respective saturation
current values of the two diodes.
0
10
20
30
40
50
-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Di ode Vol tage, V
d
(vol ts)
D
i
o
d
e

C
u
r
r
e
n
t
,

I
d

(
m
A
)
Silicon
Diode
Germanium
Diode

Figure (2.2). The room temperature volt-ampere characteristics of representative PN junction diodes
fabricated in silicon and germanium technologies. Both diodes are presumed to project an
injection coefficient of n = 1. The silicon diode has a room temperature saturation current
of 2 fA, while its germanium cousin has a saturation current of 1 A.
We observe further that large diode currents do not require diode voltages that are
significantly larger than their respective turn on levels. For example, Figure (2.2) confirms that
the difference in voltage of the silicon diode biased at nominally 50 mA and then operated at
roughly 50 mA is less than 100 mV, or only about 14% of the 1 mA value of forward diode vol-
tage. In other words, only minutely small increases in diode voltage above the turn on threshold
result in significant increases in diode current, which is to say that the diode current is a sensitive
function of forward biasing diode potential. What a big surprise in view of the fact that diode
voltage V
d
appears as an exponentiation argument in its V-I characteristic equation of (2-3)!
Arguably, the forward diode voltage can therefore be viewed as remaining essentially constant at
a value very near to its turn on level for even substantive increases in diode current. In an idea-
lized sense, it might be suggested that the electrical behavior of a forward biased PN junction
diode approximates the volt-ampere characteristics of a battery whose potential is nominally the
diode turn on voltage, V
on
.
For both forward and reverse biases, the situation at hand is reminiscent of the biased
electrical switch diagrammed and characterized in Figure (2.3). In particular, the switch in the
subject figure is open, whence switch current I
sw
is zero, for V
sw
V
on
. On the other hand, I
sw
ex-

- 94 -

ceeds zero for the closed switch condition that delivers V
sw
= V
on
. This switch emulation can be
refined to account, albeit to first order, for the finite slope of the diode forward characteristic. To
this end, consider Figure (2.4), which depicts a typical volt-ampere characteristic of a diode,
regardless of the semiconductor technology exploited in its fabrication. Assume that the diode in
question is inserted into a circuit that allows a maximum diode current of I
dm
to flow. From (2-
3), this current corresponds to a forward diode voltage, V
dm
, which derives from
V V :
Switch Open
sw on
s
I = 0
sw
V
on
+ V
sw
V = V :
Switch Closed
sw on
I 0
sw
>
V
on
+ V
sw
V
sw
I
sw
V
on

Figure (2.3). Biased switch emulation of the volt-ampere characteristics of a PN junction diode.
( )
dm T dm T
V nV V nV
dm o o
I I 1 I . e e = ~ (2-4)
Diode Voltage
D
i
o
d
e

C
u
r
r
e
n
t
I
dm
V
dm
V
on
Actual Di ode
Characteri sti c
Pi ecewi se Li near
Characteri sti c

Figure (2.4). Piecewise linear approximation of the forward PN junction diode volt-ampere characteristic.
The approximation in (2-4) reflects the fact that the exponential term in the bracketed quantity is
significantly larger than unity when the diode is forward biased. Let a straight line be passed
through the coordinate, (I
dm
, V
dm
), such that the subject line is tangent to the diode characteristic
at (I
d
, V
d
) = (I
dm
, V
dm
). This slope, which has units of conductance, can logically be designated

- 95 -

by the inverse resistance notation, 1/r
dm
. Returning to (2-3),
d T dm T
d dm
d dm
V nV V nV
d o o dm
dm d T T T
V V
V V
dI I I I 1
,
r dV nV nV nV
e e
=
=
= = ~ (2-5)
whence
T
dm
dm
nV
r .
I
~ (2-6)
We see that (2-6) projects a diode resistance that is nominally inversely proportional to the diode
current. It therefore becomes progressively smaller as diode currents increase. Indeed, it is quite
small for both moderately large and relatively small currents owing to the fact that the numerator
term, nV
T
, on the right hand side of (2-6) is only about 26 mV at room temperature. Physically, it
represents the ratio of an incrementally small change, AV
d
, in the diode voltage -to- an incremen-
tally small perturbation, AI
d
, in corresponding diode current in the immediate neighborhood of
the volt-ampere coordinate, (I
dm
, V
dm
).
It follows that the equation of the straight line passed through the aforementioned volt-
ampere coordinate is
( )
d dm d dm
dm
1
I I V V .
r
= + (2-7)
The straight line intersects the horizontal axis in Figure (2.4) at V
d
= V
on
. From our earlier
discussion, voltage V
on
meaningfully approximates the turn on voltage of the diode. Since I
d
= 0
in the context of V
d
= V
on
, (2-7) and (2-6) provide
on dm dm dm dm T
V V r I V nV . = ~ (2-8)
It is both interesting and enlightening that the turn on voltage differs from the operating voltage,
V
dm
, of interest by a mere 26 mV or so at room temperature, which attests further to the pro-
nounced sensitivity of diode current to forward diode voltage. In a word, the steeper the volt-
ampere characteristic curve evidenced in a PN junction diode biased strongly in its forward re-
gime, the smaller is the static diode resistance, r
dm
, and the closer the operating voltage, V
dm
, lies
to the turn on voltage, V
on
.
It should be understood that (2-7) is a meaningful approximation of the volt-ampere
characteristics of a PN junction diode only if the diode voltage, V
d
, is at least as large as the volt-
age, V
on
, given by (2-8). Otherwise, the diode current is taken to be zero, which is an analytical
tack that ignores the small diode currents flowing for small positive values of diode voltage, as
well as the leakage current manifested when the diode is reverse biased. These pronouncements
lead to the piecewise linear approximation sketched in Figure (2.4), wherein a zero slope line,
coincident with the voltage axis, intersects a second line, defined analytically by (2-7), at V
d
=
V
on
. Specifically, the piecewise linear diode curve approximation is
( )
d on
d
dm d dm d on
dm
0, for V V
I . 1
I V V , for V V
r
<
~
+ >
(2-9)
Since each constituent of (2-9) is a linear equation, each can give rise to only a linear equivalent
circuit for the diode undergoing study. The equivalent circuit for the case of V
d
< V
on
is trivial in
that it is merely an open circuit, as shown in Figure (2.5a). With V
d
> V
on
, a constant current
source, a constant voltage source, and a resistance are required as we diagram in the topology
offered as Figure (2.5b).

- 96 -

I
d
+ V
d
V V
d on
s
I = 0
d
+ V
d
(a).
I
d
+ V
d
V V
d on
>
I
d
+ V
d
(b).
V
d
m
I
d
m
r
dm

Figure (2.5). Piecewise linear, low frequency model of the PN junction diode. (a). The piecewise li-
near (open circuit) model corresponding to a diode voltage that is at most equal to the
turn on voltage of the device. (b). The piecewise linear model for a diode voltage that is
at least the diode turn on voltage.
EXAMPLE #2.1:
In the simple circuit of Figure (2.6a), the PN junction diode, D, is fabricated in
silicon semiconductor technology and operates at room temperature. Its static
volt-ampere curve is characterized by a junction injection coefficient of n = 1.03
and a saturation current of I
o
= 4.2 fA. The battery voltage applied to the circuit
is V
dd
= 3 V, while the load resistance is R
l
= 150 O. Use the piecewise linear
model of a diode to calculate the diode current, I
d
, the diode voltage, V
d
, and the
load voltage, V
l
.

V
dd

R
l
D
V
d
+
I
d
V
l
(a).
I
d
+ V
d
V
d
m
I
d
m
r
dm
R
l
V
l

V
dd

(b).

Figure (2.6). (a). Circuit addressed in Example (2.1). (b). The piecewise linear model of the circuit in (a).
SOLUTION #2.1:
(1). We can see that the supply voltage, V
dd
, serves to forward bias the diode in the circuit at hand.
Accordingly, our applicable model is the structure in Figure (2.5b), which supplants diode D
in the circuit of Figure (2.6a) to establish the network given in Figure (2.6b). The practical
use of this model begins with estimating the maximum possible current, I
dm
, which the diode
in Figure (2.6a) can conduct. A reasonable first guess of this maximum current is V
dd
/R
l
,
which is the current that would flow if the diode were to behave as a short circuit; that is, a
diode boasting zero turn on voltage and infinitely large slope of the forward volt-ampere
characteristic curve. But PN junction diodes have a nonzero turn on voltage commensurate

- 97 -

with the conduction of measurable current. In silicon, a reasonable approximation of the di-
ode turn on voltage is V
on
= 700 mV. Thus, a better second guess as to the maximum current
the circuit of Figure (2.6a) is capable of conducting is
dd on
dm
l
V V
I 15.33 mA .
R
= = (E1-1)
The diode voltage, V
dm
, corresponding to this estimated maximum current is, from (2-4),
dm dm
dm T T
o o
I I
V nV 1 nV 771.32 mV .
I I
ln ln
| | | |
= + ~ =
| |
\ . \ .
(E1-2)
The unity term within the parenthesized factor on the right hand side of the last equation can
be ignored comfortably in that I
dm
>> I
o
. Finally, (2-6) gives for the series diode resistance,
r
dm
,
T
dm
m
nV
r 1.74 .
I
= = (E1-3)
(2). Kirchhoffs current law applied to the equivalent circuit in Figure (2.6b) yields a diode cur-
rent, I
d
, which satisfies
dd dm l d
d dm
dm
V V R I
I I ,
r

= + (E1-4)
whence
dm dd dm
d dm
dm l dm l
r V V
I I 14.86 mA .
r R r R
| |
= + =
|
+ +
\ .
(E1-5)
The load voltage, V
l
, follows as
l l d
V R I 2.23 V , = =
(E1-6)
while the corrected diode voltage, V
d
, is necessarily equal to
d dd l
V V V 770.51 mV . = =
(E1-7)
ENGINEERING COMMENTARY:
Two noteworthy points surface from this example. The first of these is that while the piece-
wise linear model is an approximation in that it effectively supplants the forward bias diode
volt-ampere curve by a straight line, it nonetheless is capable of reassuringly accurate
computations. In the present case, a computer-based simulation of the network in Figure
(2.6a) reveals a diode voltage of 770.49 mV, which differs from the computed result by a
miniscule 0.002%. The same simulation confirms that the computed current is high by only
0.015%. These errors are orders of magnitude smaller than analytically deduced response er-
rors accruing from the ramifications of routine processing and manufacturing uncertainties.
Of course, the accuracy of the response results hinges largely on the estimate adopted for the
current, I
dm
. In particular, the closer I
dm
is to the actual diode current, the more accurate are
the computed results. Equation (2-7) supports the last contention, for in the limit if I
dm
is esti-
mated to be the actual diode current, I
d
, V
dm
follows as the actual diode voltage, V
d
.
The second point is that the obviously nonlinear electronic circuit at hand has been analyzed
accurately with the help of only an approximate, linear circuit model. Of course, the vehicle
fostering the propriety of this linear approximation is the applied battery voltage, V
dd
, which
forces the PN junction diode to operate above its turn on threshold potential and therefore,
away from the nonlinearities implicit to the neighborhood of the turn on voltage. The lesson
worthy of learning is that traditional linear circuit theory and analytical techniques remain
crucially important to an analytical assessment of electronic networks, despite their inherent
nonlinearity. In other words, once we formulate a meaningful and realistic model for the

- 98 -

nonlinear element (or nonlinear elements in more complicated networks), electronic circuit
investigations collapse to sophomoric circuit analytical undertakings.
2.2.1.2. Diode Saturation Current
The saturation current parameter, I
o
, has at least two important properties that influence
design practices for electronic networks exploiting BJTs, MOSFETs operating in their subthre-
shold regimes, and, of course, PN junction diodes. The first of these characteristics is that I
o
is
directly proportional to the cross section area, A
e
, of the semiconductor junction. Consider, for
example, the network in Figure (2.7a), which offers a static circuit wherein two PN junction dio-
des are connected in parallel with one another. We assume that the two diodes are physically the
same except for the fact that the junction cross section area of diode D2 is larger than that of di-
ode D1 by a factor of k. Because of the shunt interconnection of the two diodes, the same static
voltage, V
d
, forward biases the two PN junction diodes. If the passive series resistances (termed
ohmic resistances) associated with the charge neutral regions of the p-type and n-type layers of
the diodes are their stereotypical small values, the voltage drops incurred across these resistances
by diode currents are significantly smaller than the internal junction voltages of the diodes. This
means that if the parasitic diode resistances are small, the indicated terminal voltage, V
d
, is effec-
tively the forward biased junction voltage of either diode. But from (2-3), if diode D2, whose
junction area is scaled k-times upward from that of diode D1, shares the same internal junction
voltage that is experienced by D1, diode D2 necessarily conducts a current that is k-times the
current flowing through D1. In effect, diode D2 mirrors the current of D1 through a scale factor
of k. Resultantly, the applied voltage source, V
dd
, must supply a current that is a factor of (k +1)-
times larger than the current conducted by diode D1. Of course, the circuit in Figure (2.7a) per-
forms similarly to the single diode circuit in Figure (2.7b), where the lone diode, D3, is fatter
than diode D1 by a factor of (k + 1).

V
dd

R
D1 D2
x k
kI
d1
I
d1
V
d
(k+1)I
d1
(a).

V
dd

R
D3
x (k+1)
(k+1)I
d1
V
d
(k+1)I
d1
(b).
x 1
+

Figure (2.7). (a). A circuit that has two PN junction diodes connected in shunt with one another. The
junction area of diode D2 is k-times larger than the junction cross section area of diode D1.
(b). The single diode equivalent of the circuit in (a) is which the utilized diode, D3, has a
junction area that is (k +1)-times larger than the junction area of diode D1.
The fact that the larger area diode conducts larger current is hardly revolutionary. For
example, prudence dictates that we use progressively thicker wire to conduct larger currents. By
selecting a wire with large cross section area, the net resistance through which current is allowed
to flow is reduced. And in addition, the heat generated by any power that happens to be dissi-
pated in this resistance is effectively spread over a larger area, thereby reducing the thermal
stress per unit of cross section area. In a word, we attempt to do with both diodes of increased
cross section area and fatter wires is to sustain reasonable current densities, thereby allowing the
power dissipated by the conducting current to be distributed over wider cross section areas.
The second important property of diode saturation current I
o
relates to junction operat-

- 99 -

ing temperature. In contrast to the designable advantage of saturation current proportionality to
junction area, I
o
exudes a troublesome temperature sensitivity that is the bane of integrated cir-
cuit designers. Current I
o
is, in fact, the leakage current that flows through a reverse biased di-
ode. As we argued earlier, this leakage derives from minority charge carriers injected across the
diode junction. Because the concentration of these minority carriers is directly proportional to
the square of the intrinsic carrier concentration, which rises dramatically with increases in junc-
tion operating temperature, the leakage current is itself strongly dependent on junction operating
temperature. Accordingly, diode currents exude a positive temperature coefficient. In particular,
diode currents tend to increase over temperature, because of the dependence of current parameter
I
o
on junction temperature.
The mathematical nature of the temperature dependence of I
o
can be addressed empiri-
cally by the expression,
( )
o
T T 10
o o o
I (T) I (T ) P ,
(
~
(

(2-9)
which asserts that the diode saturation current, I
o
(T), at an arbitrary absolute operating tempera-
ture of T increases from its reference value of I
o
(T
o
) by a factor of P for each 10 C rise in junc-
tion temperature. Absolute reference temperature T
o
is generally taken to be 27 C, I
o
(T), and P
is an empirical parameter ranging typically from 2 -to- 5 in silicon devices. Thus, for example, if
P = 3.5, the leakage or saturation current, I
o
(T), at a temperature that is 50 C above room
temperature is a factor of 525.2 larger than its reference temperature value. In the context of the
circuit in Figure (2.7a), suppose that the voltage, V
d
, is maintained constant over a 50 C in-
crease. In the face of constant diode junction voltage, the resultant current conducted by resis-
tance R in Figure (2.7) would increase by a factor of 525.2. This means that the supply voltage,
V
dd
, and thus, the power it must supply to the circuit, needs to be increased commensurately over
temperature to sustain the desired reference temperature value of the current flowing through the
shunt-connected diodes. This simple example indicates that maintaining constant diode voltage
in the face of junction temperature rises is an imprudent design option.
The disconcerting aspect of the foregoing example is that while a 50 C rise in junction
temperature is large, it is a commonly encountered increase when small geometry devices are
compelled to conduct moderately large currents. In particular, the high current densities expe-
rienced by small profile diodes incur self heating of their respective geometries. As we alluded
to earlier, this state of affairs encourages the use of relatively large geometry diodes when
correspondingly large currents must be conducted. Large cross section areas reduce current
densities, which in turn mitigate junction temperature rises incurred by unavoidable self heating.
Just as a high gauge (small cross section area), extension cord becomes dangerously hot when it
connects a power hungry appliance, such as a toaster or space heater, to a power source, small
diodes conducting large currents can likewise be damaged by the internal heat manifested by the
junction power dissipation associated with large current densities.
A casual inspection of (2-3) suggests the need of appropriately decreasing the diode
voltage to compensate for temperature-induced increases in the saturation current parameter, I
o
.
In order to ascertain the voltage decrease commensurate with sustaining constant diode current in
the face of temperature rises, let us assume a PN junction diode energized by a static voltage that
secures strongly forward biased operation. In this case, the exponential term on the right hand
side of (2-3) overpowers the unity term in the bracketed quantity so that at temperature T,
d T
V (T) nV
d o
I (T) I (T) , e ~ (2-10)

- 100 -

while at reference temperature T
o
,
d o To
V (T ) nV
d o o o
I (T ) I (T ) , e ~ (2-11)
where
o
To
kT
V
q
= (2-12)
is the reference temperature value of the Boltzmann voltage, V
T
. Since our present goal is to
determine the amount by which the forward bias diode voltage, V
d
(T), must decrease from its
reference value, V
d
(T
o
), to ensure that the diode current at temperature T is nominally the same as
the current at temperature T
o
, I
d
(T)/I
d
(T
o
) = 1. Accordingly, if we divide (2-10) by (2-11) and
subsequently use (2-9), we find that
( )
T 10 d d o
T To
V (T) V (T )
1 P ,
nV nV
exp
(
=
(

(2-13)
where
o
T T T (2-14)
is the temperature change experienced by the diode junction. Equations (2-12) and (2-13) and a
bit of algebra invoked on the bracketed term on the right hand side of (2-13) allows us to write
( )
T 10
d d o
T o
1 T
1 P V V (T ) ,
nV T
exp

( | |

=
` | (
\ . )
(2-15)
with
d d d o
V V (T) V (T ) (2-16)
understood to represent the required change in diode voltage. Upon taking the natural logarithm
of both sides of (2-15),
( ) ( )
1 10 1 10 d d o d o
T To
o o o
V V (T ) V (T ) T
nV P nV P
T T T T
ln ln
| |
= =
|
\ .
(2-17)
is readily demonstrated.
The quotient, AV
d
/AT, in (2-17) is the average temperature rate at which diode voltage
V
d
must change to preserve constant diode current over the temperature increment, AT. Observe
that this average rate of voltage change is a linear function of operating temperature, T. Note
further that even if P = 1, which implies the highly idealized condition that saturation current
I
o
(T) is not influenced by temperature, the temperature dependence of the Boltzmann voltage
renders AV
d
nonzero and indeed positive for AT > 0. For P > 1, the second term on the right
hand side of (2-15) is invariably larger than the first term so that AV
d
/AT is a negative number in
units of volts -per- C. The typical magnitude of this voltage sensitivity for AT > 0 and for sili-
con PN junction diodes is in the range of 1.0 mV/C -to- 3 mV/C.
Figure (2.8) portrays the pronounced temperature sensitivity of the static volt-ampere
characteristic of a PN junction diode. The curves displayed plot (2-3) for a 27 C saturation cur-
rent value of I
o
(T
o
) = 2 fA, a junction injection coefficient of n = 1, and a temperature parameter
of P = 3.5. The plot clearly conveys the necessity of decreasing junction voltage V
d
if the diode
current, I
d
, is to be maintained nominally constant in the face of increasing junction operating
temperatures. We also offer Figure (2.9) as a companion to Figure (2.8). The latter plot dis-
plays, as a function of junction temperature, the temperature sensitivity of diode voltage, AV
d
/AT, which is required to sustain nominally constant diode current despite increases AT in the

- 101 -

junction operating, T. The plot takes n = 1, T
o
= 27 C, and a reference temperature diode vol-
tage of V
d
(T
o
) = 730 mV. As expected, these curves project temperature linearity with a negative
slope.
0
10
20
30
40
50
60
70
80
90
100
-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Di ode Vol tage, V
d
(vol ts)
D
i
o
d
e

C
u
r
r
e
n
t
,

I
d

(
m
A
)
T = 27 C
T = 75 C
T = 125 C

Figure (2.8). The volt-ampere characteristic of a PN junction diode for three values of
junction temperature. The considered diode has n = 1, a reference tempera-
ture, T
o
, of 27 C, a saturation current, I
o
(T
o
), at the reference temperature of
2 fA, and P = 3.5.
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
J
u
n
c
t
i
o
n
V
o
l
t
a
g
e
S
e
n
s
i
t
i
v
i
t
y
(
m
V
/
C
)
Junction Temperature ( C)

Figure (2.9). The temperature rate of diode voltage change required to preserve nomi-
nally constant voltage change in light of the strong sensitivity of diode
saturation current to junction operating temperature.
EXAMPLE #2.2:
In the circuit of Figure (2.7), diode D1 has a saturation current, I
o
, of 5 fA at
room temperature. Diode D2 is identical to D1 except that its junction area is 5-
times larger than that of D1. Both diodes have a junction injection coefficient of
n = 1 and a temperature factor of P = 4. The applied voltage, V
dd
, is 6 volts and

- 102 -

supplies 18 mA of current to the circuit. What is the required value of resistance
R, and what is the average rate at which V
dd
must decrease if the current supplied
by V
dd
is to remain 18 mA when the diodes operate at 100 C. Assume that
temperature-induced changes in the value of circuit resistance are negligible.
SOLUTION #2.2:
(1). If the supply voltage provides 18 mA of current to the circuit of Figure (2.7), and if diode D2
has a junction area that is 5-times the area of D1 (k = 5), diode D1 must conduct a current of
I
d1
= 18 mA/(k+1) = 18 mA/6 = 3 mA. From (2-3), the voltage, V
d
(T
o
), developed across ei-
ther diode is, for I
d1
(T
o
) = 3 mA, I
o
(T
o
) = 5 fA, n = 1, and T
o
= 27 C,
d1 o
d o To
o o
I (T )
V (T ) nV 1 702.11 mV .
I (T )
ln
| |
= + =
|
\ .
(E2-1)
(2). Kirchhoffs voltage law applied to the lone circuit loop in the subject figure yields
dd d o
d1 o
V V ( T )
R 294.33 .
( K 1)I (T )
= =
+
(E2-2)
(3). Since resistance R boasts ideally zero temperature coefficient, the decrease in supply voltage
must match the decrease in the diode voltage commensurate with maintaining the constant
current that the voltage source attempts to supply. With V
d
(T
o
) = 702.11 mV, P =4, T
o
=
300.16 K, and a maximum operating temperature of T = 100C = 373.16 K, (2-17) pro-
vides
( )
1 10 dd d d o
T
o
V V V (T )
nV P 2.123 mV/C .
T T T
ln = =
(E2-3)
This computation implies that over the temperature range of 27 C -to- 100 C, the supply
voltage must diminish by (2.123)(100 27) = 154.96 mV, which amounts to a decrease of
2.58%.
The bad news is that the diode currents are strongly sensitive functions of junction operating
temperatures. But the good news is that diode currents are strongly sensitive functions of di-
ode voltages to which they are exponentially dependent. Since a diode current is impacted by
temperature largely through the saturation current parameter to which a diode current is
directly proportional, only small changes in diode voltage are necessary to compensate for the
ramifications on saturation current of increasing junction operating temperature. In the
present example, less than a 2.6% drop in applied voltage stabilizes the current supplied by
the power supply in the circuit of Figure (2.7). The real engineering challenge, however, is
designing the voltage source so that it can sense temperature-induced current changes and
track automatically with requisite changes in diode voltage.
2.3.0. PHYSICAL CONSIDERATIONS OF THE PN JUNCTION
In addition to having presented the static volt-ampere characteristics of the PN junction
diode, several engineering issues surrounding these characteristics have been addressed. In-
cluded among these issues are diode conduction requirements, a circuit level assessment of the
sensitivity of diode characteristics to junction temperature, and a piecewise linear model that
enables a systematic and straightforward analysis of PN junction diode circuits. Armed with a
comprehension of these issues and their associated mathematical tools, we are arguably prepared

- 103 -

to analyze networks that utilize PN junction diodes and perhaps even to design simple diode
subcircuits that support particular system performance requirements. But a prerequisite for in-
sightful analyses and innovative circuit design, and particularly integrated circuit design, requires
more expertise than that associated with our limited awareness of only fundamental device
properties. In effect, the understanding we have gleaned thus far has provided us with only the
training wheels that can initiate our guarded travel along the road to innovative and creative de-
sign of reliable electronic networks. These trainers can be discarded when manual analysis suc-
ceeds in meaningfully illuminating the performance attributes and shortfalls of considered cir-
cuits to the appropriate physical properties of the active devices and their interconnections. To
be sure, many of the performance characteristics of electronic circuits may be explained in terms
of only the engineering fundamentals of semiconductor devices and their peripheral branch ele-
ments. Unfortunately, practical electronic shortcomings often ensue from the electrical effects of
second order, and generally undesirable and unwelcomed, phenomena that are rarely rendered
visible by discussions that are limited to only basic volt-ampere properties. At a minimum, a
consideration of these higher order effects adds realism to, and enhances our understanding of,
the fruits of basic analysis. In other circumstances, the creative exploitation of these high order
phenomena can mitigate at least some of the shortfalls revealed by first order circuit analyses.
An examination of the higher order phenomena pervasive of PN junction diodes boasts the addi-
tional advantage of facilitating our engineering understanding of the operation of more compli-
cated electronic devices.
The discovery of relevant high order phenomena that loom potentially significant to cir-
cuit performance compels a discussion of the physical characteristics of the semiconductor di-
ode. In an attempt to forestall intimidation among those who are myopically focused on elec-
tronic circuits, as opposed to physical electronics, the discussion that follows exploits only the
essential mathematics that quantify the physics of semiconductor device operation. These
mathematical considerations are complemented by engineering discourse, which is directed to-
ward assimilating the circuit level impact of relevant physical phenomena. Take comfort in the
fact that this author can hardly be viewed as an expert on semiconductor physics.
2.3.1. PN JUNCTION AT EQUILIBRIUM
Before beginning a quantitative discussion of the physical properties of a PN junction
diode, a few basic qualitative observations prove useful. First, we can easily comprehend that a
semiconductor diode that is merely placed on the laboratory bench without any connection to a
voltage source or other source of energy cannot conduct current. In other words, if the terminals
of a diode are left open circuited, the diode is incapable of supporting current flow. But second,
we may encounter difficulty understanding that this zero conduction state is seemingly
inconsistent with our elementary picture of a diode that simply projects a p-type region abutting
an n-type volume at something we have called the PN junction. In particular, there is a bunch of
positively charged holes in the p-type volume, while more bushels of negatively charged
electrons pervade the n-type region. Since positive and negative mobile charges mutually attract
one another, presumably nothing hinders an n-volume electron from attracting a p-region hole
across the junction. Conversely, any p-region hole can encourage the transport of an n-region
electron across the junction and into the p-region. We perceive this seemingly innocent picture
as physically sound until such time that we remember that charges piercing a cross section of
semiconductor or any other type of potentially conductive material comprise flowing electrical
current. But since the PN junction diode we are envisaging is not connected to any closed
electrical path, Kirchhoff insists that no such current flow is possible.

- 104 -

The quandary with our initial vision of a PN junction diode is that the proximate
location of holes and electrons in the neighborhood of a geometric PN junction is that current
flow is physically encouraged in a Kirchhoff electrical environment that absolutely prohibits
such flow. Now, we are logically forced to conclude that some type of phenomenon takes place
in the immediate neighborhood of the PN junction to separate holes and electrons, thereby
precluding their mutual attraction. In the absence of this attraction, transport across the junction,
whence current flow through an open circuited PN junction diode is inhibited. A vague clue as
to the nature of this requisite higher order phenomenon is offered by our fundamental
understanding that the presence of nonzero charge manifests an electric field, which when
appropriately directed, can hinder mobile charge transport over the region in which the field
prevails. The subsequent paragraphs consider this phenomenon and in the process, our
perception of the physical nature of the junction region of a diode is widened.
Our quantitative discussion commences with an investigation of the PN junction diode
at equilibrium; that is, the diode in Figure (2.1) is operated with no voltage, light, or other form
of external energy applied to it. The diode is effectively open circuited and consequently, zero
diode current, i
d
(t), prevails. As alluded to earlier in this chapter, diode current is comprised of a
superposition of currents precipitated by hole and electron injection across the PN junction.
Recall that holes injected from the p-type region to the n-type layer and electrons injected in the
opposite direction from the n-type region to the p-type layer combine to give rise to a current
flowing from the p-side of the junction to the n-side. Accordingly, the zero current equilibrium
condition demands that the current components due to both hole and electron injection across the
junction be shut down.
The hole current, say I
dp
, is, in turn, a superposition of drift and diffusion components,
which we denote herewith as I
pdrift
and I
pdiff
, respectively. In particular,
dp pdrift pdiff
I I I = + (2-18)
where the drift component of hole current is
pdrift e p
I A qp(x) (x) (x), = E (2-19)
and the hole diffusion current is
pdiff e T p
dp(x)
I A qV (x) .
dx
= (2-20)
We note that if the hole concentration gradient, dp(x)/dx, is negative, we witness a positive
diffusion current, I
pdift
. In the last two expressions, A
e
, q, and V
T
are the previously introduced
junction cross section area, electron charge magnitude, and Boltzmann voltage, respectively. In
addition, p(x) is the concentration of mobile holes as a function of position x in Figure (2.1a),
p
(x) symbolizes hole mobility (in units of cm
2
/volt-sec), and E(x) is the electric field intensity
(in units of volts/cm) prevailing at position x in the subject diagram. The hole mobility (as well
as the electron mobility) is dependent on position x by virtue of the fact that mobility is a
function of carrier concentration, which varies with position x. Since the hole current component
is zero at equilibrium, (2-18) through (2-20) confirm a requisite internal electric field intensity of
| |
T
d p(x)
(x) V .
dx
ln
= E (2-21)
In other words, a nonzero electric field must prevail to establish equilibrium. This field is
proportional to both junction temperature and the slope of the natural logarithm of the hole
concentration. As we demonstrate subsequently, the subject electric field is dominantly confined
to the immediate neighborhood of the junction.

- 105 -

Analogously, the electron component, I
dn
, of diode current is expressible as
dn ndrift ndiff
I I I , = + (2-22)
where the drift component of electron current is
ndrift e n
I A qn(x) (x) (x), = E (2-23)
and its diffusion component is
ndiff e T n
dn(x)
I A qV (x) .
dx
= (2-24)
In (2-23) and (2-24), n(x) represents the free electron concentration, while
n
(x) is the position
dependent electron mobility. The last three relationships confirm that zero electron current
mandates an electric field intensity of
| |
T
d n(x)
(x) V .
dx
ln
= E (2-25)
The last result and (2-21) combine to stipulate that diode equilibrium is achieved when the slopes
of the logarithmic profiles of the hole and electron concentrations adjust to satisfy the constraint,
| | | |
d p(x) d n(x)
.
dx dx
ln ln
= (2-26)
2.3.1.1. Junction Transition Region
The simplicity of the equilibrium condition in (2-26) masks important engineering an-
swers to questions as to how an electric field that is internal to the PN junction diode can be
formed to stop charge transport across the junction when no energy is applied to the diode. This
question is best addressed by examining the nature of the free carrier profiles in the PN junction
device of Figure (2.1a). To this end, assume that the p-type region is doped uniformly to an
acceptor carrier concentration of N
A
4
. It follows that on the p-side of the junction and suffi-
ciently removed from said junction, the hole concentration is p(x) N
A
, assuming complete
ionization of the introduced acceptor impurity atoms. But on the n-side of the junction and far
enough away from the actual PN junction, where holes are minority carriers, p(x) n
i
2
/N
D
, where
n
i
is, of course, the intrinsic carrier concentration. The resultant hole profile is sketched in Fig-
ure (2.10a), which clearly shows that in the vicinity of the junction, the hole concentration
necessarily transitions from the large value evidenced for on the p-side of the junction for x <
X
po
to its substantially smaller value of n
i
2
/N
D
on the n-side of the junction where x > X
no
. Al-
though the transitional curve in Figure (2.10a) is delineated as a straight line, its actual
mathematical nature is an error or Gaussian function, depending on the nature of the doping
methodology adopted in the fabrication process. The boundaries of the junction transition region
defined by X
po
x X
no
are also dependent on the device fabrication scenario but in general,
the equilibrium width, W
o
, of the transition region is rarely more than a half micron or so. This
declaration, coupled with the fact that N
A
commonly exceeds n
i
2
/N
D
by several orders of magni-
tude implies that the slope of the transitional hole profile in the immediate vicinity of the PN
junction is both negative and very large in magnitude. It follows from Figure (2.10a) and (2-21)
that an electric field, E(x), which is established in association with the hole profile, is
commensurately large and negative near the junction and is essentially zero far enough away
from the junction. A large electric field derives from the steepness of the free hole profile in the
junction transition region, while a negative field, which implies a field directed from the n-side

4
Uniform doping can be achieved through ion implantation of the dopant.

- 106 -

of the junction to the p-side, accrues because of the obviously negative slope of the hole profile.
As such, this internally established built-in field exerts a force on free holes that effectively
confines them to the p-type volume of the PN junction diode. More about these electric fields is
offered subsequently.
x
p(x)
X
po
X
no
N
A
n /N
i D
2
0
(a).
x
n(x)
X
po
X
no
N
D
n /N
i A
2
0
(b).
W = X +X
o no po

Figure (2.10). (a). Simplified depiction of the free hole profile of a PN junction diode in
equilibrium. (b). Simplified diagram of the free electron profile of a PN junc-
tion diode in equilibrium.
Analogously, the free electron profile, which we sketch in Figure (2.10b), varies from a
constant of n
i
2
/N
A
for x < X
po
to a high value of approximately N
D
for x > X
no
. As in the case of
the free hole curve, a straight line is adopted to represent the electron profile in the junction
transition domain. Since the slope of the indicated straight line is large and positive, (2-25) sug-
gests a proportionately large and negative equilibrium electric field in the neighborhood of the
junction, while the field in regions removed from the junction approach zero. Again, more about
these electric fields is offered subsequently.
In order that a negative electric field, E(x), be established in the neighborhood of the
PN junction to inhibit hole/electron transport and sustain the equilibrium condition, a positive
charge must prevail to the right of the junction, and a negative charge must be observed to the
left of the junction. This contention stems from the elementary picture of field lines emanating

- 107 -

from positive charges and terminating on negative counterparts. On either end of the
semiconductor outside of the transition region abstracted in Figure (2.10), the net charge must be
zero because in equilibrium, the hole and electron densities are constant, thereby forcing zero
electric field in these domains at equilibrium.
In general, the net charge, say (x), is comprised of free holes, free electrons, ionized
donor atoms, and ionized acceptor atoms. This is to say that
| |
D A
(x) q p(x) n(x) N N . = + (2-27)
In this simple relationship, p(x) is the concentration of free holes, n(x) represents the concentra-
tion of free electrons, N
D
symbolizes the concentration of ionized donor atoms (a positive
charge), and finally, N
A
is the concentration of ionized acceptor atoms (a negative charge). To
the extent that the concentration of donor and acceptor atoms is a constant, independent of
geometrical position x, the charge concentration signified by the bracketed quantity on the right
hand side of (2-27) reflects the net positive charge density at position x. Since (x) = 0 outside
the transition region at equilibrium,
D A po no
p(x) N n(x) N for x X and x X + = + < > (2-28)
But on the p-side of the junction where X
po
x 0, there are no donor impurities, and the
concentration of electrons, which are the minority carriers in the p-side of the junction, is minis-
cule in comparison to the concentration of ionized acceptor impurities. On the other hand, no
acceptor impurities reign, and the concentration of minority holes is far smaller than the
concentration of ionized donor impurity atoms, on the n-side of the transition layer. Accor-
dingly,
| |
| |
A po
D no
q p(x) N , X x 0
(x) .
q N n(x) , 0 x X
s s
=
s s
(2-29)
From Figure (2.10), it should be noted that p(x) < N
A
in the transition region immediately to the
left of the junction, while in the transition region to the immediate right of the PN junction, N
D
>
n(x). This observation is important for it confirms the existence of a net negative charge imme-
diately to the left of the junction and a net positive charge to the right of said junction. In turn,
these negative and positive charges provide the electrostatic foundation to support the negative
electric field in the transition region (meaning that field lines are directed from the n-side of the
junction to the p-side) that is required to sustain diode equilibrium.
In summary, the transition region that cloaks the PN junction of a semiconductor diode
is the vehicle that establishes electrical equilibrium in a diode that lies dormant as an open cir-
cuited device. It accomplishes this feat by establishing a region of net negative charge on the p-
side of the junction, immediately to the left of the physical junction and a similar region of net
positive charge immediately to the right of the junction. These charge regions give rise to an
electric field directed across the PN junction from the n-side -to- the p-side. Although not expli-
citly discussed, this electric field manifests a potential, known as the built-in junction potential,
across the junction and polarized positive on the n-side and negative on the p-side. The
establishment of this voltage derives from the simple fact that voltage potential is little more than
the integrated electric field formed across the region over which the potential is developed. In
turn, the positive potential on the right side of the PN junction inhibits the transport of positively
charged holes from the p-side of the junction -to- the n-side. Moreover, said potential also serves
to block negatively charged electrons from coming across the junction to the p-side from the n-
side. And when the transport of both holes and electrons are blocked, no current can flow. It is
important to understand that the condition of zero current in a PN junction diode requires stop-

- 108 -

ping the transport across the junction of both holes and electrons since holes moving from the p-
side of the junction -to- n-side incur a current flow from p-side -to- n-side as do negatively
charged electrons jogging from n-side -to- p-side.
2.3.1.2. Depletion Approximation
On the p-side of the junction transition region, the observed charge is negative; it is, in
fact, a very good approximation of a constant (independent of position x) negative charge. Simi-
larly, the charge to the immediate right of the PN junction is a very good approximation of a con-
stant positive charge. We arrive at these approximations because on the p-side of the junction,
the concentration, p(x), of free holes drops dramatically and almost abruptly from its high value
of N
A
to its significantly smaller (by several orders of magnitude) value of n
i
2
/N
D
over a transi-
tion region width, W
o
, which is of the order of at most a half micron. Moreover, on the n-side of
the transition region, the concentration of free holes, n(x), likewise falls precipitously as we ap-
proach the PN junction from the right. These observations, coupled with (2-29), strongly suggest
the feasibility of approximating the charge population on the p-side of the transition region
exclusively by the charge associated with ionized acceptor impurity atoms while on the n-side,
the charge population can be represented as the charge associated with ionized donor impurities.
Formally, the depletion approximation reflects the presumptions, p(x) << N
A
and n(x) << N
D
in
the transition region, so that (2-29) simplifies to
A po
D no
qN , X x 0
(x) .
qN , 0 x X
s s
~
s s
(2-30)
Although the algebraic approximations leading to (2-30) are trivial, the understanding
of the resultantly approximated charge profile can prove elusive without a bit of further engineer-
ing thought. To this end, recall that the junction transition region of width W
o
supports an elec-
tric field, and thus, a built-in junction potential, say V
j
, which is positive on the n-side of the
physical PN junction with respect to the p-side of said junction. Voltage V
j
inhibits the flow of
holes from the p-side -to- the n-side. This voltage accomplishes this deed by serving as the
source of energy that pushes free holes further away from the physical PN junction and thus dee-
per into the p-type volume. In other words, getting these free charges away from the junction is
a proactive way of discouraging them from socializing with the electrons on the right of the PN
junction. But since the region about the junction are initially charge neutral, as implied by (2-
27), every displaced positively charged hole must leave behind a negative charge. This negative
charge is an ionized acceptor atom; that is, an originally charge neutral acceptor atom that has
begrudgingly released a positively charged hole. Given an average p-side acceptor concentration
of N
A
, we would therefore naturally expect on average a net ionized charge of qN
A
to be mani-
fested in the transition region immediately to the left of the junction.
A similar situation is experienced by the electrons to the immediate right of the junc-
tion. In this case, the negative polarity of voltage V
j
on p-side repels negatively charged elec-
trons deeper into the n-type volume. Every departing electron leaves behind a positive ionic
charge. It follows that on average, an ionic charge concentration of qN
D
is established in the
transitional region immediately to the right of the physical PN junction. It is important to
underscore the fact that these foregoing charges are ionic charges. They are therefore immobile,
which is to say that they are incapable of contributing to current flow.
The transition region addressed above is often referred to as a depletion zone or region,
presumably because at equilibrium, the region to the left of the PN junction is divorced of free

- 109 -

hole charges. Similarly, free electrons are absent in the proximate depletion zone to the right of
the junction. But it is crucial that we understand that the transition, or depletion, region is not
free of charge. There is acceptor ionic charge on the p-side and ionized donor charge on the n-
side. Thus, we might quip that the transition region is home to useless charge in the sense that
that because of its ionic immobility, it is incapable of contributing to diode current flow. In fact,
if these ionic charges were mobile, rupturing of the covalent bonds that hold the ions in their
respective atomic places has taken place, presumably because of the application of an excessive
level of junction voltage. In effect, the semiconductor crystal is being destroyed by improper
voltage biasing.
i (t)
d
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +

= 0
x
0 W
n
W
p
X
po
X
no
Acceptor
Ions
Donor
Ions Junction
Transition Region
W
o

Figure (2.11). Abstraction of a PN junction diode in equilibrium, wherein the depletion approximation is
invoked over the junction transition region. The only charges prevailing within the transi-
tion volume are those associated with immobile, ionized impurity atoms.
The ramifications of (2-30) and the preceding three paragraphs are abstracted in Figure
(2.11), which highlights a PN junction transition layer that is divorced of mobile charge carriers
under equilibrium conditions. Specifically, the transition region to the left of the junction is
filled with the negative charges associated with ionized acceptor atoms, while the transition layer
to the immediate right of the junction is a lake of positive charges deriving from ionized donor
impurities. The depletion approximation is obviously suspect at each of the two transition layer
boundaries; that is, at x = X
po
and at x = X
no
. Suspicions are justifiably aroused as well at the
origin, x = 0, where the charge distribution model of (2-30) produces a charge profile changing
abruptly from qN
A
at x = 0 to +qN
D
at x = 0+. Misgivings notwithstanding, Figure (2.11)
conveys an elegantly simple, albeit approximate, picture of the equilibrium condition. In particu-
lar, the negative ionic charge to the left of the junction repels any free electrons that may be
motivated to cross the junction from right to left. Of course, this circumstance nullifies any elec-
tron component of diode current. Similarly, the positive ionic charges to the right of the PN
junction inhibit hole injection from the p-side to the n-side of the junction, whereupon the hole
component of diode current is rendered null. This simple picture encourages the view that the
width, W
o
, of the transition layer defined over the closed interval, X
po
x X
no
, is just wide
enough to accommodate a sufficient concentration of negative ionic charge on the left of the

- 110 -

junction and positive ionic charge on the right side to impede the injection of mobile charge
carriers across the junction. When one side of the junction is doped more intensely than is the
other side, the intrusion of the ion-charged transition layer into the more lightly doped side must
be proportionately deeper to insure a sufficient volume for the ionic charge needed to repel the
injection of mobile charge from the strongly doped side. As we noted earlier, PN junction diodes
are commonly fabricated with an n-side doped more strongly than the p-side, which therefore
gives rise to a depletion region that intrudes further into the p-side of the junction than into the n-
side.
2.3.1.3. Electric Field And Potential In The Depletion Layer
The simple charge model advanced by (2-30) and Figure (2.11) enables a convenient
quantification of the electric field intensity and corresponding potential distribution associated
with the equilibrium condition. To this end and in accord with the depletion approximation, Fig-
ure (2.12a) portrays the approximate charge distribution as a function of position x in Figure
(2.1). Gauss law relates the electric field intensity, E(x), to this charge distribution, (x), in
accordance with
[1]

x
X
po
X
no
0
(a).
qN
A
qN
D
(x)
x
X
po
X
no
0
(b).
E(x)
E(0)

Figure (2.12). (a). Depletion approximation of the charge profile in a PN junction
operated at equilibrium. (b). The electric field corresponding to the
charge profile in (a). The electric field intensity, F(0), at the junction
is given by (2-37).

- 111 -

s
d (x) (x)
,
dx
=
E
(2-31)
where c
s
is the dielectric constant of the semiconductor under consideration
5
. In the region, X
po

x 0, where (x) = qN
A
, (2-31) implies
po po
(x) x
A
s
(-X ) X
qN
d (x) dx ,
=
} }
E
E
E (2-32)
or
( )
A
po
s
qN
(x) x X ,
= + E (2-33)
where the indicated limits of integration exploit the previously disclosed fact that at equilibrium,
the electric field is null outside of the transition region; specifically, E(X
po
) = 0. On the n-side
of the junction,
no no
(X ) X
D
s
(x) x
qN
d (x) dx ,
=
} }
E
E
E (2-34)
which produces, with E(X
no
) = 0,
( )
D
no
s
qN
(x) x X .
= E (2-35)
Consistency at x = 0 between the two electric field solutions in (2-33) and (2-35) mandates
A po D no
N X N X . = (2-36)
The last result mathematically confirms our previous supposition to the effect that the transition
layer about the PN junction intrudes deeper into the more lightly doped side of the junction than
it does into the heavily doped side. The results postured by (2-33), (2-35), and (2-36) give rise to
the field plot shown in Figure (2.11b), where it is understood that the electric field intensity,
E(0), at the actual junction is
A po
D no
s s
qN X
qN X
(0) .

= = E (2-37)
We have thus confirmed that the electric field is negative throughout the transition region. In
other words, the electric field is always directed from the n-side of the junction, which is home to
positive ionic charge in the depletion region, -to- the p-side of the junction where negative ionic
charge reigns supreme. A maximum magnitude of field intensity is observed at the actual junc-
tion of the PN structure, while zero field prevails in the charge neutral regions outside of the
transition region.
Poissons equation teaches that the presence of an electric field, E(x), implies the exis-
tence of a potential, V(x), such that
dV(x)
(x) .
dx
= E (2-38)
This fundamental relationship can be gainfully exploited to discern the potential, V(X
po
), at the
p-side boundary of the transition layer for a diode in equilibrium, and V(X
no
), the corresponding

5
The dielectric constant of silicon is
s
= 1.05 pF/cm.

- 112 -

potential at the n-side boundary of the transition layer. These two voltage metrics allow for the
evaluation of the junction built-in potential, V
j
, which is little more than the potential difference,
( ) ( )
j no po
V V X V X . = (2-39)
Recall that this built-in potential corresponds to, and arises from, the electric field plotted in Fig-
ure (2.11b).
We return now to (2-21), which delineates the requisite electric field commensurate
with zero hole current. Combining (2-38) with (2-21),
| |
T
dV(x) V d p(x) , ln = (2-40)
which can be integrated over potential from an arbitrary reference potential of V(X
i
) to the poten-
tial, V(x) at any position x to stipulate
| |
i i
V(x) ln [p(x)]
T
V(X ) ln [p(X )]
dV(x) V d p(x) . ln =
} }
(2-41)
Upon carrying out the integration implicit to this relationship, we see that the potential, V(x),
necessarily satisfies
( )
( )
i T
i
p(x)
V(x) V X V .
p X
ln
(
=
(

(2-42)
The traditional reference convention sets V(X
i
) to zero with the understanding that X
i
is the loca-
tion at which the free carrier concentration, p(X
i
) in this case, attenuates to the intrinsic
semiconductor concentration, n
i
. Thus, V(X
i
) = 0 when p(X
i
) = n
i
, whence (2-42) becomes
T
i
p(x)
V(x) V .
n
ln
(
=
(

(2-43)
With reference to Figure (2.10a), (2-43) identifies the equilibrium potential, measured with re-
spect to the potential at which the hole concentration profile degrades to its intrinsic value, as a
function of position x on the p-side of the junction. At x = X
po
, p(X
po
) = N
A
, which results in
a potential, V(X
po
), at the p-side boundary of the PN junction transition layer of
( )
A
po T
i
N
V X V .
n
ln
(
=
(

(2-44)
Equations (2-43) and (2-44) derive from (2-21), which sets the condition for zero hole
current in a PN junction diode. On the other hand, (2-25) delineates the requirement underlying
zero electron current. If we repeat the preceding analysis and premise it on (2-25), we can easily
confirm that
T
i
n(x)
V(x) V ,
n
ln
(
=
(

(2-45)
and
( )
D
no T
i
N
V X V .
n
ln
(
=
(

(2-46)
Equation (2-45) defines the potential, referenced to the potential at the position where the free
electron concentration reduces to intrinsic value n
i
, on the n-side of the PN junction diode.
Equation (2-46) gives the specific potential at the n-side boundary of the equilibrium transition

- 113 -

layer. Upon insertion of this result and (2-44) into (2-39), the junction built-in potential, V
j
,
manifested in concert with diode equilibrium is found to be
( ) ( )
A D
j no po T
2
i
N N
V V X V X V .
n
ln
| |
| = =
|
\ .
(2-47)
The built-in voltage, V
j
, is a positive number since the dopant concentrations on both
the p-side and the n-side of the PN junction diode are assuredly larger than the semiconductor
intrinsic carrier concentration. This voltage, which is generally of the order of 800 mV -to- 1
volt, is polarized from the n-side transition layer boundary to the p-side transition layer boun-
dary. Strangely enough, this relatively large internal voltage is established in a diode that is not
connected into a network that incorporates an energy source.
In an attempt to thwart perceptions of premature author senility, the background physi-
cal issues that attest to the foregoing (and tacitly curious) built-in potential are worthy of review.
First, a diode in equilibrium conducts zero current, which requires that both the hole and electron
components of diode current be zero. Zero hole and electron current components require that an
electric field be established in the transition layer. This field is proportional to the logarithmic
slopes of the hole and electron concentrations in the immediate neighborhood of the junction.
The electric field in question is directed from the n-side of the PN junction to the p-side. In turn,
this field orientation requires a concentration of positive charge in the n-side transition region
and a concentration of negative charge on the p-side of the transition layer. These charge
concentrations support the subject built-in junction potential, whose polarization effectively
serves to reverse bias, albeit internally, the PN junction diode. The potential, V
j
might therefore
be thought of as the requisite level of reverse biasing that is just large enough to preclude hole
and electron injection, and therefore null current conduction, through the PN junction under
equilibrium conditions.
2.3.1.4. Contact Potential
Adding to the puzzling nature of the built-in equilibrium junction potential, V
j
, is the
fact that its direct measurement in the laboratory is all but impossible. A somewhat cavalier
explanation of this measurement dilemma is that any attempt to connect a voltmeter, oscillos-
cope, or other measurement equipment around a non-energized diode inherently destroys the
equilibrium condition that is promoted by the built-in potential. A more satisfying rationale is
offered by the concept of contact potentials.
A contact potential is an unavoidable voltage difference established between two
dissimilar materials that are in electrical contact with one another. These contact voltage drops
are precipitated by differences in the potential energies of mobile electrons on either side of the
contact. Consider, for example, the resistively shunted diode in Figure (2.13), in which the metal
contacts at either end of the diode structure are expressly delineated. Because these metal
contacts, which are typically formed of copper or aluminum, differ materially from the physical
properties of the semiconductor diode, contact potentials, V
pm
and V
nm
are explicitly established,
as we show in the extended diode diagram. In particular, a contact potential of V
pm
is forged
from the p-type semiconductor to the metal contact on the left of the device, while a contact
potential, V
nm
, is analogously formed from the n-type semiconductor to the metal contact on the
right. The charge neutral regions of both the p- and n-sides of the junction support zero voltage
drops because of the zero current equilibrium condition implied by the absence of a biasing
voltage. Even if diode current were to flow, these voltage drops remain near zero because the

- 114 -

heavily doped p- and n-sides of the diode give rise to very small ohmic resistances in these
charge neutral sectors. Using Kirchhoffs voltage law,
d nm j pm
i (t)R V V V . = + + (2-48)
i (t)
d
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +

= 0
V
j 0 + +
V
pm
+
V
nm
+
+
0
Metal
Contact
Metal
Contact
R

Figure (2.13). PN junction diode connected in shunt with a resistance, R. No voltage is applied to forward
bias the diode. The metal contacts at either end of the diode are expressly highlighted, as are
the corresponding semiconductor-metal contact potentials, V
pm
and V
nm
.
Since the built-in potential, V
j
, precludes the flow of diode current, the contact potentials must
neutralize V
j
; that is,
A D
nm pm j T 2
i
N N
V V V V ,
n
ln
| |
|
= =
|
|
\ .
(2-49)
where (2-47) has been enlisted. If (2-49) is not satisfied, a nomination for a Nobel is appropriate
for us for otherwise, current is made to flow through, and thus energy is delivered to, a resistance
without any energy applied to the diode-resistance system. We should note that (2-49) implies
that contact potentials track with doping concentrations, and hence semiconductor regional
properties, since the built-in potential is sensitive to impurity concentrations.
2.3.1.5. Transition Layer Width And Depletion Capacitance
We are at liberty to apply Poissons equation in (2-38) to the junction transition region,
X
po
x X
no
, which is graphically highlighted in Figures (2.10) through (2.13). On the p-side
of the junction, (2-38) and (2-33) give
( )
A
po
s
dV(x) qN
x X ,
dx
= + (2-50)
which in turn delivers
( )
po po
V(x) x
A
po
s
V(-X ) X
qN
dV(x) x X dx .
= +
} }
(2-51)
The integration of both sides of this expression produces a potential, V(x), on the p-side of the
junction transition layer of

- 115 -

( ) ( )
2
A
po po
s
qN
V(x) V X x X .
2
= + + (2-52)
This expression predicts a potential, V(0), at the actual junction, referenced to the potential
evidenced at the position where the free carrier concentration reduces to intrinsic level, which is
given by
( )
2
A po
po
s
qN X
V(0) V X .
2
= + (2-53)
On the n-side of the junction, (2-38) and (2-35) combine to offer
( )
no no
V(X ) X
D
no
s
V(x) x
qN
dV(x) x X dx ,
=
} }
(2-54)
whence
( ) ( )
2
D
no no
s
qN
V(x) V X x X .
2
= (2-55)
The last result posits a junction potential of
( )
2
A no
no
s
qN X
V(0) V X .
2
= (2-56)
This relationship for the potential at the diode junction must mirror the junction potential defined
by (2-53). If (2-53) is subtracted from (2-56) and if use is made of (2-39) and (2-36), such
connectivity of potential at the junction forms the basis for positioning the actual boundaries of
the transition region, subject, of course, to the depletion approximation invoked earlier. In
particular,
s j
D
po
A A D
2 V
N
X
qN N N
| |
=
|
+
\ .
(2-57)
and
s j
A A
no po
D D A D
2 V
N N
X X .
N qN N N
| | | |
= =
| |
+
\ . \ .
(2-58)
It follows that the equilibrium width, W
o
, of the junction transition layer is
( )
s j
o no po
AD
2 V
W X X ,
qN
= = (2-59)
where N
AD
is the effective impurity concentration,
A D
AD
A D
N N
N .
N N
=
+
(2-60)
We should underscore the observation here that the depletion layer width and the junction built
in potential are inextricably linked. This link is sensible since a larger V
j
implies a larger electric
field at the PN junction, which, in turn, implies more ionic charge on both sides of the junction.
Of course, larger levels of ionic charge require greater physical space to house this charge,
whence a larger depletion layer width, W
o
.
The positive charge prevailing on the n-side of the transition region in the PN junction
diode in Figure (2.11), the negative charge prevailing on the p-side transition volume of the junc-

- 116 -

tion, and the finite, nonzero width, W
o
, which separates the boundaries of the charge transition
layer combine to conjure visions of an effective parallel plate capacitance that straddles the junc-
tion. The plates of this perceived capacitance are not metallic, as is the norm in traditional
capacitances. Instead, they are the heavily doped, and thus low resistivity (which synergizes
with the resistive properties of a metal), p-type and n-type charge neutral regions to which
electrical contact is made for ultimate circuit applications of the diode structure. In concert with
our parallel plate vision, the capacitance, say C
jo
, associated with the charge embedded in the
transition volume of a PN junction diode is
e s s AD
jo e
o j
A q N
C A .
W 2V
= = (2-61)
This capacitance is commonly referred to as the equilibrium, or zero bias, depletion capacitance
of the PN junction. We note that this capacitance is directly proportional to the area of the
junction, which correctly hints that diodes earmarked for high-speed circuit applications must be
small enough to avoid the voltage response sluggishness implicit to significant charge storage at
the junction. Its value is also largely limited by the impurity concentration of the lightly doped
side of the junction. The latter observation mirrors engineering intuition in that we can view the
depletion capacitance straddling the entire transition layer as the series interconnection of two
capacitances. One of these series capacitances appears from the p-side boundary of the junction
transition layer to the actual PN junction, while the second of the two series capacitances
effectively connects from the junction to the n-side boundary of the transition layer. We recall
that the net capacitance of a series interconnection of two capacitances is smaller than either of
the series capacitances.
EXAMPLE #2.3:
A certain silicon diode boasts a PN junction injection area of 80 m
2
, an approx-
imately constant p-side dopant concentration of 10
16
atoms/cm
3
, and an approx-
imate n-side dopant concentration of (6.5)(10
18
) atoms/cm
3
. For equilibrium and
room temperature conditions, calculate the built-in potential of the junction, the
width of the junction transition layer, the maximum magnitude of electric field
internal to the junction, and the zero bias value of the junction capacitance. As-
sume the validity of the depletion approximation and take the intrinsic carrier
concentration at room temperature to be (1.5)(10
10
) atoms/cm
3
.
SOLUTION #2.3:
(1). At 27 C, which is 300.16 K, the Boltzmann voltage is, by (2-2), V
T
= 25.89 mV. From (2-
47), the built-in potential with N
A
= 10
16
atoms/cm
3
, N
D
= (6.5)(10
18
) atoms/cm
3
, and n
i
=
(1.5)(10
10
) atoms/cm
3
follows as
A D
j T
2
i
N N
V V 862.02 mV .
n
ln
(
( = =
(

(E3-1)
(2). Using (2-60), we find that the effective diode impurity concentration is
15 3 A D
AD
A D
N N
N (9.985)(10 ) atoms/cm .
N N
= =
+
(E3-2)
For V
j
= 862.02 mV, a silicon dielectric constant of c
s
= 1.05 pF/cm, and an electron charge
magnitude of q = (1.6)(10
19
) coulomb, (2-59) delivers an equilibrium depletion layer width

- 117 -

of
s j
-5
o
AD
2 V
W (3.37)(10 ) cm 0.337 m .
qN
= = =
(E3-3)
(3). For junction cross section area of A
e
= 80 m
2
= (80)(10
8
) cm
2
, (2-61) yields an equilibrium
transition region capacitance of
e s
jo
o
A
C 24.95 fF .
W
= =
(E3-4)
Since the junction area of an integrated PN junction diode is a designable parameter selected
in accordance with appropriate system considerations, this capacitance is often expressed as a
capacitance density. This density is the metric, C
jo
/A
e
, which happens to be 31.19 nF/cm
2
in
this particular case.
(4). From (2-57), the intrusion of the junction transition layer into the p-side of the junction is
s j
D
po
A A D
2 V
N
X 0.3361 m .
qN N N
| |
= =
|
+
\ .
(E3-5)
For the n-side intrusion, (2-58) offers
A
no po
D
N
X X 0.000517 m 0.517 nm .
N
| |
= = =
|
\ .
(E3-6)
Appealing to (2-37), the maximum magnitude of the electric field intensity, which is ob-
served at the actual PN junction, is
A po
D no
s s
qN X
qN X
(0) 51.22 kVolt/cm .

= = = E
(E3-7)
A notable aspect of this numerical example is the significant electric field intensity that is
established at the junction of the considered diode under equilibrium conditions. The field of
better than 50 kV/cm is comparable to the electric field established by a 12-volt automobile
battery cable whose positive and negative leads are separated by two and a third microns of
insulation. As might be expected, the field in question is accompanied by a correspondingly
sizeable built-in potential whose magnitude in this case exceeds typical turn on voltages for
silicon diodes by better than 160 mV. Finally, observe that most of the depletion layer ex-
tends into the p-side of the junction, which is doped lighter than is the n-side. Indeed, only
0.267% of the net equilibrium width of the depletion layer intrudes to the n-side of the junc-
tion.
2.3.2. PN JUNCTION AT NON-EQUILIBRIUM
A PN junction diode operated under non-equilibrium conditions has energy applied to it
to incur either reverse bias or forward bias. The diode equilibrium conditions studied in the
preceding section are foundational for studying non-equilibrium junction dynamics. This
contention derives from earlier assertions to the effect that the equilibrium width, W
o
, of the
junction depletion region is wide enough to house just the right density of positive and negative
impurity ions to repel the injection of holes and electrons across the junction. Equivalently,
these ionized impurities within the depletion layer establish an electric field that supports a built-
in potential, V
j
, which serves to reverse bias the intrinsic junction at precisely the level
commensurate with precluding free carrier injection across the PN junction. In a word, the

- 118 -

magnitude and polarization of the built-in junction potential guarantees zero diode current in the
equilibrium state. The situation at hand is overviewed in Figure (2.14a).
i (t)
d
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +

= 0
x
0
W
n
W
p
X
po
X
no
W
o
V
j
+
(a).
+ v (t)
d
i (t)
d
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +

< 0
x
0
W
n
W
p
X
p
X
n
W > W
o
V + V
j
+
(b).
+ v (t)
d

+ +
+ +
+ +
+ +
+ +
+ +
+ +
+ +

V

Figure (2.14). (a). PN junction diode under equilibrium conditions for which no diode current flows. (b).
Reverse biased PN junction diode. A small amount of negative diode current flows in re-
sponse to the applied reverse biasing voltage, V, owing to injection across the junction of
minority carriers on either side of the junction.
2.3.2.1. Reverse Biased PN Junction Diode
In Figure (2.14b), we show the PN junction diode cross section of Figure (2.14a) with a
reverse bias voltage, V, applied across the diode terminals. In this non-equilibrium state, the
measurable diode terminal voltage, v
d
(t), is v
d
(t) V in that the very small reverse bias current

- 119 -

manifested by reverse biasing voltage V incurs negligible potential drop in the ohmic, charge
neutral p-type and n-type volumes. Because v
d
(t) V, the built-in junction potential increases
from its equilibrium value of V
j
to its reverse biased value of (V
j
+ V). At least three ramifica-
tions of this enhanced built-in potential are apparent. First, since V
j
is the value of the intrinsic
junction reverse bias that is just sufficient to preclude the transport of mobile charge carriers
across the junction in equilibrium, an increase of V
j
by the amount, V, serves to preclude aggres-
sively the transport of majority carriers across the junction. But it also serves to attract minority
carrier electrons from the p-side of the junction to the n-side. Similarly, the increased intrinsic
junction potential corresponds to an increased density of ionic charge within the depletion layer
that encourages minority carrier holes from the n-side to traverse the PN junction.
The second effect of the applied reverse bias is to increase the equilibrium width, W
o
,
of the depletion layer to the value, W, delineated in Figure (2.14b). In (2-59), if we replace vol-
tage V
j
by its expanded value (V
j
+ V), we can deduce a revised value of depletion layer width
given by
( )
s j
d
o o
AD j j
2 V V
v (t) V
W W 1 W 1 .
qN V V
+
= = + = (2-62)
Because of the increased depletion layer width, the zero bias depletion capacitance in (2-61) can
be expected to decrease from its original value of C
jo
to its biased value, say C
j
, such that
jo
e s
j
d
o
j j
C
A
C ;
V v (t)
W 1 1
V V
= =
+
(2-63)
that is, the junction depletion capacitance decreases with increasing reverse bias, largely because
of the increased depletion layer width (or thickness of the parallel plate capacitance fantasized
earlier) incurred by this reverse bias.
The third consequence of the applied reverse bias is increased electric field intensity at
the junction. Referring to (2-37) and (2-57), the revised (reverse biased) junction electric field
intensity, say E
r
(0), is
( )
AD j
d
r
s j
2qN V V
v (t)
(0) (0) 1 .
V
+
= = E E (2-64)
This increased field intensity is a concern in that the field intensity at zero bias is, as demon-
strated in Example #2.3, already surprisingly large. As a result, field-induced voltage breakdown
is a possibility if the applied reverse bias, V, exceeds the reverse bias voltage rating of the de-
vice
[2]
. Such breakdown, which manifests potentially appreciable negative diode current, does
not necessarily imply a catastrophic device failure. Indeed, special purpose diodes known as
Zener diodes, are commonly manufactured to operate expressly in breakdown mode. These
components deliver significant negative diode currents at a virtually constant reverse bias voltage
that is commonly referenced as the Zener voltage. Indeed, Zener diodes enjoy utility in regulator
applications for which the system requirement is a nominally constant load voltage in the face of
perturbations in line voltages and effective load resistance. We provide more information
regarding voltage regulation later.
We can summarize the immediate effects of a reverse bias applied to a PN junction di-
ode as increased junction field intensity, decreased depletion capacitance, and increased transi-

- 120 -

tion layer width. From (2-64), (2-63), and (2-62), we can coalesce the modulations associated
with these phenomena as

jo
d r
j o j j
C
v (t) (0) W V
1 1 .
(0) C W V V
= = = + =
E
E
(2-65)
Because (2-65) is premised on the depletion approximation, which while reasonable and conve-
nient, is suspect at the junction and at the edges of the transition region, (2-65) is traditionally
adjusted in accordance with
j j
m m
jo
d r
j o j j
C
v (t) (0) W V
1 1 .
(0) C W V V
| | | |
= = = + = | |
| |
\ . \ .
E
E
(2-66)
In (2-66), m
j
is an empirically determined grading coefficient whose numerical value generally
spans the range, 0.25 m
j
0.5. Conventionally, m
j
tends toward if the observed charge pro-
file closely approximates the abrupt change at the junction that is projected Figure (2.12a). On
the other hand, m
j
is of the order 1/3 if the charge profile at the junction has a shallow gradient.
2.3.2.2. Forward Biased PN Junction Diode
Figure (2.15) diagrams the state of affairs pertinent to forward biasing a PN junction di-
ode. Specifically, Figure (2.15a) compares the equilibrium state to the structure in Figure
(2.15b), which reflects the effects of a forward biasing voltage applied across the diode. In this
case, the applied voltage, V, mirrors the actual diode voltage, v
d
(t). Its polarization therefore
counteracts the built-in potential, V
j
. The voltage resultantly developed intrinsically across the
transition region can therefore be expected to track with voltage V as (V
j
V). Since the
establishment of a built-in voltage of V
j
corresponds to an equilibrium transition region width of
W
o
, a potential reduced by the amount, V, affords a smaller transition layer width, which we shall
symbolize as W. The reduced built-in junction potential facilitates the injection of mobile major-
ity charge carriers across the junction. This disclosure synergizes with the fact that V
j
is the
built-in potential required to preclude such mobile carrier injection. It follows that a positive di-
ode current, i
d
(t), is established.
It should be understood that the applied voltage, V, can neither equal nor exceed the
original built-in potential, V
j
. If V were to equal V
j
, the PN junction diode effectively emulates a
short circuit between its external terminals because of the resultant zero voltage drop across the
junction transition region and the negligible ohmic drops in the charge neutral p- and n-sides of
the junction. If V were to exceed V
j
, the curious and surrealistic case of a transition region boast-
ing negative width arises. It is therefore reasonable to postulate that V
j
represents the maximum
possible forward bias that can be sustained across a PN junction diode without incurring a diode
short circuit and the likely catastrophic failure spawned by the resultantly large short circuit cur-
rents.
A subtle, but enormously important, impact of diode forward biasing is that the junc-
tion transition region depicted in Figure (2.15b) is no longer a depletion region. To be sure,
immobile ionized charges, and therefore a depletion capacitance component, persist in this re-
gion because the width of the transition layer never collapses to zero. But immersed in this den-
sity of ionic charges are densities of mobile charges in that the injection of p-side holes across
the junction is promoted, as is the injection of free electrons from the n-side to the p-side. Equa-
tion (2-66), which presumes complete depletion of the transition layer, therefore no longer pro-

- 121 -

scribes accurate disclosures of junction capacitance. Since the forward bias applied to a PN
junction diode differs negligibly from the junction turn on voltage, V
on
, even for relatively large
forward diode currents, the depletion capacitance expression of (2-66) can be supplanted by the
approximation,
i (t)
d
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +

= 0
x
0
W
n
W
p
X
po
X
no
W
o
V
j
+
(a).
+ v (t)
d
i (t)
d
+
+
+
+
+
+
+
+

> 0
x
0
W
n
W
p
X
p
X
n
W < W
o
V V
j
+
(b).
+ v (t)
d
+
+
+
+
+
+
+
+

V

Figure (2.15). (a). PN junction diode under equilibrium conditions for which no diode current flows.
(b). Forward biased PN junction diode. Majority carrier injection across the junction,
and thus a positive diode current, i
d
(t), is promoted by the partial collapse of the junc-
tion transition layer width.
j j
d
jo jo
j jf
m m
v (t) 0
d on
j j
C C
C C .
v (t) V
1 1
V V
>
= ~
| | | |
| |
| |
\ . \ .
(2-67)

- 122 -

The argument in favor of the last result, which advances a constant depletion capacitance under
forward bias conditions, is that for v
d
(t) V
on
, very few mobile charge carriers traverse the PN
junction, while large forward diode currents can prevail even when the observed diode voltage
only slightly exceeds V
on
.
The junction depletion capacitance, C
jf
, approximated by (2-67) is not the only capacit-
ance indigenous to a forward biased PN junction, nor is it generally the dominant component of
the net capacitance of a forward biased diode. In the course of traversing the junction from the
p-side to the n-side, a hole necessarily must spend some time in the junction transition region for
the simple reason that charge can never be transferred instantaneously. Similarly, a free electron
hangs out in the transition layer en route from the n-side of the junction to the p-side. For the
average amount of time that these holes and electrons spend within the transition volume, the
charge therein obviously increases above the zero current charge level set by the density of ionic
charge. Consequently, the hole-electron charge population that briefly resides in the transition
volume under forward bias conditions increases the effective junction capacitance above the
depletion capacitance level established solely by immobile ionic charges. This enhanced mobile
charge, say Q
d
(t), which might properly be viewed as an excess hole-electron charge in the sense
of comparing it to the background ionic charge within the transition layer, is foundational to the
steady state diode current defined by the right hand side of (2-1). Indeed, this steady state diode
current, i
d
(t), is nonzero if and only if Q
d
(t) is nonzero, for diode current in the steady state arises
exclusively from the continual transport of holes and electrons across the transition layer that
straddles the PN junction. It is therefore reasonable to infer that the excess junction charge,
Q
d
(t), is proportional to diode current in accordance with the simple relationship,
d T
v (t) nV
d d d d o
Q (t) i (t) I 1 , e
(
= =

(2-68)
where the proportionality constant, t
d
, is termed the average lifetime of free charge carriers.
More specifically,
d
physically reflects the average time spent by injected holes and electrons
within the junction transition layer. For relatively small feature size diodes destined for high-
speed signal processing applications,
d
is of the order of less than a few tens of picoseconds.
For large PN junction diodes earmarked for use in power systems,
d
can be tens or even several
hundreds of nanoseconds.
The diffusion capacitance, C
d
, associated with the excess transition region charge of (2-
68) is
d T
v (t) nV d d o d d
d
d T T
dQ (t) I i (t)
C ,
dv (t) nV nV
e = = ~ (2-69)
where we have invoked (2-1), in which, for forward biasing, the unity term is discarded in
comparison to the exponential term on the bracketed right hand side. Recalling (2-67), it follows
that the total capacitance, say C
T
, associated with a forward biased PN junction diode is
j
m
d d on
T d jf jo
T j
i (t) V
C C C C 1 .
nV V
| |
= + ~ + |
|
\ .
(2-70)
The foregoing results combine to infer that the forward biased PN junction diode can be
represented electrically by the model in Figure (2.16a). In this model, we take note of two
capacitive components to the net diode capacitance, C
T
. The diffusion component, C
d
, which is
manifested only for forward biasing conditions, is proportional to the diode current. For reasona-
bly substantial currents, this diffusion component is likely to dominate over its depletion counter-

- 123 -

part, C
jf
, which arises from ionic charge in the transition layer. On the other hand, Figure (2.16b)
is the model pertinent to reverse biasing, wherein the diffusion capacitance is null since no free
holes or electrons are injected across the junction. Accordingly, the only capacitance across a
reverse biased PN junction is the depletion component, C
j
, as dictated by (2-66). Finally, the
steady state diode current stipulated by (2-1) is supplanted in the model of Figure (2.16b) by the
very small diode saturation/leakage current, I
o
.
i (t)
d
+ v (t)
> 0
d
(a).
i (t)
d
+ v (t)
d
Q (t)/
d d
C
d
C
jf
C
T
i (t)
d
+ v (t)
< 0
d
(b).
i (t)
d
+ v (t)
d
I
o
C
j

Figure (2.16). (a). Approximate circuit model of a forward biased PN junction diode. The charge func-
tion, Q
d
(t), and the capacitances, C
d
and C
jf
, are given respectively by (2-68), (2-69), and (2-
67). (b). Approximate circuit model of a reverse biased PN junction diode. The current, I
o
,
is the saturation current of the subject diode, while the junction capacitance, C
j
, derives
from (2-65).
2.4.0. CIRCUIT CONSIDERATIONS FOR THE PN JUNCTION
The models in Figure (2.16) and the physical and engineering concepts that underpin
these structures enable meaningful analytical disclosures of the electrical responses generated by
circuits utilizing PN junction diodes. Among the most important of these issues are switching
times observed in diode networks that are driven by voltage waveforms emulating step functions
in the time domain. An understanding of these switching transients and an ultimate mitigation of
their dominant degrading effects in high-speed signal processors often comprise critical design
considerations in diode, as well as in more advanced semiconductor circuits. A second critical
circuit issue is the concept of small signal response, wherein diodes (and transistors) in a given
network are biased in their forward regimes and continue to function for all time in a restrictive
neighborhood of their respective quiescent operating points. Small signal analysis concepts are
particularly germane to these electronic networks, which are designed to achieve nominally li-

- 124 -

near I/O signal processing despite the inherent nonlinearities that prevail within the semiconduc-
tor devices embedded in these networks.
2.4.1. PN JUNCTION DIODE SWITCHING TRANSIENTS
Our investigations of diode circuits begin with a consideration of the series resistance-
diode circuit given in Figure (2.17). For a long time prior to time t = 0 in this simple circuit, the
input voltage, v
i
(t), remains constant at the indicated level, V
F
. We presume that voltage V
F
ex-
ceeds the turn on threshold, V
on
, of the PN junction diode, which is to say that the diode in the
network conducts forward current for t < 0. At time t = 0, the switch is moved in the direction
shown in the diagram so that voltage v
i
(t) changes instantaneously from a positive value of V
F
to
a negative voltage of V
R
. The resultant time domain depiction of this input port voltage is dia-
grammed in Figure (2.18a). Because v
i
(t) = V
F
for a long time prior to switching, we assume
logically that the circuit operates in the steady state immediately prior to voltage switching at
time t = 0. Using the simple diode switch model of Figure (2.3), we observe a diode current,
i
d
(0), immediately prior to input voltage switching of

V
F
i (t)
d
V
R

t

=

0
R
+
v (t)
d
v (t)
i
S
W

Figure (2.17). Circuit used to evaluate the switching response speed of a PN
junction diode driven in the time domain by an applied vol-
tage step.
F on
d F
V V
i (0 ) I .
R

= (2-71)
If the simple diode model of Figure (2.3) continues to be invoked subsequent to the indicated in-
put voltage switching, we are forced to conclude, unfortunately erroneously, that the diode cur-
rent vanishes instantly at time t = 0+. From this conclusion, it follows that our initial prediction
of the diode current resulting from the input voltage step is ostensibly (but incorrectly) the re-
sponse delineated in Figure (2.18b).
The idealized diode current response in Figure (2.18b) is unrealistic for at least two rea-
sons. First, it inherently ignores the fundamental fact that charge cannot be displaced instanta-
neously. Recall from our earlier discussions that under forward bias conditions, there is an
appreciable concentration of hole and electron charge (the so-called excess charge) within the
depletion layer. Diode turn off cannot be achieved until this excess charge (over and above the
immobile ionic charge that prevails within the depletion layers) is swept away. Second, the idea-
lized plot is oblivious to the voltage charging properties of the junction depletion capacitance,
which influences the circuit response subsequent to removal of the excess junction charge. As
we propose in Figure (2.18c), during the interval of time in which excess charge remains in the
transition area, a substantial current in the amount of I
R
flows effectively the wrong way through
the diode immediately after input voltage switching. The current flows the wrong way because
free electrons remaining within the transition layer are repulsed to the n-side of the junction by

- 125 -

the potential, V
R
, which is applied to the p-side of the junction. On the other hand, holes within
the layer are attracted to the p-side by this negative potential. Since the approximate forward di-
ode voltage, V
on
, is associated with the excess junction charge that awaits removal, it too is sus-
tained for time t > 0, thereby manifesting a wrong way current of
v (t)
i
t
V
F
V
R
0
(a).
i (t)
d
t
I
F
0
(b).
i (t)
d
t
I
F
I
R
0
(c).
t
s
V /10R
R
t + t
s c
t
off

Figure (2.18). (a). The voltage applied to the input port of the diode-resistance
circuit shown in Figure (2.17). (b). Idealized diode current re-
sponse to the input port excitation shown in (a). (c). A more
realistic depiction of the diode current response to the input port
excitation shown in (a).

- 126 -

R on
d R
V V
i (0 ) I .
R
+
+
= (2-72)
The diode continues to conduct current I
R
until the time, t
s
in Figure (2.18c), at which the junc-
tion transition region is wiped clean of the excess charge originally stored in the depletion layer
prior to input voltage switching. In effect, the diode does not begin to turn off until time t = t
s
,
which might properly be referred to as the excess charge storage time of the diode. At t = t
s
, the
diode voltage remains V
on
, which means that the junction depletion capacitance is charged to V
on
;
specifically, v
d
(t
s
+) = V
on
. Zero diode current is ultimately achieved only when this capacitance
discharges from voltage V
on
to near the switched input voltage, which is V
R
.
With reference to the diagram in Figure (2.18c), the overall turn off time, t
off
, of the di-
ode is the sum of the storage time, t
s
, and the junction capacitance charging time, t
c
; that is,
off s c
t t t . = + (2-73)
It is understood herewith that Q
d
(t
s
) = 0, while t
c
is the additional time (above time t
s
) required
for the diode depletion capacitance to charge to within an appreciable percentage of the switched
voltage, V
R
. The usual convention dictates that appreciable be equated to 90%. Thus, we
may define time t
c
implicitly by the requirement, v
d
(t
s
+ t
c
) = 0.9V
R
. We observe then that the
diode current, i
d
(t
s
+ t
c
), corresponding to v
d
(t
s
+ t
c
) = 0.9V
R
, is
R
d s c
V
i (t + t ) .
10R
= (2-74)
2.4.1.1. Switching Transient Analysis
As we might expect, the analysis of a nonlinear circuit, such as the one that is presently
before us, is not as straightforward as is the analysis of a linear network. To be sure, we shall
still need to write the current and/or voltage equilibrium relationships, and we shall still make
use of the volt-ampere characteristics of the various branch elements embraced by the network of
interest. In the case of linear branch elements, such as resistive or capacitive branches, these V-I
characteristics linearly interrelate respective branch voltages and corresponding branch currents.
Moreover, a single, linear equation, or perhaps a set of linear equations, applies for all time and
for all considered values of voltage, current, and time. But in the case of PN junction diodes and
other kinds of nonlinear branch elements, the V-I relationships are nonlinearly intertwined,
and/or they display conditional time dependencies. To be sure, we shall seek to linearize these
expressions, or perhaps simplify them in some reasonable fashion but in the process, we shall
need to be mindful that such simplifications may apply for only certain times and for only certain
V-I regimes of branch element operation. For example, a simplification may be entirely
appropriate for small branch currents, but totally skewed for high currents, where hopefully,
another form of an approximation can be more meaningfully invoked.
When a circuit or system analysis is not straightforward and is predicated on
approximations premised on our presumed understanding of the operation of a nonlinear ele-
ment, there is a natural doubt that the circuit responses gleaned through manual analysis accu-
rately reflect the responses observed ultimately when the network undergoes test and evaluation.
This doubt is foundational to our asserting that the purpose of analysis, and especially manual
analysis, is not the formulation of precise disclosures. Rather its purpose is the delineation of
sufficiently accurate, albeit first order approximations of, results that convey design insights
whose exploitation can lead to enhanced network performance or optimization. Lingering
doubts that impede lending credence to analytical deductions can also be mitigated by computer-

- 127 -

aided simulation via the ubiquitous CADENCE design suite or SPICE
6
. Simulators have little
problem with most nonlinearities in that they generally deliver, with remarkable alacrity, accu-
rate results predicated on iterative analyses that generally invoke few, if any, approximations. It
is, of course, a happy and reassuring day when simulated results largely agree with manual
revelations. But it can also be good news when they do not agree. To the latter end, it could be
that a simple analytical error has been made; it is always a good idea to correct it before present-
ing it to the boss. It could also mean that we have misinterpreted a device or network concept or
perhaps inappropriately approximated an important situation. Revisiting this misinterpretation or
incorrect approximation just might inspire new and profitable design insights that were inadver-
tently masked by erroneous interim conclusions.
We can begin to substantiate the preceding, largely qualitative, predictions of the diode
current response in the circuit of Figure (2.17) by noting that at time t = 0 (immediately prior to
throwing switch SW), the circuit operates in the steady state, and the diode current is given by (2-
71). Using (2-68), this current gives rise to an excess charge, Q
d
(0), at t = 0 of
on T
V nV
d d F d o
Q (0 ) I I 1 , e
(
= ~

(2-75)
where in the interest of consistency with the current expression in (2-68), the diode voltage,
v
d
(0), at time t = 0 has been approximated as the diode threshold voltage, V
on
. To the latter
end, remember that when forward biased, the diode voltage exceeds turn on potential V
on
by no
more than the relatively small Boltzmann voltage multiple, nV
T
. As explained in the preceding
subsection, the diode remains forward biased immediately after switch SW is thrown so that the
pertinent diode equivalent circuit in the neighborhood of t = 0+ remains the structure of Figure
(2.16a).
Since the diode current, i
d
(t), is I
R
, as per (2-72), for as long as the diode remains for-
ward biased, the model in Figure (2.15a) delivers
d d d
R d jf
d
Q (t) dv (t) dv (t)
I C C .
dt dt
= + + (2-76)
In the interest of analytical simplicity, the depletion capacitance component of diode current,
which is the last term on the right hand side of (2-76), can be ignored. This simplification is
reasonable in view of the fact that depletion capacitance C
jf
is rarely the dominant capacitance of
a forward biased PN junction. Moreover, the diode voltage, v
d
(t), changes only minimally under
forward bias operating circumstances, thereby rendering its time derivative small. Since
d d d d
d
d
dQ (t) dQ (t) dv (t) dv (t)
C ,
dt dv (t) dt dt
= = (2-77)
where (2-69) is invoked, (2-76) reduces to the delightfully simple first order differential equa-
tion,
d d
R
d
dQ (t) Q (t)
I .
dt
~ + (2-78)
Even though the charge function itself depends nonlinearly on the diode voltage, this equation is
a linear function of the excess charge function, Q
d
(t). From (2-75) and the fact that the differen-
tial equation in (2-78) predicts a steady state charge value of Q
d
() = t
d
I
R
, the solution follows
forthwith as

6
The computer scientists and electrical engineers at the University of California at Berkeley stretched a bit with the
SPICE acronym in that it stands for Simulation Program with Integrated Circuit Emphasis.

- 128 -

( )
d
t
d d R d R F
Q (t) I I I , t 0. e
= + + > (2-79)
It is important to appreciate that while (2-79) is the time domain solution of (2-78), (2-78) itself
applies only to the time interval, 0+ t t
s
where the diode remains forward biased. The model
of Figure (2.16a), from which (2-79) derives, reflects this forward bias condition. At the diode
charge storage time, t = t
s
, Q
d
(t
s
) = 0, and the diode enters its reverse biased regime. Equation
(2-79) produces this storage time as
F on F
s d d
R R on
V V I
t 1 1 .
I V V
ln ln
| | | |
= + ~ +
| |
+
\ . \ .
(2-80)
At t = t
s
, the diode voltage, v
d
(t
s
), remains at barely the diode threshold level, V
on
. At
time t
s
+ and beyond, the depleted nature of the transition region forces the diode into a reverse
bias state so that the applicable diode model is the topology offered in Figure (2.16b). Ignoring
the small saturation current, I
o
in this model, the applicable equivalent circuit, for t > t
s
+, of the
network in Figure (2.17) is the topology shown in Figure (2.19), where, of course, C
j
represents
the depletion capacitance defined by (2-65). Clearly,
d
R j d s
dv (t)
V RC v (t) for t t .
dt
= + > + (2-81)
i (t)
d

V
R
R
+
v (t)

d
v (t)
i
C
j

Figure (2.19). Equivalent circuit for the network in Figure (2.16) for
the case in which the PN junction diode is reverse bi-
ased.
A closed form solution of this equation is impossible owing to the nonlinear dependence of
capacitance C
j
on diode voltage v
d
(t). Although (2-81) can be solved numerically with readily
available software, it should be noted that the expression is premised on several simplifying
modeling and circuit approximations that render questionable the engineering value of exact
numerical answers. Most importantly, we are reminded that the purpose of circuit analysis is not
necessarily the generation of precise results. Indeed, precise and consistently reproducible cir-
cuit performance results can rarely be generated in electronics because of device processing
vagaries, uncertainties in the numerical values of key physical device parameters, and nonzero
circuit manufacturing tolerances. Rather, it is important to hang on to the philosophy that the
purpose of circuit analysis is the generation of approximate, but nonetheless meaningful and use-
ful, disclosures that insightfully bracket performance results in such a way as to encourage and
facilitate design innovation.
A supremely accurate delineation of diode turn off time is generally unnecessary in the
vast majority of high-speed system applications. Instead, a worst-case (largest) switching time
result usually proves practicable. To this end, a large time constant, RC
j
, inherently slows the
turn off transient. Thus, replacing C
j
by its largest possible value, which is its zero bias depletion
value, C
jo
, arguably reflects engineering prudence. With C
j
= C
jo
, a constant capacitance, a
closed form solution to (2-81) follows forthwith as

- 129 -

( )
( )
s jo
t t RC
d R R on s
v (t) V V V for t t . e

~ + + > + (2-82)
As postulated earlier, the diode current collapses to zero at time t = (t
s
+ t
c
), where the diode vol-
tage, v
d
(t), rises, and thus the diode depletion capacitance charges, to about 90% of (V
R
). Using
(2-82) it is readily shown that
on
c jo jo
R
V
t RC 10 1 2.3RC ,
V
ln
( | |
= + ~
( |
(
\ .
(2-83)
where the additional liberty of presuming V
on
<< V
R
is exploited. The overall diode turn off time
is resultantly,
F on on
off s c d jo
R on R
F
d jo
R
V V V
t t t 1 RC 10 1
V V V
V
1 2.3RC .
V
ln ln
ln
( | | | |
= + ~ + + +
( | |
+
(
\ . \ .
| |
~ + +
|
\ .
(2-84)
Equation (2-84) suggests that two engineering efforts can be slotted toward reducing
the diode turn off time to imposed transient excitation. First, we must consider reducing the
charge storage time, which is given by the first term on the right hand side of either of the last
two forms of the subject expression. Second, we can mitigate the charging time, which is hig-
hlighted by the last terms on the aforementioned right hand sides. We should first recognize that
both of these time components are minimized through deployment of minimal geometry diodes
since capacitance C
jo
is directly proportional to cross section junction area, and lifetime
d
de-
creases progressively as device feature sizes decrease. On the other hand, we see that the storage
component of the turn off transient is seen as approaching zero if V
F
<< V
R
. This observation
supports engineering intuition in that it suggests that a way to achieve a progressively smaller
storage component of the turn off time is to excite the input terminal by a strong negative vol-
tage. In a sense, the observation asserts that we must blast the diode off, subject to the proviso
that the reverse voltage blast does not fry the PN junction because of excess electric field. On
the other hand, the charging time component is reduced through use of a small current limiting
resistance, R. Once again, however, design care is required in that too small a value of resistance
R gives rise to large forward and large wrong way currents that may incur significant self heat-
ing in the diode. Such self heating proves counterproductive in that it can be shown to increase
lifetime
d
and capacitance C
jo
. An excessively large diode current may even incur outright ther-
mally-induced device damage.
2.4.1.2. Compensation Of The Switching Transient
The foregoing discussion of the turn off effectiveness of a large applied reverse voltage,
V
R
, offers a clue as to how the circuit in Figure (2.17) might be compensated to achieve dimi-
nished turn off time. In particular, a large V
R
promotes the prompt exodus of stored excess
charge from the junction transition layer. Unfortunately, the current limiting resistance, R, acting
in concert with the time constant it establishes with the diffusion capacitance of the diode, serves
to delay this vigorous reverse biasing for at least as long as the storage time, t
s
. But if a so-called
speedup capacitance, C, is appended as a shunting element across resistance R, as we suggest in
the modified circuit diagram of Figure (2.20), any sudden change in the input port voltage, v
i
(t),
is immediately transmitted to the diode terminals. Such an instantaneous voltage transfer derives
from the inability of a capacitance to change its terminal voltage suddenly as long as the capacit-

- 130 -

ance conducts finite current. In particular, at time t = 0, v
i
(0) = V
F
, and the diode voltage,
v
d
(0), is approximately V
on
. This latter voltage supports the steady state diode current, I
F
, de-
fined by (2-71). The indicated circuit speedup capacitance, C, is accordingly charged initially to
a voltage, (V
F
V
on
). This voltage is sustained at time t = 0+ when the input voltage changes
abruptly to the level, v
i
(0+) = V
R
. Consequently, the diode voltage swings instantly from V
on
at
time t = 0 to (V
on
V
R
) at time t = 0+. To the extent that V
R
is large, but certainly not so large
as to cause voltage breakdown of the PN junction, the diode is robustly reverse biased at the in-
stant that switch SW is thrown in the circuit. In principle therefore, most of the storage and
charging times can be eliminated, and zero storage time is theoretically possible. However, a
reality check properly infers that zero storage and charging times can be achieved only within the
hallowed, ivy-draped confines of academe. The shortfall of the foregoing qualitative arguments
is that the internal impedances associated with both input voltage levels are never zero, thereby
incurring an unavoidable nonzero delay between the input port of the network and the diode
terminals. Nonetheless, the turn off time of the indicated diode switching network can indeed be
reduced, and possibly significantly, by the simple capacitance compensation technique we have
advanced.
We begin the development of an analytical basis to the proposed compensation strategy
by observing in Figure (2.20) that the diode current, i
d
(t), which in general can be approximated
by the right hand side of (2-78), satisfies
| |
d d i d
d i d
d
dQ (t) Q (t) v (t) v (t) d
i (t) C v (t) v (t) .
dt R dt
~ + = + (2-85)

V
F
i (t)
d
V
R

t

=

0
R
+
v (t)
d
v (t)
i
S
W
C
+
v (t)
c

Figure (2.20). Turn off time compensation of the switching network in Figure
(2.17) through incorporation of a capacitance, C, across the cur-
rent limiting resistance, R.
At time t = 0+, v
i
(0+) = V
R
, v
d
(0+) remains approximately fixed at the turn on level, V
on
, and
the first term on the far right hand side of (2-85) is resultantly I
R
, as stipulated by (2-72).
Moreover, v
i
(t) changes abruptly at time t = 0, which means that its time derivative, dv
i
(t)/dt, for
t 0 is the impulse function, V
R
(t). Accordingly,
d d d
R R
d
dQ (t) Q (t) dv (t)
C I CV (t) for t 0,
dt dt
+ + ~ > (2-86)
which should lay to rest any feelings you may have harbored that the infamous delta function
is little more than mere theoretic fodder. The last result applies for all positive time for which
the diode sustains a net positive excess stored charge, Q
d
(t) and thus remains forward biased.

- 131 -

Since the diode voltage, v
d
(t), modulates only minimally while the diode is forward biased, the
current component, Cdv
d
(t)/dt, can be ignored (because of a small diode voltage derivative). It
follows that
d d
R R
d
dQ (t) Q (t)
I CV (t) for t 0,
dt
+ ~ > (2-87)
for which the excess charge solution is readily confirmed to be
( )
d
t
d d R d R F R
Q (t) I I I CV , t 0. e
= + + > (

(2-88)
The storage time, t
s
, which is defined implicitly by Q
d
(t
s
) = 0, now derives as
F R
s d
R d R
I CV
t 1 ,
I I
ln
| |
= +
|
\ .
(2-89)
which is assuredly smaller than the uncompensated charge storage time postured by (2-80). In
order to reduce time t
s
to zero (2-89) stipulates capacitance C in accordance with
d F d
R R
I Q (0 )
C ,
V V

= = (2-90)
where (2-75) has been recalled. The application of (2-90) theoretically causes zero storage time,
but you are once again reminded of the tacit neglect of Thvenin impedances associated with the
voltage levels, V
F
and V
R
. Impedances notwithstanding, (2-90) suffices as a pragmatic, first step
design guideline for reducing the charge storage time, and thus the overall switching time of a
PN junction diode.
2.4.2. SMALL SIGNAL DIODE OPERATION
In many electronic systems, a PN junction diode and/or the PN junctions implicit to
bipolar junction transistors and other semiconductor devices are called upon to deliver nominally
linear current or voltage responses to applied, time varying input signals. In these applications, a
necessary condition underpinning reasonably linear system operation is that each diode be biased
in its forward operating regime. In the on domain, the static volt-ampere characteristic curve
of a diode approximates current versus voltage linearity for at least suitably constrained perturba-
tions in the diode current. This nominal linearity requirement mandates two prerequisites whose
fulfillment lies within the purview of the circuit designer. First, consider the special case for
which all time varying input signals applied to the considered network are held to zero, but all
static sources deployed for biasing purposes remain activated. Such a condition establishes the
quiescent operating state of the considered network. This is to say that the network is quiet in
the sense that no time varying signals surface for electrical or electronic processing. In effect,
the network in question operates in a standby mode; that is, it is standing by, or just hanging out,
until it sees an applied input signal. The only observed branch currents and node voltages in
standby are therefore static, time invariant variables whose values are functionally dependent on
the topology of the quiescent network, the volt-ampere nature of the utilized diodes, and, of
course, the applied static sources. The sole and essential purpose of these static energy sources is
to pin the quiescent operating point, or Q-point, defined by [i
d
(t), v
d
(t)] = (I
dQ
, V
dQ
), of a subject
PN junction diode in a reasonably linear region of its static volt-ampere characteristic curve.
Second, the network responses generated exclusively by the applied time varying input
signals must establish reasonable volt-ampere linearity among all embedded diodes and other
nonlinear branch elements. This requirement implies that the resultant perturbations induced in
the quiescent operating points of all nonlinear devices embraced by the considered circuit must

- 132 -

be nominally linear functions of the applied input signals. Thus, in addition to requiring that the
Q-points of all PN junction elements reside in a nominally linear sector of their static characteris-
tic curves, another caveat to linear operation is incurred. In particular, in order for nonlinear de-
vices, such as PN junction diodes, to be capable of emulating volt-ampere linearity, they
mandate that the aforementioned signal-induced perturbations in the respective Q-points be suffi-
ciently small to inhibit operating point excursions into obviously substantive nonlinear regimes.
This constraint on signal responses is the basis for the ubiquitously encountered electronic sys-
tem lexicon of small signal operation, which is equivalently referred to as linearized operation.
2.4.2.1. Small Signal Operating Concepts
An analytical expansion of the concepts articulated in the preceding section commences
with a consideration of the generic electronic network example offered in Figure (2.21a). As is
indicated in this diagram, a signal source voltage, v
s
(t), together with its Thvenin resistance, R
s
,
is applied to the network input terminals, 1 and 2, one of which can be the network ground. Vol-
tage v
s
(t) has no static component and therefore contributes nothing to the determination of the
static currents and voltages of the diode and linear network. More than one signal source may be
used in conjunction with a given electronic network but in this initial foray into small signal
habitats, no loss of generality arises if we presume the presence of only one signal source. A sin-
gle PN junction diode, whose current is i
d
(t) and whose corresponding terminal voltage is v
d
(t), is
incident with terminals 3 and 4, where once again, one of the latter two terminals can be system
ground. In order to bias the junction diode in its forward volt-ampere regime, a supply voltage,
V
BB
, is applied between the fifth network terminal and ground. We assume that voltage V
BB
is
divorced of a signal component. Additionally, we disallow static or signal sources of energy
within the linear electronic network itself.
+
i (t)
d
+
v (t)
d
3
5
4
Linear
Network
R
s
+V
BB
(a).
v (t)
s
1
2
+
i (t)
d
+
v (t)
d
3
4
R
T
v (t)
T

V
kk

(b).

Figure (2.21). (a). Linear network driven by a time varying signal source, v
s
(t), whose Thvenin resistance is R
s
,
applied between terminals 1 and 2. Biasing for the indicated diode is arranged by the supply vol-
tage, +V
BB
. (b). Equivalent circuit showing the effective static voltage, V
kk
, the effective
Thvenin signal voltage, v
T
(t), and the Thvenin resistance, R
T
, witnessed by the diode at termin-
als 3 and 4.
Since the network to which the indicated PN junction diode is incident is linear, we can
supplant terminal pair 3 and 4 by a Thvenin equivalent circuit to model the subcircuit that
drives the diode branch. In the Thvenin representation of Figure (2.21b), V
kk
is a purely static
voltage whose value is zero when V
BB
is set to zero. Moreover, v
T
(t), the pertinent Thvenin sig-
nal voltage that excites the diode, is directly proportional to the applied signal voltage, v
s
(t),

- 133 -

while R
T
represents the Q-point value of the Thvenin, or output, resistance at terminals 3 and 4.
Because of the linearity of the network that couples the signal source to the diode load, voltage
v
T
(t) is, in addition to being directly proportional to signal voltage v
s
(t), is actually linearly
proportional to every branch current and node voltage within the subject linear network. In the
event that more than one input signal is applied, v
T
(t) becomes a linear superposition of the ef-
fects of all applied input signal voltages and currents. In the interest of completeness, the
mathematical computation of signal voltage v
T
(t) derives from Figure (2.22a) as the open circuit
voltage (meaning that the diode branch is removed) developed between terminals 3 and 4 under
the condition of V
BB
= 0. The convenience of null V
BB
derives directly from the presumption that
static energy source V
BB
harbors no signal component. Finally, resistance R
T
is the ratio, V
x
/I
x
, in
Figure (2.22b) with I
x
representing an independent mathematical ohmmeter current of arbitrary
value, while both V
BB
and v
s
(t) clamped to zero.
+
v (t)
T
3
5
4
Linear
Network
R
s
(a).
v (t)
s
1
2
+
V
x
3
5
4
Linear
Network
R
s
(b).
1
2
I
x
5 5

Figure (2.22). (a). Computation of the Thvenin signal, or open circuit, voltage, v
T
(t), that drives the PN junc-
tion diode in the network of Figure (2.21). The power supply voltage is supplanted by its small
signal value, which is usually zero. (b). Computation of the Thvenin resistance, R
T
, associated
with signal v
T
(t) in (a). This resistance is the voltage to current ratio, V
x
/I
x
, with both the input
signal set to zero and the power supply voltage set to zero.
In Figure (2.21b),
kk T T d d
V v (t) R i (t) v (t) , + = + (2-91)
with the implicit understanding that (2-1) defines the low frequency relationship of diode current
i
d
(t) to diode voltage v
d
(t). This relationship is plotted for a representative diode in the i
d
(t)-v
d
(t)
Cartesian plane of Figure (2.23) as the diode characteristic curve. Under quiescent signal
conditions, the input signal, v
s
(t), and hence the Thvenin signal voltage, v
T
(t), is zero, whence
(2-91) implies
d kk
d
T T
v (t) V
i (t) .
R R
= + (2-92)
When plotted in the aforementioned i
d
(t)-v
d
(t) plane, this expression is a straight line whose slope
is 1/R
T
, whose vertical (current) axis intercept is i
d
(t) = V
kk
/R
T
, and whose horizontal (voltage)
axis intercept is v
d
(t) = V
kk
. The straight line implied by (2-92) is indicated as the load line in
Figure (2.23). In effect, (2-92) and (2-1) comprise a system of two independent equations in the
diode current and voltage variables, i
d
(t) and v
d
(t), respectively. In accordance with our high
school algebra teachings, their simultaneous solution is the intersection of the load line with the
diode characteristic curve. This intersection uniquely defines the quiescent operating point of the
considered PN junction diode; namely, [i
d
(t), v
d
(t)] = (I
dQ
, V
dQ
), as marked in the figure of inter-

- 134 -

est. Of course, the Q-point, (I
dQ
, V
dQ
), can be discerned by substituting (2-1) into (2-92) and
thence solving iteratively for the diode voltage, v
d
(t) = V
dQ
, which supports the Q-point diode
current, I
dQ
, in accordance with
dQ T
V nV
dQ o
I I 1 . e
(
=
(

(2-93)
Alternatively, but arguably unnecessarily, the piecewise linear diode model of Figure (2.5b) can
be exploited to arrive at a maximally accurate estimate of the diode operating point.

Figure (2.23). Graphical interpretation of the first order electrical dynamics of the PN junction diode in the
network of Figure (2.21).
The quiescent operating point defined herewith is merely a single volt-ampere solution
of (2-91) that corresponds exclusively to all times for which the quiescent operating circums-
tance of zero input signal is observed. When signal is applied, the resultant diode current and
voltage vary with time in a manner that reflects the time variance proscribed by the Thvenin
signal voltage, v
T
(t). Assume for the moment that the variation of v
T
(t) is constrained in the time
domain to the closed and not necessarily symmetric interval, V
2
v
T
(t) V
1
. Since voltage
v
T
(t) merely superimposes with the static voltage, V
kk
, in (2-91), the immediate impact of nonzero
signal is witnessed as a variation of V
kk
. This variation proceeds from a maximum level of (V
kk
+
V
1
), through the Q-point manifested by V
kk
, to a minimum level of (V
kk
V
2
). We note that the
subject voltage change is effected without altering the series resistance, R
T
, in the circuit. Hence,
the slope of the originally highlighted load line is unaltered by the applied signal. Resultantly,
the load line plotted in Figure (2.23) is displaced, parallel unto itself, from the line labeled load
line for maximum input signal to the line branded load line for minimum input signal. The
resultant time domain, low frequency solutions for the diode current and diode voltage, which
necessarily reside on the diode characteristic curve in the subject figure, are constrained to lie on
the emboldened diode curve segment traced by the intersection of the perturbed load line and the
diode characteristic curve. This segment is labeled in Figure (2.23) as locus of Q-point excur-
sion. In the present case, the diode current is seen as varying from a maximum value of I
d1
,
corresponding to v
T
(t) = V
1
, -to- a minimum current value of I
d2
, which is the result of v
T
(t) =
V
2
. The diode voltage perturbation accompanying these current changes is minimal, as is indi-

- 135 -

cated in Figure (2.23), owing to the steepness of the slope of the on region diode characteristic
curve. This V-I curve steepness supports the previously espoused significant diode current
sensitivity to diode voltage in the forward bias domain.
2.4.2.2. Small Signal Diode And Network Model
The locus of Q-point excursion in Figure (2.23) suggests viscerally that for sufficiently
small V
1
and V
2
, the observed net current change, (I
d1
I
d2
), about the quiescent diode current,
I
dQ
, is likely to approximate a linear function of the corresponding, and necessarily small, diode
voltage perturbation about its Q-point, V
dQ
. The need for suitably constrained input voltages is
underscored by a casual consideration of the effect of large V
2
. In particular, large V
2
shifts the
original load line downward to such an extent that the intersection of the perturbed load line with
the diode volt-ampere characteristic curve may lie on the obviously nonlinear knee of the diode
V-I curve. If this were the case, the presumption of linearity between current and voltage
perturbations is rendered dubious. The figure at hand also suggests that the constrained locus of
Q-point excursion, which embraces only a local region about the diode Q-point, as opposed to
the entire characteristic curve, is tailor made for a Taylor series expansion of the diode
characteristic curve about the Q-point (pun intended). In particular, we exploit Taylors theory
to write,
( ) ( ) ( )
2 3
2 3
d d d
d dQ d dQ d dQ d dQ
2 3
d
Q
d d
Q Q
di d i d i 1 1
i I v V v V v V ,
dv 2! 3!
dv dv
= + + + + .
(2-94)
where the time domain notation appended to the diode current and voltage has been discarded in
favor of symbolic simplicity. We need to understand that each derivative on the right hand side
of this relationship is evaluated at the quiescent operating point of the diode; that is, at [i
d
(t),
v
d
(t)] (i
d
, v
d
) = (I
dQ
, V
dQ
). Therefore, the coefficient of (v
d
V
dQ
)
i
, for i = 1, 2, 3, is a con-
stant, independent of the net diode current and diode voltage, i
d
and v
d
, respectively.
The infinite power series of (2-94) is foreboding. However, its circuit-oriented implica-
tions are crucial to the computationally efficient analysis of properly biased, approximately li-
near, electronic networks that are driven by acceptably small signals. To wit, we see that the vol-
tage difference, (v
d
V
dQ
), represents the positive or negative change in the diode Q-point
voltage that is incurred exclusively by the applied input signal. This voltage difference is
meaningfully symbolized as the signal-induced voltage change, V
sig
, about the Q-point diode vol-
tage, V
dQ
; namely,
sig d dQ
V v V . (2-95)
We can advance an analogous substitution for the signal induced change, (i
d
I
dQ
), in the drain
current; that is,
sig d dQ
I i I . (2-96)
Equation (2-94) can therefore be couched as,
2 3 4
2 3 4 d d d d
sig sig sig sig sig
2 3 4
d
d Q
d d Q
Q Q
di d i d i d i 1 1 1
I V V V V .
dv 2! 3! 4!
dv dv dv
= + + + + . (2-97)
In light of the constant nature of each derivative term in this expression, (2-97) advances a signal
component of diode current that is dependent, albeit nonlinearly, on the signal component of di-
ode voltage. Now, if the peak, root mean square, or instantaneous value of the signal-induced
component, V
sig
, of diode voltage is small, the square of V
sig
is smaller, the cube of V
sig
is smaller

- 136 -

yet, and in general, all non-unity powers of V
sig
approach negligible proportions. But in addition
to small V
sig
, or perhaps in lieu of adequately small V
sig
, a nominally linear diode characteristic in
the neighborhood of the Q-point generates a derivative di
d
/dv
d
, which is virtually constant even
prior to numerically evaluating this derivative at the Q-point. In turn, the second and all higher
order derivatives of the diode current with respect to the diode voltage approach zero (prior to
their evaluation at the Q-point). Thus, for small V
sig
and/or for reasonable linearity of the diode
characteristic curve in the immediate neighborhood of the diode Q-point, (2-97) collapses to
d
sig sig
d
Q
di
I V ,
dv
~ (2-98)
which comprises little more than a modestly extended version of Ohms law. It is crucial to
understand that (2-98) is a valid relationship only for the nominally linear volt-ampere locus of
Q-point excursion in Figure (2.23). Specifically, for sufficiently small signal voltages and/or
nominal linearity of the diode characteristic curve in the neighborhood of the diode Q-point, the
signal component, I
sig
, of the diode current relates to the signal component of diode voltage, V
sig
,
in accordance with the classic Ohms law expression,
sig
sig
d
V
I .
r
~ (2-99)
In (2-99), parameter r
d
is termed the small signal resistance of the subject PN junction diode.
With
d
d d
Q
di 1
,
r dv
= (2-100)
r
d
is clearly the inverse of the slope of the diode characteristic curve at the Q-point. Recalling
(2-1) or (2-3),
dQ T
T T
d
V nV
dQ
o
nV nV
r .
I
I e
= ~ (2-101)
Observe in the last result that progressively larger diode Q-point currents breed correspondingly
smaller diode resistances. Accordingly, PN junction diodes operated at large quiescent currents
emulate short circuits for small input signals. This contention synergizes with the observation in
Figure (2.23) that the diode voltage changes garnered for relatively significant diode current
changes are very small. Indeed, if the slope of the diode characteristic curve in the forward bias
regime were vertical in Figure (2.23), the diode voltage change for any change in diode current is
zero, as is r
d
in (2-100).
Before we venture further, there are two issues in need of crystal clarity. The first re-
sponds to the traditional electronic circuits query, How small does the input signal need to be to
validate the small signal approach to electronic circuit analysis? At risk of being type cast as a
cavalier professor, the only accurate answer that can be provided is that the signals applied to an
electronic network must be small enough to validate the approximation that permits reducing (2-
97) to (2-98). In concert with this response, we should understand that a small signal could
actually be reasonably large if the nonlinearities the signal encounters are not severe. As an ex-
treme example of this special case, suppose that our diode were postured as a linear, static volt-
ampere characteristic (to be sure, a diode is never linear). Then, the first derivative of diode cur-
rent with respect to diode voltage on the right hand side of (2-97) is a constant. It follows that all
higher order derivatives are zero, which means that the higher order terms in (2-97) are entirely
inconsequential, regardless of the amplitude of the applied signal. In a word, the requisite

- 137 -

smallness of the applied signal is largely determined by the degree of nonlinearity of the vari-
ous electronic elements embedded in the circuit of interest. And to a point, this degree of
nonlinearity might indeed be minimized through prudent biasing. Our vehicle for this desirable
design tack involves ensuring that the Q-points for our nonlinear elements lie in the nominally
linear regimes of their respective volt-ampere characteristic curves. On the other hand, an
unwelcomed and unavoidable profound nonlinearity may require the application of signal
processing to reduce the applied signals to sufficiently small proportions. In this way, the higher
order terms in (2-97), which depend on various powers of the signal, are rendered progressively,
and hopefully adequately, smaller.
The second important issue is that resistance r
d
in (2-100) or (2-101) is merely a special
case of the resistance, r
dm
, introduced in (2-6) in conjunction with the piecewise linear model of a
PN junction diode. In particular, r
dm
, as introduced earlier, is the inverse of the slope of the static
diode characteristic curve evaluated at an arbitrary volt-ampere coordinate, (I
dm
, V
dm
). For piece-
wise linear analyses, current I
dm
is generally selected as the estimated maximum current con-
ducted by the diode under low frequency operating circumstances. On the other hand, r
d
in (2-
100) is a similar characteristic curve inverse slope, but it is evaluated specifically at the quiescent
operating point of the diode. It follows that r
dm
r
d
if I
dm
I
dQ
. In general, resistance r
d
is about
as small as the scant few ohms we witnessed previously as a numerical measure of resistance r
dm
.
If (2-95), (2-96), (2-99), and (2-100) are merged with the power series expansion of (2-
94),
sig d dQ
d dQ dh sig dQ dh sig
d d
V v V
i I I (V ) I I (V ) ,
r r
= + + = + + (2-102)
where
k
k
d
dh sig sig
k
d k 2
d i 1
I (V ) V
k !
dv
=
| |
= |
|
\ .
(2-103)
is the sum of all nonlinear current components in (2-94). Equation (2-102) leads to the PN junc-
tion diode behavioral model advanced in Figure (2.24a), where in practice, the power series
represented by the high order current, I
dh
(V
sig
), is truncated at user discretion after a number of
terms that is consistent with the accuracy requirements of the analysis task. If V
sig
is small and/or
the diode volt-ampere characteristic curve is reasonably linear in the immediate neighborhood of
its quiescent operating point, I
dh
(V
sig
) is negligible in comparison to the sum of the first two
terms on the right hand side of (2-102). In this situation, (2-102) collapses to
sig d dQ
d dQ dQ
d d
V v V
i I I ,
r r
~ + = + (2-104)
and the behavioral structure in Figure (2.24a) becomes the equivalent circuit given in Figure
(2.24b). Recalling (2-96), the network model in Figure (2.24c) can be promoted as a simple
small signal alternative to the topology in Figure (2.24b). It may be somewhat disconcerting that
all of the foregoing mathematics and associated engineering discourse combine to give rise to a
low frequency small signal model of a diode that is no more complicated than a single, two ter-
minal resistor. And why not a simple resistance? The PN junction is a two terminal device.
And if this two terminal device is modeled by a linear V-I characteristic curve, a resistor is the
only element possible in a low frequency, circuit level representation of the subject diode.
The relevance of the simple small signal model in Figure (2.24c) can best be appre-
ciated by returning to the network representation in Figure (2.21b) and using the last result to

- 138 -

quantify the diode current, i
d
(t). Specifically,
i (t)
d
i (t)
d
(a).
(b).
r
d
+
V
dQ

V
dQ

V
sig
+
v (t)
d
I
dQ
I
sig
I (V )
dh sig
+
V
sig
+
v (t)
d
i (t)
d
r
d

V
dQ

I
dQ
I
sig
+
V
sig
+
v (t)
d
(c).
I
sig
r
d
+
V
sig

Figure (2.24). (a). The behavioral model of a PN junction diode. The diode terminal voltage, v
d
(t), is pre-
sumed to be the superposition of a Q-point voltage component, V
dQ
, and a time varying sig-
nal component, V
sig
. (b). The model of (a) simplified to reflect the presumption of small in-
put signals and/or reasonable linearity of the diode characteristic curve in the immediate
neighborhood of the operating point. (c). Small signal, low frequency model of the PN junc-
tion diode.
sig
kk T T dQ sig dQ
d
V
V v (t) R I V V .
r
| |
+ = + + +
|
\ .
(2-105)
But the static voltage, V
kk
, appears in the output port loop of the network solely to bias the diode
at a suitable Q-point. This is to say that under quiescent operating conditions for which v
T
(t) = 0
and hence, V
sig
= 0,
kk T dQ dQ
V R I V . = + (2-106)
If we insert (2-106) into (2-105), we arrive at the network equilibrium relationship,
( ) ( )
sig
T T d sig T d
d
V
v (t) R r I R r ,
r
= + = + (2-107)
which corresponds to the small signal network model submitted as Figure (2.25).
At least three important sidebars accompany the modeling disclosure in Figure (2.25).
First and perhaps most obviously, the diode in the circuit of Figure (2.21b) is merely supplanted
by the small signal, two terminal, purely resistive diode model advanced in Figure (2.24c). Sec-
ond, the network model in Figure (2.25) at hand is incapable of generating any information about
the quiescent currents and voltages indigenous to the diode, largely because the static supply

- 139 -

used to establish the Q-point is inherently vanquished by the small signal analysis methodology.
In fact, the practical utilization of the small signal network model requires a priori knowledge of
the quiescent operating point of the diode in order that the small signal diode resistance, r
d
, can
be computed in accordance with (2-101). Third, the current, I
sig
, supported by the circuit of Fig-
ure (2.25) is not the net diode current, i
d
. Rather, I
sig
is only the small signal component of the
diode current. The net diode current derives from (2-96), which obviously requires a numerical
delineation of the Q-point diode current, I
dQ
. Similarly, the small signal diode voltage, V
sig
=
r
d
I
sig
in Figure (2.25) is not the net diode voltage, v
d
, but is, in fact, only the small signal compo-
nent of this diode voltage. The overall diode voltage derives from (2-95), whose application re-
quires a numerical value for the diode Q-point level, V
dQ
.
+
i (t)
d
+
v (t)
d
3
4
R
T
v (t)
T

V
kk

I
sig
r
d
+
3
4
R
T
v (t)
T
+
V
sig

Figure (2.25). Equivalent small signal model for the output port of the network addressed in Figure (2.21).
A final observation is that the small signal diode model of Figure (2.24c), as well as the
network model it configures in Figure (2.25), is limited to low frequency signal processing
conditions. If the Fourier spectrum implicit to the Thvenin signal voltage, v
T
(t), personifies
critically important high frequencies or if timing issues associated with the transient response to
v
T
(t) are relevant to the engineering problem at hand, the small signal diode model must be
embellished to include the effects of charge storage at the junction. This modeling enhancement
is a straightforward task since charge storage phenomena, as witnessed in conjunction with the
discussion surrounding (2-85), precipitates only a single additional current component to the net
observed diode current. This current is recalled to be dQ
d
(t)/dt, where Q
d
(t) represents the excess
charge stored in the junction transition region. In turn, the time derivative of the excess charge is
equivalent to currents conducted by the shunt interconnection of two capacitances, as inferred by
the high frequency small signal diode model postulated in Figure (2.26). The capacitance, C
dQ
,
is the quiescent state value of the junction diffusion capacitance, which by (2-69) derives as
d dQ
dQ
T
I
C ,
nV
~ (2-108)
where, of course, t
d
is the average lifetime of free charge carriers that transit the transition layer
of a forward biased diode, n is recalled as the junction injection coefficient, and V
T
is the
Boltzmann voltage. Appealing to (2-70), C
jQ
in the model of Figure (2.26) is
j j
m m
dQ T
on
jQ jo jo
j j
V nV
V
C C 1 C 1 .
V V

| | | |
~ ~ | |
| |
\ . \ .
(2-109)
In (2-109), use is made of the fact that the diode turn on voltage, V
on
in (2-70), lies below the di-
ode Q-point voltage, V
dQ
, by the amount, nV
T
.

- 140 -

i (t)
d
+
V
dQ

V
sig
+
v (t)
d
I
sig
r
d
+
V
sig
C
dQ
C
jQ

Figure (2.26). High Frequency, small signal model for the PN junction diode. Capacitance C
dQ
is the
Q-point value of the diffusion capacitance of the junction, while C
jQ
represents the
quiescent state value of the depletion capacitance in the forward bias regime.
EXAMPLE #2.4:
In the simple attenuator shown in Figure (2.27a), the input signal is a small
amplitude sinusoid, v
s
(t), whose phasor is denoted in Figure (2.27b) by the vol-
tage source, V
s
. Resistance R includes the internal resistance of the signal
source. The static voltage, V
BB
, is used to bias the diode in its forward regime
where the quiescent diode current is set to I
dQ
and the corresponding quiescent
diode voltage is V
dQ
. If the small signal resistance of the diode at the indicated
Q-point is r
d
and if the effective total capacitance across the diode is C
T
(diffu-
sion plus depletion components), derive an expression for the transfer function,
H(je) = V
o
/V
s
. Additionally, determine the radial 3-dB bandwidth, say B, of the
circuit. Finally, explain the low frequency operation of the attenuator.
SOLUTION #2.4:
(1). The disclosures of the present section of material forge the small signal equivalent circuit of
the attenuator shown in Figure (2.27b). In this model, resistance r
d
is defined by (2-101),
while capacitance C
T
, is the sum of the capacitances, C
dQ
and C
jQ
in (2-108) and (2-109),
respectively. Voltage V
BB
does not appear in the small signal model because it is deployed
exclusively to establish the quiescent operating point. The output phasor response, V
o
, is
proportional to the phasor, V
s
, of the applied input sinusoid. Alternatively, we can say that
V
BB
, which is a constant supply voltage, must be replaced by a short circuit because its small
signal value, like the small signal value of any constant voltage or current, is zero. It is also
important to recall that the small signal model of a diode, or of any other nonlinear element,
can never surrender any information regarding the circuit Q-point.
(2). An inspection of the circuit in Figure (2.27b) foretells
( )
( )
d d
o d T d
d
s d T
d T
r r
V 1 jr C r R
H j .
r
V 1 j r R C
R
1 jr C
+ +
= = =
+
+
+
(E4-1)
In this result, the zero frequency value, H(0), of the network transfer function, which is
immediately evident from an inspection of the subject circuit model, is

- 141 -

i (t)
d
+
V
BB

v (t)
s
V
s
+
v (t)

d
r
d
C
T
R R
v (t)
o
V
o
(a). (b).

Figure (2.27). (a). Simple attenuator circuit addressed in Example #2.4). The static supply voltage,
V
BB
, establishes a diode quiescent operating point at [i
d
(t), v
d
(t)] = (I
dQ
, V
dQ
). Observe
that the output response, v
o
(t), in the time domain is identical to the voltage, v
d
(t),
developed across the PN junction diode. (b). The small signal, high frequency model
of the attenuator in (a).
( )
d
d
r
H 0 ,
r R
=
+
(E4-2)
and by (2-101),
( )
d T
d T dQ
r nV
H 0 .
r R nV RI
= =
+ +
(E4-3)
Accordingly, as I
dQ
is varied, through changes in the input supply voltage, V
BB
, the zero fre-
quency gain (which is always less than one) can be made to vary over a prescribed range.
For example, maximum gain, or minimum attenuation, is offered by small values of I
dQ
,
while minimum gain (corresponding to maximal attenuation) is provided by large I
dQ
.
(3). The radial 3-dB bandwidth, B, is the value of the radial signal frequency, , for which the
magnitude of the network transfer function is 3-dB below, or a factor of root two smaller
than, the zero frequency gain of the circuit. Since the zero frequency gain of the circuit
undergoing investigation is little more than the numerator term on the right hand side of (E4-
1), the 3-dB bandwidth evolves by mere inspection of the subject expression. In particular,
( )
( ) d T d T d dQ jQ
1 1 1
B ,
r C r R C r C C
= ~ =
+
(E4-4)
where the reasonable presumption that R >> r
d
has been invoked. If (2-108) is substituted
into (E4-4),
T
d jQ
dQ
1
B ,
nV
C
I
~
| |
+ |
|
\ .
(E4-5)
which projects inverse carrier lifetime as a limitation on the achievable 3-dB bandwidth of the
circuit. In fact, the bandwidth approaches 1/t
d
only for the maximal attenuation case precipi-
tated by large quiescent diode current, I
dQ
.
Although the circuit considered herewith can function as an attenuator, it is hardly a candi-
date for the attenuator of the month award. We can immediately perceive several shortfalls to
the circuit. For example, the attenuation provided by the circuit at low frequencies is of the
order of the ratio, r
d
/R, which implies an attenuation range of roughly 1/10 (20 dB) to 1/100

- 142 -

(40 dB). While this factor of ten or so attenuation range is appropriate to numerous system
applications, it comes at the price of enormous changes in the quiescent drain current, which
in turn spawns concerns about circuit power dissipation and circuit linearity. Moreover, the
degree of attenuation is sensitive to junction operating temperature because resistance r
d
is
proportional to the Boltzmann voltage (which is directly dependent on absolute temperature)
and inversely dependent on diode current. As we argued earlier in this chapter, the signifi-
cant temperature sensitivity of PN junction diode current in the absence of appropriate
compensation is legendary. One attribute of the structure is that because the diode small sig-
nal resistance, r
d
, is very small, its 3-dB bandwidth can theoretically be well into the arena of
several gigahertz. Unfortunately, this bandwidth is itself dependent on temperature, as well
as on the attenuation factor, because of its functional dependence on Q-point diode current.
Another arguable attribute is circuit simplicity. But while simplicity is always nice from the
perspectives of reliable processing and reproducible manufacturing, not all simple designs
prove satisfying.
EXAMPLE #2.5:
The application and implications of the concepts underlying small signal analy-
sis techniques are not restricted to PN junction diodes. They are broadly perti-
nent to all two terminal elements that exhibit nonlinear volt-ampere characteris-
tics. As is demonstrated in subsequent chapters, small signal analysis methods
can even be extended to embrace nonlinear multiport networks. To these ends,
consider Figure (2.28), which depicts a two terminal resistance for which the low
frequency volt-ampere characteristic abides by the nonlinear relationship,

( )
h
2
h h
k
0, V V
I ,
V
V V 1 , V V
V
|
<
| |
=
| + >
|
\ .

where = 0.05 siemens/volt, V
h
= 0.6 volt, and V
k
= 15 volts. Evaluate the small
signal resistance, say r, of this nonlinear element when it is biased at the quies-
cent voltage, V = V
Q
= 850 mV.
I
+
V
( )
h
2
h h
k
0, V V
I
V
V V 1 , V V
V
<
= | |
+ >
|
\ .

Figure (2.28). The two-terminal nonlinear resistor stu-
died in Example #2.5.
SOLUTION #2.5:
(1). For | = 0.05 siemens/volt, V
h
= 0.6 volt, and V
k
= 15 volts, the quiescent current, I
Q
,

- 143 -

conducted by the subject resistance for a quiescent terminal voltage, V
Q
, of 0.85 volt, is
( )
2
Q
Q Q h
k
V
I V V 1 3.302 m A .
V
| |
= + =
|
\ .
(E5-1)
(2). For V > V
h
, the linear approximation of the Taylor series expansion of the given volt-ampere
characteristic curve about the stipulated quiescent operating point is
( )
Q Q
Q
d I
I I V V ,
dV
~ + (E5-2)
where I
Q
= 3.302 mA, and V
Q
= 0.85 volt. The indicated derivative evaluated at the Q-point
represents the inverse of the desired small signal resistance, r. We determine that
Q Q
Q
Q k k
Q
I V
1 d I
4I 1 26.63 m .
r dV V V V
| |
= + + =
|
+
\ .
(E5-3)
It follows that the small signal resistance at V = V
Q
= 0.85 volt is r = 37.56 O.
-10
-5
0
5
10
15
20
0 0.2 0.4 0.6 0.8 1 1.2
Vol tage, V (vol ts)
C
u
r
r
e
n
t
,

I

(
m
A
)
V
Q
I
Q
Nonlinear
Resistance
Characteristic
Linear Taylor
Series Approximation

Figure (2.29). Plot of the volt-ampere characteristic of the nonlinear resistance examined in Example #2.3.
Superimposed on the subject characteristic is the linear approximation of the Taylor series
expansion of the curve about the Q-point.
The nonlinear resistance addressed herewith emulates a diode in the sense that the current
conducted by the element is zero for voltages less than an effective threshold level, V
h
, while
for voltages larger than V
h
, the current conducted by the element rises monotonically.
Actually, the element at hand is a diode realized with a metal-oxide-semiconductor field-
effect transistor (MOSFET), as you will learn in a subsequent chapter. The determination of
the requested small signal resistance is straightforward, amounting to little more than an
evaluation of the slope of the device characteristic curve at the stipulated quiescent operating
point. An appreciation of the accuracy and pertinence of the resistance computation is
another matter that is worthy of at least tacit attention. To this end, the device characteristic
curve is plotted in Figure (2.29), as is the Taylor series approximation projected by (E5-2).
An even casual comparison of the actual curve and the straight line Taylor approximation,

- 144 -

which is foundational to the small signal resistance model, reveals the potential for significant
modeling errors if (E5-2) is invoked carelessly in an application. For example, if the
differences between the two curves are to be held to within 10%, the terminal voltage must
be restricted to the range, 0.791 volt V 0.963 volt, which corresponds to a current
excursion from 1.91 mA to 9.91 mA.
2.4.3. STEADY STATE SINUSOIDAL RESPONSE
The PN junction diode and all other semiconductor elements inherently pose nonlinear
volt-ampere characteristics. Their ability to emulate volt-ampere linearity requires the satisfac-
tion of at least two conditions. The first of these is that the time domain amplitudes of applied
voltage signals must be limited so that diode operation is constrained to a restricted neighbor-
hood of the quiescent operating point of the considered diode. The second condition is that the
Q-point must reside in a region of the characteristic curves that boast reasonable volt-ampere
linearity. The immediate ramification of nonlinearity is that an applied single frequency sinusoid
of arbitrary voltage amplitude generates distortion. Unlike a linear branch element, the current
response to such a sinusoid is not merely a scaled or delayed replica of the excitation. Instead,
the response contains, in addition to a signal component at the fundamental frequency of the ap-
plied sinusoid, harmonics of this fundamental frequency. A common way to quantify the sever-
ity of observed distortion, and thus the extent to which the considered element or circuit is nonli-
near, entails an evaluation of the total harmonic distortion, THD. The THD effectively compares
the amplitude of each harmonic component of the observed sinusoidal response with the re-
sponse amplitude evidenced at the fundamental frequency.
Gaining an appreciation of the engineering implications of harmonic distortion begins
with our returning to the PN junction diode of Figure (2.24a). In that circuit, we assume that vol-
tage V
dQ
biases the diode in its forward operating regime; that is V
dQ
is somewhat larger than the
diode turn on voltage, V
on
. Moreover, we assume further that the indicated signal voltage, V
sig
,
applied to the diode is the sinusoid,
( )
sig m
V V t , cos = (2-110)
where V
m
is the voltage amplitude, and is the radial frequency of the applied sinusoid. If is
not so large as to require a consideration of charge storage phenomena at the PN junction, (2-1)
is the applicable volt-ampere relationship. In this case, the diode current, i
d
(t), corresponding to
a net diode voltage of
( )
d dQ m
v (t) V V t cos = + (2-111)
is
( ) ( ) dQ m T dQ m T
V V t nV V V t nV
d o o
cos cos
i (t) I 1 I , e e
+ + (
= ~
(

(2-112)
where, as usual, the unity term within the bracketed quantity is ignored. Such tacit neglect is
possible because of the exponentiation of a reasonably large Q-point voltage, V
dQ
. The quiescent
diode current, I
dQ
, which is the diode current flowing under the zero signal circumstance implied
by V
m
= 0, is
dQ T
V nV
dQ o
I I . e ~ (2-113)
We therefore couch (2-112) in the form,
m
X t
d dQ
cos
i (t) I , e ~ (2-114)
where

- 145 -

m
m
T
V
X
nV
= (2-115)
is the sinusoidal signal amplitude normalized to the effective Boltzmann voltage, nV
T
.
Equation (2-114) defines the diode current response to a voltage input comprised of the
superposition of a biasing level, V
dQ
, and a sinusoidal signal whose amplitude is V
m
. The expres-
sion in question can be expanded into its Fourier series to uncover its constituent frequencies, as
well as to reveal the amplitudes associated with these individual frequency components. In
particular
[3]
,
( ) ( ) ( )
d dQ o m n m
n 1
i (t) I B X 2 B X nt , cos
=
(
~ + (
(

(2-116)
where, as it materializes, B
n
(X
m
) is the n
th
order modified Bessel function expressed as a function
of the normalized sinusoidal signal amplitude, X
m
. While tabularized numerical data for mod-
ified Bessel functions can be found in the archival literature
[4]
, two useful and reasonably accu-
rate empirical analytical expressions are
( )
( )
m
n
m
m
n m
X 2
m
m m
X 2
for X 5, & n 0, 1, 2, 3,
n!
B X .
n
1 for X 5, & n 0, 1, 2, 3,
2X 2 X
e
< =
~
| |
> = |
|
\ .
(2-117)
Equation (2-116) projects that the amplitude at the fundamental frequency component
of diode current is 2B
1
(X
m
). The relationship additionally advances an n
th
harmonic amplitude of
the diode current of 2B
n
(X
m
). We shall find it convenient to introduce the amplitude ratio,
o
n
(X
m
), as
( )
( )
( )
( )
( )
n m n m
n m
1 m 1 m
2B X B X
X for n 2, 3, 4, 5, .
2B X B X
= = (2-118)
Then, the degree of nonlinearity in a device or a system is easily quantified as the total harmonic
distortion, THD, which is given by
( )
( )
( )
2
n m
2
n 2
n m 2
n 2
1 m
B X
THD X .
B X
o
=
=
=

(2-119)
A consideration of the foregoing definition suggests that the THD is the ratio of the root mean
square contribution of all harmonics of the fundamental frequency component to the root mean
square value of the fundamental frequency component itself. Alternatively, it may be viewed as
the average net power contributed by the harmonics, normalized to the average power associated
with the fundamental frequency component. Although the total harmonic distortion is often
quantified as a percentage, the THD can be cast in units of decibels. To this end,

- 146 -

( )
( )
( )
2
n m
2
n 2
(dB) n m 2
n 2
1 m
B X
THD 20 (THD) 10 X 10 ,
B X
log log log o
=
=
(
(
(
(
( = = =
(
(
(

(
(

(2-120)
where the indicated logarithms are executed to base 10. Thus, for example, THD
(dB)
= 60 dB
infers that THD = 0.1%, which means that the fundamental frequency component of the applied
signal boasts an amplitude that is 1,000-times larger than the root mean square contribution of
the amplitudes of all harmonic components. It should be understood that while (2-119) and (2-
120) are applicable to all nonlinear elements excited by a single frequency sinusoid whose
normalized amplitude is X
m
, (2-118) applies only to PN junctions excited by a sinusoidal voltage.
Moreover, (2-118) is restricted to low signal frequencies in that the diode characteristic equation
of (2-112), which tacitly ignores charge storage phenomena, serves as the basis for the current
response formulation in (2-116).
0.0001
0.001
0.01
0.1
1
0 1 2 3 4 5 6 7 8 9 10
Normal i zed Si gnal Ampl i tude, X
m
N
o
r
m
a
l
i
z
e
d

H
a
r
m
o
n
i
c

A
m
p
l
i
t
u
d
e
o
2
(X
m
)
o
3
(X
m
)
o
4
(X
m
)
o
5
(X
m
)

Figure (2.30). The normalized harmonic amplitudes, o
n
(X
m
), as defined by (2-118), plotted as a function of the
normalized amplitude of a sinusoid applied to a biased PN junction diode. Harmonics through
only the fifth order are explicitly considered.
Figure (2.30) depicts the behavior of the amplitude ratio, o
n
(X
m
), as a function of the
normalized signal amplitude, X
m
, for the second through fifth harmonics. The curves depicted in
this plot derive from tabulated values of the modified Bessel function, as opposed to relying on
the approximate relationships given in (2-117). Note that for any value of X
m
, these amplitude
ratios decrease monotonically with the order, n, of the harmonic, although the amount of de-
crease diminishes with progressively larger X
m
. This is to say that for reasonably small signal
amplitudes, higher order harmonics have a markedly decreasing impact on the overall diode cur-
rent response to an applied sinusoidal voltage. We might logically anticipate the foregoing
observation, just as we might expect the observation that the harmonic amplitude ratio for any
harmonic order increases monotonically with normalized signal amplitude. Indeed, the harmonic

- 147 -

ratio appears to rise toward one for large signal amplitudes, independent of the actual harmonic
order.
The curves in Figure (2.30), coupled with (1-119), generate the total harmonic distor-
tion plot in Figure (2.31). Although (2-119) is an infinite series, only terms through the fifth har-
monic are considered in the latter figure
7
. The news proclaimed by Figure (2.31) is not good in
that it shows that the total harmonic distortion rises rapidly with applied signal amplitude. For
example, 10% diode current distortion to an input sinusoid, which is hardly an acceptable THD
in the majority of modern communication systems, requires a normalized signal amplitude of
only about X
m
= 0.4, which corresponds at room temperature to a sinusoidal signal amplitude of
approximately 10.4 mV. In short, an applied sinusoid whose amplitude is around 10 mV pro-
duces about 10% of THD.
0
20
40
60
80
100
120
0 1 2 3 4 5 6 7 8 9 10
m
T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

(
%
)

Figure (2.31). Total harmonic distortion, plotted as a function of the normalized amplitude of a sinusoid applied
to a biased PN junction diode. Harmonics through only the fifth order are explicitly considered.
Harmonic distortion aside, another disquieting effect of a large input signal amplitude is
an effective shift in the quiescent operating point imposed on the device undergoing examina-
tion. In (2-116), each of the infinity of signal components embodied by the second term in the
bracketed quantity on the right hand side has zero average value because each of these terms is a
simple sinusoid. It follows that the average value, say I
DC
, of the diode current is
( )
DC dQ o m
I I B X , = (2-121)
and not simply the quiescent current, I
dQ
, that we may have logically surmised. As we highlight
in Figure (2.32), which plots the current ratio, I
DC
/I
dQ
= B
o
(X
m
) (using tabulated Bessel function

7
SPICE circuit simulation software examines the effects of nine harmonic terms in the course of executing its
harmonic distortion analyses. For most manual analyses, a consideration of the first three to five harmonics
generally proves sufficient.

- 148 -

data), the average current increases dramatically with signal amplitude from the Q-point current
value evidenced at low input signal amplitudes. While the drama implied by the subject figure
may not have been initially predicted, we can easily rationalize an increase in the average current
above the Q-point value. In particular, the diode in the circuit of Figure (2.24a) prohibits a
wrong way or negative diode current, i
d
(t), in the steady state. It necessarily converts the ap-
plied sinusoidal voltage to a unidirectional, positive diode current. In the vernacular of PN junc-
tion diodes, the diode is said to rectify the response current, which is equivalent to asserting that
it converts the applied sinusoid, which has periodic positive and negative voltage values, to a
current that is forever positive. Because this diode current response is exclusively positive over
time, it has nonzero average value. This average naturally merges with the quiescent current
value set under zero signal conditions. An implicit undertone of the plot in Figure (2.32) is that
large amplitude sinusoids applied across PN junction diodes may comprise a destructive
phenomenon in that the large average current values resulting from aggressively large signal
amplitudes may cause catastrophic thermal stress within the ohmic regions of the device.
1
10
100
1000
10000
0 1 2 3 4 5 6 7 8 9 10
m
I
D
C
/
I
d
Q

Figure (2.32). The ratio of the average diode current to the Q-point diode current as a function of the
normalized signal amplitude, X
m
.
While the total harmonic distortion metric is a reasonable and relatively simple
quantification of the nonlinearity implicit to a response of interest, its engineering implication is
somewhat masked by the requisite mathematics of Fourier components and Bessel functions. In
an attempt to attach meaningful engineering perspective to the THD, return to (2-112) and note
therein that the maximum achievable diode current, say I
dmax
, is
( ) dQ m T
m
V V nV
X
dmax o dQ
I I I , e e
+
= = (2-122)
where (2-113) and (2-115) are exploited. It follows from (2-114) that the diode current, i
d
(t),
normalized to its maximum value, I
dmax
, is
( )
m
m
m
X t
dQ X t 1
d
X
dmax
dQ
cos
cos
I
i (t)
,
I
I
e
e
e

= = (2-123)
which is depicted graphically in Figure (2.33). Observe in the subject figure that for small X
m
,
and in particular, X
m
= 0.4, the diode current response closely resembles a cosine wave despite

- 149 -

the sizeable 10% THD engendered by this normalized signal amplitude. At X
m
= 2, which
corresponds to 45.5% THD, distortion of the applied cosine voltage wave is plainly evident in
the diode current response. For excessively large X
m
and specifically, X
m
= 10, which reflects
better than 120% THD, the observed distortion is so extreme that the diode current begins to
resemble a reasonably narrow, periodic pulse response. This pulse-like waveform derives from
the fact that large signal amplitudes attempt to induce a negative diode current, which is, of
course, impossible in the steady state. We shall witness later in our electronics dialogue that the
pulse model for the large amplitude sinusoidal response of a nonlinear network comprises the
basis for predicting the amplitudes of the self-sustaining responses in sinusoidal oscillators.
0
0.2
0.4
0.6
0.8
1
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
Normal i zed Ti me, t /2
N
o
r
m
a
l
i
z
e
d

D
i
o
d
e

C
u
r
r
e
n
t
X
m
= 0.4; THD = 10%
X
m
= 2.0; THD = 45.5% X
m
= 10; THD = 120.8%

Figure (2.33). Normalized diode current response to an applied sinusoidal voltage whose normalized amplitude
is X
m
= V
m
/nV
T
. The current scale is normalized to the maximum achievable diode current, I
dmax
,
defined in (2-122).
2.5.0. DIODE APPLICATIONS
PN junction diodes enjoy widespread utility in both integrated and discrete component
electronic systems. In this section, we give a few examples of these applications. Other illustra-
tions of diode utility, particularly as it concerns thermal compensation of biasing networks, ap-
pear in subsequent chapters. No attempt is made to document diode applications exhaustively,
nor is any interest shown in a definitive mathematical analysis of the considered examples. Ra-
ther, the intent of this section is to demonstrate how meaningful first order mathematical ana-
lyses of practical diode applications are undertaken as a prelude to understanding the salient fea-
tures operating dynamics for the applications considered herewith.
2.5.1. LOGARITHMIC AMPLIFIER
A logarithmic amplifier, which is often called a compression amplifier, delivers an out-
put response that is proportional to the natural logarithm of the applied input signal. As such, it

- 150 -

compresses an applied voltage by transforming its amplitude from a Cartesian scale -to- a
logarithmic one. The logarithmic amplifier is commonly used in instrumentation, recording, and
in certain types of communication systems for which the input signals have a broad range of
amplitudes, and thus, a wide dynamic range. An ability to process these high dynamic range sig-
nals in a nominally linear fashion therefore requires their compression prior to their ability to
drive subsequent networks or media that offer only limited dynamic range.
A simple example of a logarithmic network appears in Figure (2.34). In this diagram, a
diode is connected between the inverting input and single ended output port of an operational
amplifier (op-amp). The applied input voltage, V
s
, whose intrinsic Thvenin resistance is ab-
sorbed into the indicated circuit resistance, R, is also incident with the inverting input node of the
op-amp. We assume that the average value of V
s
is a positive voltage. This presumption may
require a biasing source implicit to the applied input voltage so that the net effective value of Vs
is precluded from dropping below zero volts. Since the output voltage, V
o
, swings negative for
positive V
s
, the diode is forward biased. Accordingly, diode current I
d
is non-negative and re-
lates to diode voltage V
d
in concert with (2-3). But since the forward biased diode acts as a low
resistance feedback element around the op-amp, voltage v, at the op-amp input port is driven to
near zero if the op-amp offers large open loop gain. If the op-amp is additionally characterized
by a very large input resistance, the input current, i, flowing into the inverting node of the op-
amp is nearly zero. It follows that the diode and source circuit currents, I
d
and I
s
, respectively,
are almost identical. We therefore witness
+
+
+
v
R
I
d
i
I
s
V
d
+
V
s
Op-Amp V
o

Figure (2.34). Basic schematic diagram of a logarithmic (compression)
amplifier. Biasing for the operational amplifier, which
functions as a linear network, is not shown.
d
o d T
o
I
V V nV ,
I
ln
| |
~ ~
|
\ .
(2-124)
while
s
s d
V
I I .
R
~ ~ (2-125)
The substitution of (2-125) into (2-124) leads immediately to the desired result; namely,
s
o T
o
V
V nV .
RI
ln
| |
~
|
\ .
(2-126)
The signal compression forged by the amplifier at hand is significant. For example, as-
sume in (2-126) that R = 1 KO and I
o
= 50 fA at room temperature. For V
s
= 5 mV, (2-126)
yields V
o
= 18.42 nV
T
, which is about 479 mV at room temperature. On the other hand, if V
s

= 500 mV, which corresponds to an input signal dynamic range of 40 dB, V
o
in (2-126) is 23.03

- 151 -

nV
T
, or almost 600 mV at room temperature. The resultant ratio of output voltages corresponding
to the rather striking 5 mV -to- 500 mV of input signal swing is only about 1.25, or less than 2
dB! But before pontificating the virtues of the compression amplifier, we must take note of the
fact that (2-126) relies on an ideal op-amp, which is available only in academe and is progres-
sively more difficult to emulate as the signal frequencies of the applied input signal rise. Moreo-
ver, (2-126) suggests potentially significant temperature sensitivity issues primarily because of
the dependence of the output voltage on Boltzmann voltage V
T
.
2.5.2. EXPANDER CIRCUIT
The expander circuit diagrammed in Figure (2.35) performs the inverse of the signal
processing function executed by the compression network of Figure (2.34). As such, it is often
used in conjunction with the compression circuit, in that it restores a logarithmically compressed
response to its original dynamic range. Analogous to the compression amplifier, an op-amp
boasting very large open loop voltage gain and very large input impedance is required in the ex-
pander. This op-amp clamps the indicated input current, i, to zero and in concert with the feed-
back resistance, R, the input port voltage, v, holds fast to very near zero. As a result, the voltage,
V
s
, of the signal source, which we presume has negligibly small Thvenin resistance, is dropped
entirely across the diode. Moreover, the current, I, equates to the diode current, I
d
, and the out-
put response, V
o
, is simply the negative of the resistive drop, RI. In view of these observations,
+
+
+
v
R
I
d
i
I
V
d
+
V
s
Op-Amp V
o

Figure (2.35). Basic schematic diagram of an expander amplifier. Bias-
ing for the operational amplifier is not shown.
s T
V nV
o d o
V IR I R I R , e = = ~ (2-127)
which confirms an output voltage proportional to an exponentiation of the applied signal voltage.
2.5.3. POWER SUPPLY
As we have already discussed, electronic systems designed to process applied input sig-
nals as linearly as possible require that their embedded semiconductor elements be biased at judi-
ciously selected quiescent operating points. The establishment of these operating points relies on
external power supplies that are designed to generate static voltages and currents that support
these Q-points. In portable electronics, such supplies may be as simple as one or more batteries.
In contrast, non-portable electronics derive their biasing supply voltages from a properly condi-
tioned, sinusoidal, or alternating, line voltage. Regardless of the specific nature of these sup-
plies, a regulator is often incorporated to desensitize the device Q-points with respect to supply
voltage variations (which may be unavoidable battery voltage degradation), variations in the cur-
rents conducted by the electrical loads imposed on the supplies, and fluctuations in on-chip
temperature. For non-portable, commercial electronic systems, the power supplies must trans-

- 152 -

form the alternating or AC voltage available at a traditional power outlet to the static energy
required for biasing. Since diodes are capable of transforming alternating energy having zero
average, or zero DC, value to unidirectional energy featuring nonzero DC level (discussed pre-
viously as the rectification ability of diodes), it is not surprising that power supplies for non-
portable electronics are among the more common of PN junction diode applications.
Figure (2.36) abstracts the salient features of a power supply that converts alternating
power to static power. The voltage, v
s
(t), whose internal resistance is R
s
, can be taken as the
sinusoid,
+
AC/DC
Converter
(Rectifier)
Voltage
Regulator
v (t)
s
R
s
R
L
Lowpass
Filter
V
DC
I
DC

Figure (2.36). System level abstraction of a power supply appropriate for non-portable, commercial
electronic systems. Resistance R
L
is not a physical element. It is used in the diagram
merely to convey the fact that the power supply provides a static output voltage of
V
DC
at a static output current of I
DC
, which is given by the ratio, V
DC
/I
DC
.
( ) ( )
s p p
v (t) V t V 2f t , sin sin = = (2-128)
where in the United States, the root mean square (RMS) line voltage is commonly 110 volts,
which makes V
p
= 2 (110) = 155.6 volts. Also in the USA, the radial frequency of this input
energy is = 2t(60 Hz) = 377.0 radians -per- second. In many cases, v
s
(t) is the output voltage
of a transformer that is utilized to step down the 110 volt RMS voltage to an amplitude that is
amenable to the application at hand.
The AC/DC converter, or rectifier, can be as simple as a single diode circuit or as
complicated as either a two-diode circuit utilizing a center-tapped transformer or a four-diode
bridge network. The purpose of the lowpass filter, which commonly is a large capacitance
placed in shunt with the load imposed on the supply, is to null, as best as possible, the amplitudes
at the fundamental frequency, as well as the harmonic components of the output response gener-
ated by the rectifier. A well-designed filter enables the voltage observed at the output port of the
lowpass filter to be virtually constant, divorced of fundamental or harmonic frequency compo-
nents. The voltage regulator, which is not addressed in this chapter, may or may not be present
in a particular embodiment of a power supply. This regulator ideally renders the ultimately
achieved static, or DC, output voltage, V
DC
, independent of the static load current, I
DC
, drawn
by the load that the power supply drives. One way of effecting this voltage invariance with load
current entails establishing a near zero Thvenin resistance seen by the effective load. In this
design approach, the load voltage, V
DC
, reduces to the Thvenin output voltage of the regulator.
Since a Thvenin voltage is an open circuit metric, it is, of course, independent of the current
drawn from the Thvenin source by the load. A regulator can also be deployed to stabilize vol-
tage V
DC
against variations in the input peak voltage, V
p
, changes in system operating tempera-
ture, and even electrical noise that couples to critical nodes of the supply system. Finally, the
load, R
L
, can be taken as purely resistive. Despite its circuit level depiction in Figure (2.36) as an

- 153 -

actual two terminal resistor, this load is rarely a physical branch element. Instead, it is more
properly viewed as a mathematical load that represents the ratio of DC output voltage to DC out-
put current; that is, R
L
=V
DC
/I
DC
. While the load at the output port of the power supply com-
monly shares system ground, the input voltage, v
s
(t), need not be grounded.
2.5.3.1. Half Wave Rectifier
As we have stated in the preceding section, the rectifier in Figure (2.36) converts the in-
put sinusoid, v
s
(t), which has zero average value, to a unidirectional waveform having nonzero
average value. The simplest form of AC/DC converter is the half wave rectifier, which utilizes a
single PN junction diode, as we portray in Figure (2.37a). The diode in this circuit behaves
effectively as a switch that is closed, or conductive, for sufficiently positive v
s
(t) and is open cir-
cuited, or non-conductive, whenever v
s
(t) is smaller than the turn on voltage, V
on
, of the diode.
As a result, the effective load, which is delineated as resistance R
Leff
in the subject diagram, wit-
nesses only a positive voltage, v
o
(t), for all time. The diode is seen as eating nominally one-
half of the input signal, and in particular, it removes the one-half of the input waveform per pe-
riod for which v
s
(t) < V
on
. Such annihilation allows the load to witness only a half sinusoid per
period. Figure (2.38) displays this half wave rectified sinusoid.
+
(a).
I
d
I
d
+
+
V
o
n
r
do
R
s
R
Leff
v (t)
s
v (t)
o
V
d
V
d
+
(b).
I = 0
d
R
s
R
Leff
v (t)
s
v (t)
o
+
(c).
R
s
R
Leff
v (t)
s
v (t)
o

Figure (2.37). (a). Schematic diagram of a half wave rectifier. (b). Approximate equivalent circuit of the half
wave rectifier for the case of v
s
(t) < V
on
. (c). Approximate equivalent circuit of the rectifier for
v
s
(t) > V
on
.
For v
s
(t) < V
on
, no diode current flows and the pertinent circuit model becomes the
structure in Figure (2.37b). Obviously, this model delivers an output voltage, v
o
(t), of zero. Note
in the subject model that the diode voltage, V
d
, is identical to the source voltage, v
s
(t). Since the
most negative value of voltage v
s
(t) is V
p
, this observation affirms that the utilized diode must
be capable of withstanding a reverse bias voltage of at least V
p
. Common engineering practice in
the design and implementation of a half wave rectifier is to use a diode whose Zener breakdown
rating is at least twice the peak source voltage. This tack protects the diode from any transients it
may experience during the rectification process.
If a silicon diode is used in the rectifier, a reasonable estimate of V
on
is 700 mV. Other-
wise, V
on
can be approximated in accordance with the analyses and discourse surrounding the
diode model postulated in Figure (2.5). In particular, the maximum diode current, I
dm
, in light of
(2-128), can be estimated as

- 154 -

p
dm
s Leff
V
I ,
R R
~
+
(2-129)
whence by (2-3), the corresponding maximum diode voltage, V
dm
, is
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
Normal i zed Ti me, t/
V
o
l
t
a
g
e

(
v
o
l
t
s
)
v
s
(t)
v
o
(t)

Figure (2.38). Input and output voltage waveforms for the half wave rectifier in Figure (2.37). The peak ampli-
tude, V
p
, of the input voltage is taken as 50 volts, the diode turn on voltage, V
on
, is 700 mV, and
the voltage attenuation factor, k
e
, is taken to be 0.75.
( )
p
dm
dm T T
o
o s Leff
V
I
V nV nV .
I
I R R
ln ln
(
| |
( ~ =
|
+ (
\ .

(2-130)
It follows from (2-8) that
( )
p
on dm T T
o s Leff
V
V V nV nV 1 .
I R R
ln
(

(
~ =
`
(
+

)
(2-131)
With v
s
(t) V
on
, the diode is conductive, and a plausible diode model is the architecture
postulated in Figure (2.5b). However, since the diode is turned off for approximately 50% of the
time, a more meaningful diode model derives from an expansion of the diode volt-ampere
characteristic about the turn on voltage, as opposed to expanding said curve at the maximum cur-
rent point, which is the scenario reflected by Figure (2.5b). Accordingly, V
dm
in the subject
model is supplanted by voltage V
on
, which renders current I
dm
(current corresponding to voltage
V
dm
) in the subject model zero. Moreover, the diode resistance, say r
do
, is now the inverse of the
slope of the diode characteristic curve at V
d
= V
on
. By (2-5) and (2-131),
( )
on T
T T
do s Leff
V nV
p
o
nV nV
r R R .
V
I e
= = + (2-132)

- 155 -

The resultant circuit model of the rectifier for v
s
(t) V
on
, which is offered in Figure (2.37c), pre-
dicts
| |
o e s on
v (t) k v (t) V , = (2-133)
where
Leff
e
Leff do s
R
k
R r R
=
+ +
(2-134)
is the pertinent voltage attenuation factor. In summary,
| | ( )
s on
o
e s on e p on s on
0, for v (t) V
v (t) .
k v (t) V k V sin t V , for v (t) V
<
=
( = >

(2-135)
This dual relationship, along with the input waveform, comprise the plots delineated in Figure
(2.38).
It is worth interjecting, at risk of offending a cadre of analytical purists, that the fore-
going disclosures concerning V
on
and r
do
are likely to comprise insignificant engineering side-
bars. In particular, most applications feature V
p
>> V
on
, as well as nV
T
<< V
p
, which collectively
imply that the turn on voltage, V
on
, as well as its corresponding diode turn on resistance, r
do
, can
likely be ignored. In light of these approximations, the average value, V
DC
, of the output voltage
plotted in Figure (2.37) is
( ) ( ) ( )

e p
DC o e p
0 0
k V
1 1
V v (t)d t k V sin t d t ,
2 2
~ =
} }
(2-136)
whose numerical value is about 32% of the amplitude of the observed output response. The
background applause detected here recognizes that the rectifier at hand has succeeded in convert-
ing an input voltage waveform having no average value to a unidirectional response that features
a nonzero average value. Every performance attribute has a price. In this case, the price paid for
this conversion is that converted static output voltage that is smaller than one-third of the ampli-
tude of the applied input sinusoid.
2.5.3.2. Full Wave Rectification
+
Nv (t)
s
v (t)
line
R
line
R
Leff
+
+
v (t)
s
+
v (t)
s
I
d1
I
d2
+
+
v (t)
o
V
d1
V
d2
D1
D2

Figure (2.39). Schematic diagram of a full wave rectifier that utilizes a center tapped transformer.
An obvious shortfall of the half wave rectifier is that one-half of the input voltage
waveform is effectively thrown away in the process of achieving the desired AC -to- DC conver-

- 156 -

sion. The full wave rectifier, an example of which is presented in Figure (2.39), circumvents this
shortfall by coalescing together two half wave rectifiers. For a given line voltage input, v
line
(t),
the center-tapped transformer produces a voltage, v
s
(t), which is a linear function of v
line
(t),
across each secondary winding. The root mean square value of the secondary voltage produced
for a given line voltage is determined by the so called turns ratio, N of the transformer
[5]
. In
particular, N > 1, which corresponds to a step down transformer, establishes v
s
(t) < v
line
(t), while
the step up version associated with N < 1 delivers v
s
(t) > v
line
(t).
Our inspection of the circuit in Figure (2.39) suggests that when v
line
(t) is positive
enough so that v
s
(t) > V
on
, diode D1 conducts current, but diode D2 is reverse biased. Because
diode D2 is reverse biased, the current conducted by D1 necessarily flows through the effective
load resistance, R
Leff
. On the other hand, negative v
line
(t) turns off diode D1 and supports current
conduction in diode D2. Once again, the diode current is forced to ground through the load
resistance. In effect, the section of the circuit connected to the upper part of the center-tapped
secondary processes positive v
s
(t), while its counterpart on the bottom section of the circuit
exclusively handles negative v
s
(t).
The voltage response, v
o
(t), of the circuit topology at hand is the full wave rectified
sinusoid displayed in Figure (2.40). Because the full wave sinusoid encloses twice the area per
period than does its half wave counterpart, the average value of voltage delivered to the load is
twice that predicted by (2-136). Specifically,
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
Normal i zed Ti me, t/
V
o
l
t
a
g
e

(
v
o
l
t
s
)
v
s
(t)
v
o
(t)

Figure (2.40). Center tapped input and output voltage waveforms for the full wave rectifier in Figure (2.38).
The peak amplitude, V
p
, of the input voltage is taken as 50 volts, the diode turn on voltage, V
on
,
is 700 mV, and the voltage attenuation factor, k
e
, is taken to be 0.75.
2
e p
DC o o
0 0
2k V
1 2
V v (t)d(t) v (t)d(t) .
2 2
= =
} }
(2-137)

- 157 -

In the interest of comparative consistency, the Thvenin resistance, R
line
, of the line voltage and
the transformer turns ratio, N, are presumed to deliver an effective Thvenin resistance asso-
ciated with v
s
(t) on each secondary winding that is identical to the resistance, R
s
, adopted in the
half wave rectifier. As Figures (2.38) and (2.40) suggest, (2-37) confirms that the full wave rec-
tifier delivers twice the DC output value of the half wave rectifier.
Several prices are paid for the increased conversion efficiency afforded by full wave
rectification. First, a center-tapped transformer, which is bulky, heavy, somewhat expensive, and
not very pretty is required. Second, the two diodes in the circuit must be electrically matched to
ensure that the circuit dynamics implicit to the upper part of the transformer secondary are iden-
tical to those of the bottom part topology. Finally, the matched diodes must be capable of
withstanding twice the peak voltage generated at each secondary port with respect to ground. To
wit, with diode D1 conducting, which implies diode D2 is turned off, the voltage, V
d2
, forged
across diode D2 is [2v
s
(t) + V
on
], where V
on
is the nominal forward biasing voltage of D1.
Recalling (2-128), the maximum value of v
s
(t) is V
P
, and assuming that 2V
P
>> V
on
, V
d2
is seen
to rise toward nearly 2V
p
.
+
Nv (t)
s
v (t)
line
R
line
R
Leff
+ +
v (t)
s
I
d
1
I
d
2
I
d
3
I d
4
+

v (t)
o
V
d
1
V
d
2
V
d
3
V
d
4
D
1
D
2
D
3
D
4

Figure (2.41). Schematic diagram of a full wave bridge rectifier that does not require a center tapped
transformer.
An alternative full wave rectifier that does not require the use of a center-tapped
transformer is the bridge topology offered in Figure (2.41). With v
s
(t) sufficiently positive, only
diodes D1 and D2 conduct. In particular, the current generated by the signal source at the
transformer secondary flows through diode D1, thence to ground through the effective load resis-
tance, followed by a flow from ground and through diode D2, and finally, it is returned to the
transformer secondary. On the other hand, negative v
s
(t) negative forces only diodes D3 and D4
to conduct. In this circumstance, the current supplied by the transformer secondary winding
flows through diode D4, to ground through R
Leff
, from ground and through diode D3, and ulti-
mately back to the transformer secondary.
In addition to boasting the advantage of not requiring a center-tapped transformer, the
maximum voltage that any diode must be capable of withstanding in reverse bias in the bridge
topology can be demonstrated to be only V
p
. In effect, the breakdown of twice voltage ampli-
tude that is common to conventional full wave rectifiers is shared in the bridge circuit by two
matched diodes. Of course, all four diodes must be matched. An issue of potential concern,
especially if the voltage, v
s
(t), which is earmarked for rectification, is characterized by small
peak amplitude, is that the effective turn on voltage for either pair of diodes is 2V
on
since two
diodes are embedded in the signal path driven by the transformer secondary.

- 158 -

2.5.3.3. Filter
Although the rectifiers introduced in the preceding subsection succeed in transforming
an alternating time domain voltage into a unidirectional response, they do not deliver the con-
stant, or static, output voltages that are required of a high performance electronic network. In-
deed, the rectifiers produce only a unidirectional, and therefore harmonically rich, version of the
line sinusoid. Since the frequency domain content of a purely constant voltage is comprised of
only a zero frequency component, it can be argued that the fundamental purpose of the filter in a
power supply is to kill the harmonic components, as well as the fundamental frequency compo-
nent, of the waveform produced by the rectifier. It follows that the filter must be a lowpass
topology exuding a time constant that is significantly larger than the inverse of the fundamental
frequency (usually 60 Hz) of the line voltage.
+
(a).
I
d
I
d
+
+
V
o
n
r
do
R
s
R
Leff
v (t)
s
v (t)
o
v (t)
o
v (t)
o
V
d
V
d
+
(c).
I = 0
d
R
s
v (t)
s
+
(b).
R
s
R
Leff
R
Leff
v (t)
s
C
L
C
L
C
L
+

Figure (2.42). (a). Schematic diagram of a half wave rectifier with capacitive lowpass filter. (b). Equivalent
circuit of the half wave rectifier for the case of v
s
(t) V
on
. In this time interval, the filter
capacitor, C
L
, charges to a maximum voltage of V
omax
= k
e
V
p
. (c). Equivalent circuit of the rec-
tifier for v
s
(t) V
on
. In this interval of time, the filter capacitor discharges through effective
load resistance R
Leff
from its maximum voltage of V
omax
to a designable minimum voltage, V
omin
.
The simplest and most commonly used power supply filter is little more than a capacit-
ance, say C
L
, placed in shunt with the effective load resistance. This filter is illustrated schemati-
cally in Figure (2.42a) in conjunction with the unfiltered half wave rectifier of Figure (2.37a).
The effectiveness of the appended load capacitance can be argued in terms of the ability of a
sufficiently large C
L
to short circuit to ground the fundamental and all higher frequency harmon-
ics of the voltage waveform to which it is exposed. Alternatively, its short circuiting of voltages
that change over time attests to its ability of sustaining the voltage to which it is charged by the

- 159 -

applied signal. In Figure (2.42a), resistance R
Leff
is the ratio of the DC voltage, V
DC
, which is
presumably the voltage to which C
L
charges (with the polarity indicated in the subject figure), to
the DC current, I
DC
, supplied to the output port. In the absence of a regulator, R
Leff
is identical to
the resistance, R
L
, in the system level diagram of Figure (2.36). With the regulator present, R
Leff
is the input resistance of said regulator.
Recall that when v
s
(t) V
on
, the diode in the rectifier conducts to deliver its current to
the load. This current generates a nonzero output voltage, v
o
(t), which charges the shunting
capacitance, C
L
. From (2-135), the maximum output voltage in the steady state, and thus the
maximum voltage, say V
omax
, to which capacitance C
L
can charge is
( )
omax e p on
V k V V , = (2-138)
where V
p
is recalled as the voltage amplitude of the applied sinusoid, V
on
is the turn on voltage of
the diode, and k
e
is the circuit attenuation factor defined by (2-134). Although a nonzero time
delay between v
s
(t) and its response, v
o
(t), is unavoidable when the diode conducts, a small
Thvenin source resistance, R
s
, and a very small diode resistance, r
do
, minimizes this delay. At
low frequencies, this delay is given by the circuit time constant,
( )
on Leff do s L
R r R C . ( = +

(2-139)
To the extent that time constant
on
in (2-139) is indeed small, the capacitor charges periodically
in the steady state to its peak value, V
omax
, at nearly the same times at which v
s
(t) attains its maxi-
mum value. We should mention, however, that if time constant
on
is a large number, the delay
incurred between input line signal and output voltage response increases the time required to
achieve steady state operation. In such an event, the ultimate achievement of steady state condi-
tions may require that the subject circuit process several cycles of the input line voltage. This
long wakeup time does not necessarily comprise a bad operating scene, for it effectively serves
to soften the impact of any transients that might result from a sudden buildup of load voltage.
This softening is important because modern, high performance and especially wideband
electronic systems are vulnerable to voltage overstress problems precipitated by abruptly applied
power supply voltages.
As time progresses beyond the instant at which v
o
(t) attains its maximum value, v
s
(t)
decreases because of its sinusoidal signature. But the load capacitor, which is unable to change
its terminal voltage instantaneously, temporarily holds its maximum voltage value of V
omax
.
Accordingly, v
o
(t) is now greater than v
s
(t) in Figure (2.42a), which means that the diode is
forced to cease conduction. Figure (2.42c) becomes the applicable equivalent circuit. In light of
the fact that capacitance C
L
is charged to voltage V
omax
at the instant at which the diode cuts off,
this model yields
Leff L
t R C
o omax
v (t) V ; e
= (2-140)
that is, capacitance C
L
discharges through the effective load resistance, R
Leff
. The result at hand
remains valid as long as the diode does not conduct. But slightly less than one period of the in-
put waveform later and specifically, at a time T
p
subsequent to the realization of maximal output
voltage, v
s
(t) cycles through zero and ultimately matches the voltage value of the continuously
decaying v
o
(t). If time t = 0 is defined to correspond to the peak value of v
s
(t), which is tanta-
mount to a shift of /2 radians in the argument, t, of the input sinusoid, time T
p
is such that
( )
p Leff L
T R C
omax p omax omin
V T V V , cos e
= (2-141)
where V
omin
is, as depicted in Figure (2.43), the minimum value to which the voltage across the
shunt load capacitance converges when the diode turns off. At t = T
p
, the diode once again be-

- 160 -

gins to conduct, and the output voltage follows its unfiltered form until the maximum level of
V
omax
is embraced again. At the time when v
o
(t) rises to V
omax
, the entire process described above
is repeated.
Time
V
o
l
t
a
g
e
V
omax
V
omin
Line
Voltage
Filtered
Output
Unfiltered
Output
t = 0 t = T
p
t

Figure (2.43). Projected steady state response of the filtered half wave rectifier given in Figure (2.42a). The
filtered output plotted herewith is the output voltage, v
o
(t), in Figure (2.42a).
When compared to the unfiltered response shown in Figure (2.38), Figure (2.43) shows
that the load capacitor vastly improves the overall character of the output voltage response of the
power supply. But while the use of a load capacitor appears to be prudent engineering, the re-
sponse remains imperfect in that the observed output voltage is not the strict constant that is
ideally associated with a static power supply. The problem, of course, is the capacitive discharge
through the effective load resistance. Since this effective load is the ratio of static output voltage
to static output current, the foregoing imperfections are exacerbated when the power supply of
interest is called upon to supply relatively large load currents at small output voltages.
The ripple factor, r, quantifies the extent to which an actual power supply deviates from
the idealized norm of a system capable of supplying a strictly constant voltage to an arbitrary
load. It is generally expressed as a percentage metric. The ripple factor is defined in terms of
the ripple voltage, V
r
, which is
r omax omin DC omin
V V V V V , ~ (2-142)
where V
omax
is equated to V
DC
because a negligible amount of capacitive discharge (ideally zero
discharge) establishes V
omax
as the constant, steady state output voltage. The ripple factor com-
pares the foregoing ripple voltage to the maximum output voltage in accordance with
p Leff L
T R C
omin r
omax omax
V V
r 1 1 ,
V V
e
= = (2-143)

- 161 -

where (2-141) is invoked. Since a fundamental objective in the design of the power supply is a
minimization of the amount of capacitive discharge, T
p
<< R
Leff
C
L
is a reasonable design target,
whence
p Leff L
T R C p
r
omax Leff L
T
V
r 1 .
V R C
e
= ~ (2-144)
An analytical disclosure of the time, T
p
, required in the preceding relationship can be
marshaled through an iterative solution of (2-41). Rather than enduring this grief, we note via an
inspection of Figure (2.42) that T
p
is necessarily only slightly smaller, by a specific amount of At,
than the period, 2/ = 1/f, of the unfiltered output response. Time parameter T
p
approaches pe-
riod T = 1/f if the capacitance discharges only slightly. It follows that
p Leff L
T R C p
r
omax Leff L Leff L
T
V 1
r 1 ,
V R C f R C
e
= ~ ~ (2-145)
where f symbolizes the frequency (in hertz) of the unfiltered response. We should understand
that in the case of half wave rectification, the frequency, f, of the unfiltered response is identical
to the frequency of the applied line voltage. But in a full wave rectifier, which effectively func-
tions as dual half wave rectifiers, frequency f in (2-145) is twice the frequency of the line vol-
tage. As might have been anticipated, (2-145) confirms that larger shunt load capacitances en-
gender progressively smaller power supply ripple factor. In addition, the foregoing frequency
comment implies that the ripple factor of a full wave rectified power supply is one-half that of a
half wave system, assuming the time constant, R
Leff
C
L
, is the same in both considered units. Note
that for the desirable circumstance of a ripple factor satisfying r << 1, (2-145) asserts that (1/fC
L

<< R
leff
.
The foregoing observations infer that the key to successful power supply design is
simply a big enough shunt output capacitance. But before jumping on the capacitance bandwa-
gon, we need to be aware that large power supply capacitances, which generally approach hun-
dreds, if not thousands, of microfarads, are bulky, relatively expensive, and, especially in the
case of polarized electrolytic capacitors, generally unreliable in the long term. Moreover, the
fact that the load capacitance acts as a short circuit at the instants of time when the diode in the
circuit switches to its conductive state suggests the possibility of dangerously large diode cur-
rents.
We can investigate potential diode current issues by beginning with the observation that
for At t 0 in Figure (2.42), the filtered output response, v
o
(t), is
( ) ( )
o omax
v t V t , cos = (2-146)
while at t = At,
( )
( )
2
o omin omax omax
t
v ( t) V V t V 1 .
2
cos
(
(
= ~
(

(2-147)
The indicated approximation exploits the presumption of a sufficiently small time increment, At.
Thus, the ripple voltage, V
r
, in (2-142) becomes
( )
2
r omax omin omax
t
V V V V .
2
(
( ~
(

(2-148)
This expression and (2-143) combine to deliver

- 162 -

t 2r , ~ (2-149)
which confirms the expected fact that time interval At diminishes with progressively decreasing
ripple factor. A sidebar to the last conclusion is that the solution to time T
p
in (2-141) can now
be deduced in that T
p
, as delineated in Figure (2.42), is clearly T At, where T = 1/f is the period
of the unfiltered response. We can easily demonstrate that this observation synergizes with (2-
149) to deliver
p
2 2r 1 r
T 1 .
f 2
| |
~ ~ |
|
\ .
(2-150)
We note that in this approximate result that parameter T
p
approaches 1/f, the period of the unfil-
tered response for small ripple factor.
Returning to the circuit in Figure (2.42a), the current, I
d,
flowing through the diode
necessarily satisfies the Kirchhoff constraint,
o o
d L
Leff
v (t) dv (t)
I C .
R dt
= + (2-151)
At time t = At, when the diode returns from its off state to initiate current conduction, v
o
(t) =
V
omin
= (1 r)V
omax
, where (2-143) is exploited. On the other hand, (2-146) shows that
( )
o
omax
dv (t)
V t ,
dt
sin = (2-152)
whence at t = At,
( ) ( )
o
L L omax L omax
t t
dv (t)
C C V t C V t .
dt
sin sin
=
= = (2-153)
For small At, sin(eAt) ~ eAt and thus,
( ) ( )
o
L L omax L omax L omax
t t
dv (t)
C C V t C V t C V 2r ,
dt
sin
=
= ~ = (2-154)
where (2-149) is used. It follows that the diode current at time t = At is
omax
d L omax
t t
Leff
V
I C V 2r ,
R
=
= + (2-155)
Factoring out V
omax
/R
Leff
and recognizing that this voltage to resistance ratio is the desired static
current, I
DC
, supplied to the effective load, (2-155) becomes
( )
d DC Leff L
t t
I I 1 r R C 2r .
=
= + (2-156)
Appealing to (2-145) and noting that ripple factor r is invariably far smaller than unity in a high
performance power supply, the last result collapses to
2
d DC DC dpeak
t t
8 2
I I 1 2I I ,
r r
=
| |
|
~ + ~ =
|
\ .
(2-157)
where the symbol, I
dpeak
, signifies peak diode current. This revealing and even disturbing disclo-
sure contends that the diode current can peak to levels that lie appreciably above its steady state
static value of I
DC
if the power supply under consideration is designed for very small ripple. For
example, the peak diode current is theoretically almost 64-times larger than the DC output cur-
rent if a 2% ripple factor is implemented! Fortunately, this current extreme, which occurs
periodically with a period equal to that of the unfiltered, rectified response, is sustained for only

- 163 -

the small time increment, At. In particular, at a time, At, after the diode begins to conduct and
peak diode current is realized, the output voltage rises to its maximum level and the diode is
necessarily turned off. A short duty cycle notwithstanding, the peak diode current must be
weighed carefully in the selection of diodes suitable for use in a filtered supply.
One way of mitigating the effects of harsh diode current transients entails the use of an
inductance placed in series with the diode. The inductance proves effective because of its inher-
ent inability to support instantaneous changes in currents that it conducts. You will doubtlessly
be delighted to know that you can explore the pragmatics of a series inductor in Problem #2.29.
EXAMPLE #2.6:
Design a full wave rectified power supply that delivers a static voltage of 9 volts
to a load that draws 25 mA of current. Use a capacitive filter to achieve a load
voltage ripple factor of at most 2.5%. Assume that the frequency of the applied
line voltage is 60 Hz and that its root mean square amplitude is 110 volts. Ex-
amine the time domain performance of the power supply with SPICE simulation
software. To this end, the model parameters of the silicon PN junction diode
suitable for this design initiative are itemized in Table (2.1).
SPICE
SYMBOL
TEXT
SYMBOL
DESCRIPTION
OF PARAMETER
VALUE UNITS
IS I
o
Saturation Current 45 fA
RS Net Ohmic Resistance 0.2 O
N n Injection Coefficient 1.03
CJO C
jo
Zero Bias Depletion Capacitance 353.6 fF
VJ V
j
Junction Built-In Potential 800 mV
M m
j
Grading Coefficient 0.5
TT t
d
Average Carrier Transit Time 10 nSEC
Table (2.1). SPICE model parameters for the diodes used in the full wave rectifier studied in Example #2.6.
SOLUTION #2.6:
(1). The effective load resistance imposed on the desired power supply is the ratio of the static
output voltage to the corresponding output current. In particular,
DC
Leff
DC
V 9
R 360 .
I 0.025
= = = (E6-1)
(2). Equation (2-145) defines the ripple factor, r, for a half wave rectifier. If frequency f in this
relationship is replaced by (2f), the expression at hand can be applied to a full wave rectifier.
Thus, the shunt load capacitance, C
L
, must satisfy
L
Leff
1 1
C 925.9 F .
(2f )r R (120)(0.025)(360)
= > = (E6-2)
It is entirely appropriate to round up this computed capacitance value to 930 F or to what-
ever value is available commercially at a reasonable price. For the purpose of this problem,
take C
L
= 930 F.
(3). A center-tapped transformer is required. The peak voltages at either secondary tap must be
sufficiently large to embrace the desired 9 volt static output, the turn on voltage of each di-

- 164 -

ode, the resistance, say R
s
, associated with each center-tapped output port, and the ostensibly
small losses precipitated by the net series ohmic resistances of the diodes. Assuming a 720
mV turn on voltage and R
s
= 5 O (which increases by about 0.125 volt for a steady state cur-
rent delivery of 25 mA, the requisite peak center tap voltage is slightly greater than 9.8 volts.
Because of the uncertainty in the effective resistance of each diode, 10.5 volts is chosen for
this design. Recalling Figure (2.38), the turns ratio, N, to each center-tapped transformer port
follows as
110 2
N 14.82 .
10.5
= =
(E6-3)
Although SPICE models of practical center-tapped transformers are commonly available, it is
not the intent of this chapter to study the dynamic properties and electrical nuances of
transformers. Hence, the circuit designed herewith and overviewed schematically in Figure
(2.44) simply represents the center-tapped output port voltages of the transformer by two
independent sinusoids possessed of a 10.5 volt amplitude and 60 Hz frequency.
+
10.5 sin(377t)
360
I
d1
I
d2
+
+
v (t)
o
V
d1
V
d2
D1
D2
10.5 sin(377t)
930
+
5
5

Figure (2.44). Schematic diagram of the power supply designed in Example #2.5.
Signal amplitudes are in volts, the signal frequencies are 60 Hz or
equivalently, 377 radians per second, the resistances are in units of
ohms, and the capacitor is in units of microfarads.
(4). With I
DC
= 25 mA and r ~ 0.025 in (2-157), the estimated peak diode current computes as
2
dpeak DC DC
8
I I 1 57.2I 1.43 amps .
| |
|
~ + = =
|
\ .
(E6-4)
While it is arguably sensible to ensure that the utilized diodes can safely withstand this
significant peak current stress, it should be noted that in practice, the inductances associated
with the windings of the transformer embedded in the power supply mitigate this current
peak, possibly by as much as a factor of two or more. Moreover, the energy storage parasit-
ics (junction capacitance and carrier transit time) tend to soften the transient diode current in-
curred at those instants of times when the diode enters its conduction state.
The simulated voltage response of the power supply considered herewith is offered in Figure
(2.45). The simulated curves in the figure not only depict the desired filtered voltage re-
sponse, but the unfiltered, or full wave rectified output. Observe that the filtered output does
not track particularly well with the first few periods of the applied signal waveform and that
indeed, several periods are required before steady state operation is realized. This deviation
from the response results projected in Figure (2.42) reflects the delay phenomenon noted ear-
lier. They are precipitated by a large time constant associated with the load capacitance dur-
ing diode conduction times. Because of this delay, observe further that the load capacitance

- 165 -

does not discharge at the peak of the unfiltered response but instead, it begins its periodic dis-
charge at roughly a diode turn on voltage below the aforementioned peak amplitude. A care-
ful examination of the numerical simulation data reveals that the maximum steady state out-
put voltage is 9.012 volts, and the minimum output value is 8.818 volts. Hence, the simulated
ripple factor is 2.15%, which is slightly better than the design target of 2.5%. The slight
improvement in ripple performance can be attributed to rounding up of the computed capacit-
ance value.
Time (mSEC)
V
o
l
t
a
g
e

(
v
o
l
t
s
)
0
2
4
6
8
10
0 10 20 30 40 50 60 70 80

Figure (2.45). Simulated output voltage response, v
o
(t), of the power supply circuit shown in Figure
(2.43). The solid curve corresponds to the actual filtered response, while the dashed curve,
which mirrors full wave rectification of a sinusoid, is the response with the load capacit-
ance, C
L
, removed.
0
0.3
0.6
0.9
1.2
1.5
0 10 20 30 40 50 60 70 80 90 100
D
i
o
d
e

C
u
r
r
e
n
t

(
a
m
p
s
)
Time (mSEC)
Diode D1
Current, I
d1
Diode D2
Current, I
d2

Figure (2.46). Simulated diode current responses of the power supply circuit shown in Figure (2.44).
The SPICE model parameters for the utilized diodes are tabulated in Table (2.1).

- 166 -

The simulated diode current responses appear in Figure (2.46). The largest peak diode cur-
rent is realized at startup, which is reasonable in view of the fact that the capacitor is initially
uncharged. The peak current is 1.26 amperes, which is only about 12% smaller than the peak
current value projected in (E6-4).
2.5.4. DIODE CIRCUITS FOR LOW LEVEL SIGNAL PROCESSING
PN junction diodes used in the half wave and full wave rectifiers addressed in the
preceding subsection are utilitarian as long as the amplitude of the periodic voltage signal ear-
marked for rectification is larger than the threshold potentials of the utilized diodes. In the case
of silicon diodes, these threshold potentials are of the order of 700 mV. Unfortunately, this
requirement comprises a serious drawback in instrumentation systems, biomedical monitoring
and sensing circuits, and other precision networks that operate on signals featuring amplitudes in
the range of tens of microvolts to a few millivolts. The relatively large threshold potential of
diodes is also a significant shortfall in electronic networks that exploit adaptive biasing to
minimize power dissipation. In the latter application, the biasing of radio frequency (RF) subcir-
cuits is adjusted in proportion to the amplitude of the input signal detected for signal processing.
Thus, small standby power prevails in these adaptive units when the input signals are very small,
while appropriately larger quiescent power is dissipated to enable nominally linear signal
processing of comparably large input signals. But the effectiveness of such an adaptive
configuration rests squarely on the ability to detect input signals whose amplitudes are far below
diode threshold potentials.
2.5.4.1. Precision Half Wave Rectifier
Figure (2.47) depicts the basic schematic diagram of a precision half wave rectifier
formed of a PN junction diode and an operational amplifier. For simplicity, the requisite biasing
for the op-amp is not shown but nonetheless, it is presumed that it functions linearly when nega-
tive feedback is applied. If diode D conducts a forward current, a low resistance feedback path is
forged from the output port of the op-amp to its inverting input port. Consequently and presum-
ing unconditional stability in the feedback system, the voltage, v, observed differentially across
the input terminals of the op-amp is driven to nearly zero. Specifically, it is driven to v
oa
(t)/A
o
,
where v
oa
(t) is the indicated output voltage of the op-amp, while A
o
represents the open loop vol-
tage gain of the op-amp. Now, the input voltage, v
i
(t), at the non-inverting op-amp input ter-
minal is essentially the applied signal v
s
(t), if the subject op-amp is characterized by large input
resistance. We therefore arrive at
+
+
Op-Amp
v (t)
s
v (t)
i
v (t)
oa
v (t)
o
R
s
R
l
+
v
D

Figure (2.47). Simplified schematic diagram of a precision half wave rectifier. Biasing
for the op-amp is not shown, but it is assumed that the op-amp operates
linearly when appropriate feedback is implemented around it.

- 167 -

oa
s i o
o
v (t)
v (t) v (t) v (t) .
A
~ = + (2-158)
But if diode D is conducting current, which implies that its terminal voltage is in the immediate
neighborhood of the turn on potential, V
on
,
o oa on
v (t) v (t) V , ~ (2-159)
and in light of (2-158),
oa
s oa on
o
v (t)
v (t) v (t) V .
A
~ (2-160)
This expression suggests that in order for voltage v
oa
(t) to exceed V
on
, it is necessary that the ap-
plied signal voltage, v
s
(t), be larger than only v
oa
(t)/A
o
. Since v
oa
(t) must rise to at least V
on
in
order that diode D conduct, the last observation puts forth a diminished turn on voltage for the
overall network of V
on
/A
o
. This effective threshold voltage is very small in that op-amps rou-
tinely boast open loop voltage gains of 80 dB or more To wit, V
on
= 700 mV and A
o
= 80 dB =
10,000 volts/volt yield an impressively low effective turn on voltage of only 70 V!
While the diode remains conductive, the output voltage response to an input signal
larger than V
on
/A
o
satisfies
oa on o
o i s
o o
v (t) V v (t)
v (t) v (t) v (t) ,
A A
+
= + ~ (2-161)
or
o on
o s
o o
A V
v (t) v (t) .
A 1 A 1
| |
~
|
+ +
\ .
(2-162)
As long as v
s
(t) > V
on
/A
o
, the output response essentially follows the input signal with an offset
of V
on
/(A
o
+1). When v
s
(t) falls below V
on
/A
o
, diode D ceases conduction, which starves the
load resistance, R
l
in Figure (2.47), of current. Neglecting leakage currents in both diode and the
op-amp, the output response drops to zero. This fact and (2-161) combine to couch the circuit at
hand as an impressive precision half wave rectifier. In particular, we can boast that the consi-
dered network is a half wave rectifier that functions basically as expected of all PN junction dio-
des whenever the input signal voltage exceeds the invariably very small effective threshold vol-
tage of V
on
/A
o
.
Unfortunately, the rectifier at hand is vulnerable to turn off transients similar to those
illustrated in Figure (2.18c). These transients, which are somewhat mitigated by diodes boasting
small junction depletion capacitances, limit the input signal frequencies that can be processed
faithfully. Further mitigation of undue diode turn off transients is afforded by signal sources that
have small internal impedances.
2.5.4.2. Precision Limiter
A slight modification of the rectifier in Figure (2.47) produces the precision limiter de-
picted in Figure (2.48). As in the rectifier of Figure (2.47), the op-amp is presumed to have a
large open loop gain, A
o
, and is further presumed to operate in its linear regime when diode D is
conductive. Accordingly, voltage v in the schematic diagram is v
oa
(t)/A
o
when negative feedback
forged by nonzero diode current prevails. If the applied signal voltage, v
s
(t), is smaller than the
static reference potential, V
R
, applied at the non-inverting input terminal of the op-amp, the op-
amp output voltage, v
oa
(t) rises to facilitate current conduction in diode D. In this event, the out-
put voltage is

- 168 -

+
+
Op-Amp
v (t)
s
v (t)
oa
v (t)
o
R
s
R
l
v
D
+

V
R

Figure (2.48). Simplified schematic diagram of a precision limiter. Biasing for the
op-amp is not shown, but it is assumed that the op-amp operates li-
nearly when appropriate feedback is applied around it.
oa
o R
o
v (t)
v (t) V ,
A
= + (2-163)
and since for a diode turn on voltage of V
on
,
oa on o
v (t) V v (t) , ~ + (2-164)
(2-163) generates
o on
o R
o o
A V
v (t) V .
A 1 A 1
| |
~
|
+ +
\ .
(2-165)
For a large open loop voltage gain, A
o
, (2-165) shows that the diode threshold potential negligi-
bly influences the output response, v
o
(t), which is essentially clamped to the reference potential,
V
R
. Thus, v
o
(t) is limited to, and held at, reference voltage V
R
, regardless of the amount by which
the input signal, v
s
(t), is below V
R
.
When v
s
(t) is greater than or equal to V
R
, the op-amp output port voltage, v
oa
(t), is dri-
ven negative, and the diode consequently shuts off. If the op-amp is characterized by large input
resistance at either of its input ports, a series circuit is thereby established among v
s
(t), signal
source resistance R
s
, and the load resistance, R
l
. It follows that
l
o s
l s
R
v (t) v (t) ,
R R
| |
=
|
+
\ .
(2-166)
and the output response is seen to track linearly with the input signal. In summary,
o on
R R s R
o o
o
l
s s R
l s
A V
V V for v (t) V
A 1 A 1
v (t) .
R
v (t) for v (t) V
R R
| |
~ <
|
+ +
\ .
~
| |
>
|
+
\ .
(2-167)
A potentially serious problem with the limiter in Figure (2.48) is manifested when di-
ode D turns off, as it does for v
s
(t) V
R
. In this case, no feedback is applied around the op-amp,
with the result that said op-amp invariably saturates; that is, v
oa
(t) locks to a supply voltage used
to bias the op-amp. This situation imposes a severe limitation to the processing speed attainable
by the circuit since a significant level of stored charge within the op-amp must be removed to
enable a return of the op-amp to its linear region when v
s
(t) < V
R
. In a word, the op-amp is
incapable of responding rapidly to input signals whose amplitudes change suddenly from a level
above V
R
to a level below V
R
. Moreover, the magnitude of the differential voltage across the in-

- 169 -

put terminals of a saturated op-amp can become very large, thereby risking breakdown of the
amplifier unit. The problem at hand can be mitigated, but only through use of appropriately con-
nected transistors, which is subject matter meant to entice in subsequent chapters.
2.5.4.3. Precision Full Wave Rectifier
The precision full wave rectifier in Figure (2.48) requires two operational amplifiers
and two PN junction diodes. The two diodes must be matched and while the two op-amps need
not be identical, both must have large open loop voltage gains and large input impedances. As
we demonstrate by the forthcoming simplified analysis, the output response, v
o
(t), is
o s
t
R
v (t) v (t) .
R
~ (2-168)
where resistance R
t
includes the Thvenin resistance of the source voltage. Thus, if the signal,
v
s
(t), applied to the indicated network is a sinusoid, the output response is a full wave rectified
sinusoid with the added icing on the proverbial cake of a designable voltage scaling factor in the
amount of (R/R
t
). By adjusting resistance R
t
, the gain can be controlled, which means that when
a filter capacitor is connected across the load resistance, the static output voltage can be adjusted
electronically.
+
+
Op-Amp
1
v (t)
s
v (t)
oa
v (t)
o
R
t
R
l
v
1
D1
D2
+
R R R
R
v
2
+
Op-Amp
2

Figure (2.49). Basic schematic diagram of a precision full wave rectifier. Biasing for the op-amps is not
shown, but it is assumed that these op-amps operate linearly when negative feedback is
applied around them. While the diodes are presumed to be identical, the op-amps need only
present very large open gains and very large input impedances.
The full wave rectifier in Figure (2.49) is obviously more topologically complex than is
its half wave counterpart in Figure (2.47). It is hardly earth shattering to declare that enhanced
topological complexity breeds correspondingly increased analytical challenges. At the risk of
preaching, recall that the purpose of circuit analysis is not necessarily the generation of precise
network solutions. Rather, its fundamental purpose is to inspire the engineering insights that
beget design creativity. Accordingly, meaningful approximate analyses of complex networks
comprise prudent undertakings in that they generally highlight at least the dominant attributes
and shortfalls of achievable I/O characteristics, albeit to only first order. An effective intellectual
response to the purist who suffers heartburn with this schema is that a network proven
dysfunctional for approximate, and generally idealized, model and architectural circumstances
can hardly be expected to satisfy design goals under real world conditions. In other words,
outstanding performance achieved under somewhat idealized conditions is a necessary condition

- 170 -

for acceptable performance in an actual engineering environment. Besides, let us not forget that
a manual analysis of an electronic circuit is merely a prelude to far more definitive computer-
aided circuit analysis.
EXAMPLE #2.7:
As an illustration of the efficacy of an approximate analysis of a reasonably
complex circuit topology, study the circuit in Figure (2.49), subject to the idea-
lized circumstances of (1) infinitely large open loop gain in both op-amps and
(2) infinitely large input impedances at both input ports of each op-amp. In
particular, deduce approximate results for the output voltage, v
o
(t), for both posi-
tive and negative values of the input signal, v
s
(t). Confirm the propriety of the
analyses through appropriate SPICE simulations of the network in question.
SOLUTION #2.7:
+
+
Op-Amp
1
v (t)
s
v (t)
oa
v (t)
o
R
t
R
l
v =0
1
0
0
0
D1
+
R R R
R
+
0
0
0
0
v
(
t
)
/
R
s
t
v (t)/R
s t
v (t)/R
o v
(
t
)
/
R
o
v (t)
o
(a).
+
+
v (t)
s
v (t)
oa
v (t)
o
R
t
R
l
0 0
D2
+
R R R
R
+
0
0
0
v
(
t
)
/
R
s
t
v
(
t
)
/
R

v
/
R
s
t
x

+
[
v
(
t
)
v
]
/
R
o
x

(b).
v
x
v
x v /R
x
[
v
(
t
)
v
]
/
R
o
x

[v (t) v ]/R
o x
Op-Amp
2
Op-Amp
2
Op-Amp
1
v =0
2
v =0
1
v =0
2

Figure (2.50). (a). Equivalent circuit of the rectifier in Figure (2.49) for the case of v
s
(t) < 0, which turns on
diode D1 and turns off diode D2. (b). Equivalent circuit of the rectifier in Figure (2.49) for
the case of v
s
(t) > 0, which turns off diode D1 and turns on diode D2.
(1). Since the input voltage, v
s
(t), is applied through a resistance, R
t
, to the inverting input ter-
minal of the first op-amp, voltage v
oa
(t) at the output port of op-amp 1 is driven to a negative

- 171 -

potential. This output voltage swing turns on diode D1, while turning off diode D2. Conse-
quently, the pertinent equivalent circuit is the structure appearing in Figure (2.50a), in which
all known node voltages and branch currents are explicitly delineated. These electrical va-
riables are deduced as follows.
(a). With diode D1 conductive, negative feedback is established around op-amp 1. In light of
the infinitely large open loop gain assumption, the voltage, v
1
, across the input terminals
of this op-amp is essentially zero. Negative feedback via resistance R is always applied
around op-amp 2, which therefore affords v
2
= 0.
(b). The infinite input impedance assumption applied to both op-amps assures zero current
flow into the inverting and non-inverting input terminals of each of the op-amps.
(c). Since the non-inverting input port of the first op-amp is grounded and its differential in-
put voltage is zero, the voltage with respect to ground at the inverting node of op-amp 1
lies at zero. Accordingly, the current supplied to this node by the signal source is v
s
(t)/R
t
.
(d). Since no current is conducted by the resistance, R, which is incident with the non-invert-
ing input port of op-amp 2, the current, v
s
(t)/R
t
, conducted by resistance R
t
flows through
the resistance, R, which is incident with the inverting input terminal of the op-amp 1 and
the p-side of diode D1.
(e). The inverting input terminal of op-amp 1 is a virtual ground, no current flows through the
resistance, R, which is connected between said op-amp terminal and the non-inverting in-
put terminal of op-amp 2, and zero volts prevails across the input terminals of op-amp 2.
It follows that the inverting input terminal of op-amp 2 is a virtual ground, thereby
establishing a current, v
o
(t)/R, which flows in the indicated direction through the feedback
resistance, R, appended to the second op-amp. Moreover, this same current is forced to
flow through the resistance, R, which intertwines the inverting input terminal of op-amp 2
with the p-side of diode D1.
(f). The last current discussed above and the virtual ground at the inverting input node of op-
amp 2 forces a voltage of v
o
(t) from the p-side of diode D1 to ground. By KVL, it fol-
lows that v
o
(t) = R[v
s
(t)/R
t
], whence for v
s
(t) > 0,
o s
t
R
v (t) v (t) .
R
| |
=
|
\ .
(E7-1)
(2). With v
s
(t) < 0, voltage v
oa
(t) in Figure (2.49) rises, thereby effecting cutoff of diode D1 and
conduction of diode D2. The applicable equivalent circuit, with critical branch currents and
node voltages highlighted, is the structure offered in Figure (2.50b).
(a). With diode D1 turned off, negative feedback is nonetheless maintained around op-amp 1
because of the upper resistances R and the lower resistance R. Voltage v
1
across the input
terminals of this op-amp is zero, as is voltage v
2
of the second op-amp. Of course, the in-
put ports of neither op-amp conduct any current.
(b). Since the inverting input port of op-amp 1 remains virtually grounded, the current sup-
plied to this node by the signal source is v
s
(t)/R
t
.
(c). Temporarily assign a voltage, v
x
, at the inverting node of op-amp 2. Because zero
differential voltage prevails across the input ports of this second op-amp, the same vol-
tage is manifested at the n-side of diode D2.
(d). The last contention, coupled with the virtual ground at the inverting input port of op-amp
1, gives rise to a current, v
x
/R, flowing through resistance R and toward the aforemen-
tioned port. By KCL, a current of [v
s
(t)/R
t
+ v
x
/R] necessarily flows through the resis-
tance, R, which is incident with the inverting input terminal of op-amp 1.
(e). In view of the temporarily assigned potential, v
x
, the current conducted by the feedback
resistance imposed around op-amp 2 is [v
o
(t) v
x
]/R, as shown. Since the input ports of

- 172 -

op-amp 2 conduct no current, this same current flows from right to left through the resis-
tance, R, which appears topologically to the left of the node at which voltage v
x
is estab-
lished with respect to ground. An inspection of the branch containing the series
interconnection of the two resistances of value R indicates that [v
s
(t)/R
t
+ v
x
/R] = [v
o
(t)
v
x
]/R, which readily produces
o s
t
R
v (t) v (t) .
R
| |
=
|
\ .
(E7-2)
(3). Obviously, (E7-2) and (E7-1) combine to validate (2-168).
(4). In order to test the propriety of the foregoing disclosures, the precision rectifier of Figure
(2.49) is simulated on SPICE software with ideal operational amplifiers having open loop
gains of 10,000 volts/volt. The diodes have SPICE model parameters of IS = 2 fA, RS = 0.20
O, N = 1.02, CJO = 0.5 fF, VJ = 800 mV, M = 0.5, and TT = 1.0 fSEC. The symbolic
nomenclature of these model parameters is defined in Table (2.1). For the purpose of this
exercise, R
t
is taken to be 50 O, R = 100 O (implying an I/O voltage gain magnitude of about
2), and R
l
= 500 O. In addition, 100 KO resistances are appended between ground and each
op-amp input port to allow consideration of large, but finite op-amp input resistances.
(a). The first simulation is a static sweep of input signal v
s
(t) to determine the describing
function that relates output voltage v
o
(t) to v
s
(t). The simulated results are displayed in
Figure (2.51) over an input voltage range of 2 volts v
s
(t) +2 volts. The projected
dependence of the output voltage on the absolute value of the source signal is clearly
confirmed, as is the I/O voltage gain magnitude of R/R
t
= 2 volts/volt. We observe that
the I/O characteristics of the circuit at hand deliver a scaled, absolute value of the applied
input signal, v
s
(t).
-2
0
2
4
6
-2 -1 0 1 2
Voltage (volts)
V
o
l
t
a
g
e

(
v
o
l
t
s
)
Output
Voltage, v (t)
o
Input
Voltage, v (t)
s

Figure (2.51). Output voltage response, v
o
(t), of the precision rectifier in Figure (2.49) for a static sweep
of the applied input voltage, v
s
(t).
(b). The second simulation is the transient time domain response of the rectifier output vol-
tage to an applied 250 MHz sinusoid having an amplitude of only 5 mV. The pertinent re-
sults appear in Figure (2.52). Fundamentally, a full wave rectified sine wave appears to

- 173 -

be generated, although diode turn off transients manifest observable effects after the first
full cycle of the input waveform. In concert with the diode turn off compensation strat-
egy documented earlier, these effects can be mitigated In part by appending small
capacitances (about 100 fF) across the two resistances, R, which are incident with the
inverting input terminal of op-amp 1.
-8
-4
0
4
8
12
0 3 6 9 12 15
Time (nSEC)
V
o
l
t
a
g
e

(
v
o
l
t
s
)
Output
Voltage, v (t)
s
Input
Voltage, v (t)
s

Figure (2.52). Output voltage response, v
o
(t), of the precision rectifier in Figure (2.49) for a 250 MHz, 5
mV, input sinusoid.
The approximate analysis of the subject circuit tracks well with relevant SPICE simulations.
As a result, the analysis serves to confirm the validity of pertinent theoretic disclosures.
More importantly, the analysis provides us a sturdy foundation upon which we can base prac-
tical design modifications and refinements. For example, the capacitance compensation
noted above tracks with fundamental theory and indeed improves the observed response (re-
fer to Problem #2.33). Additional computer-based investigations can be conducted in ad-
vance of the actual realization of the required amplifiers in MOSFET or bipolar device
technologies. For example, the effects on transient time domain responses of nonzero output
resistances, nonzero output capacitances, and nonzero input port capacitances in both amplifi-
ers can be assessed straightforwardly. The fruits of these assessments can facilitate the
choice of geometries for the active devices deployed in the final form design, and they can
prove useful for the selection of suitable device biasing levels.
2.6.0. REFERENCES
[1]. R. T. Howe and C. G. Sodini, Microelectronics: An Integrated Approach. Upper Saddle River,
New Jersey: Prentice Hall, 1997, pp. 88-106.
[2]. A. B. Phillips, Transistor Engineering and Introduction to Integrated Semiconductor Circuits.
New York: McGraw-Hill Book Company, Inc., 1962, pp. 133-139.

- 174 -

[3]. K. K. Clarke and D. T. Hess, Communication Circuits: Analysis and Design. Reading,
Massachusetts: Addison-Wesley Publishing Company, 1978, pp. 107-113 and pp. 636-641.
[4]. M. Abramowitz and I. A. Stegun, Handbook of Mathematical Functions. Washington, D. C.:
National Bureau of Standards, Applied Mathematical Series No. 55, 1964, Section 9.6.
[5]. A. M. Davis, Linear Circuit Analysis. Boston, Massachusetts: PWS Publishing Company,
1998, chap. 16.

EXERCI SES
PROBLEM #2.1
Assume a constant current conducted by a forward biased PN junction diode. Show that at room
temperature, the diode voltage commensurate with constant diode current must decrease by almost
60 mV for each one order of magnitude increase in the diode saturation current, I
o
.
PROBLEM #2.2
The two diodes in the circuit of Figure (P2.2) are identical. Current I
k
is a constant current sink. If
the volt-ampere characteristics of each diode are approximated by
d T
V nV
d o
I I , e ~
derive expressions for the individual diode currents, I
d1
and I
d2
, as a function of current I
k
and the
difference voltage, (V
1
V
2
) A V. Argue the validity of these expressions for the cases of V strongly
positive and then voltage V strongly negative.
V
2
D1 D2

V
1

I
d1
I
d2
I
k

Figure (P2.2)
PROBLEM #2.3
Repeat Problem #2.2 for the case in which the junction area of diode D2 is k-times larger than that
of diode D1.
PROBLEM #2.4
In the circuit of Figure (P2.4), diode D2 has twice the junction injection area of diode D1. When
each diode conducts measurable current, each displays the same, nominally constant forward operat-
ing voltage of V
on
, which is to say that the series resistance associated with each diode is negligibly
small.
R
3
R
2
D1 D2
+V
cc
R
1

Figure (P2.4)
(a). What condition must be satisfied by the power supply voltage, V
cc
, if the two PN junction dio-
des are to conduct measurable forward current?
(b). If the condition in (a) is satisfied, give expressions, in terms of circuit parameters, for the cur-
rents, I
d1
and I
d2
, conducted by diodes D1 and D2 respectively?

- 175 -

(c). If both diodes are either silicon or germanium units, is it possible for only one of the two dio-
des to conduct forward current?
(d). If one diode is a silicon semiconductor and the other is a germanium unit, is it possible for
only one of the two diodes to be conductive? If indeed possible, which diode (the silicon or
the germanium device) is actually conductive?
PROBLEM #2.5
The circuit in Figure (P2.5) is used to square a 10 KHz sinusoid (V
s
) whose peak amplitude is 50
volts. The diodes in the circuit have forward resistances of 10 O, infinitely large reverse resistances,
and turn on voltages that are small in comparison to the applied input signal. The battery voltages,
V
r1
and V
r2
are such that |V
r2
| > |V
r1
|, but V
r2
and V
r1
are allowed to be of opposite polarities. The
output voltage (V
o
) waveform is to be flat for 90% of the time. Design the circuit by selecting V
r1
,
V
r2
, and a reasonable value for resistance R.
+
V
r1

V
r2

V
s
V
o
R

Figure (P2.5)
PROBLEM #2.6
In the circuit of Figure (P2.6), diode D2 has 3-times the junction injection area of diode D1. When
each diode conducts measurable current, each displays a nominally constant forward operating vol-
tage of V
on
.
V
dd

R
3
R
1
D1
D2
I
d1
I
d2
R
2

Figure (P2.6)
(a). What condition must be satisfied by the power supply voltage, V
dd
, if each of the two PN junc-
tion diodes are to conduct nonzero forward current? Express your result in terms of V
on
and
relevant circuit parameters.
(b). If the actual power supply used in the circuit provides a terminal voltage that is five-times the
minimum voltage deduced in Part (a), give expressions, in terms of V
on
and relevant circuit
parameters, for the diode currents, I
d1
and I
d2
.
PROBLEM #2.7
Each of the diodes in the circuit of Figure (P2.7) has a threshold voltage of V
on
and a forward small
signal terminal resistance (inverse slope of diode static I-V characteristic curve) that can be taken to
be zero. Assume that input voltage V
s
is a sinusoid whose amplitude, V
p
, exceeds V
on
. What is the
maximally positive value of the current, I
L
, conducted by the parallel diode configuration, and what

- 176 -

is the maximally negative value of current I
L
?
+
R
s
I
L
V
s D1
D2

Figure (P2.7)
PROBLEM #2.8
Repeat Example #2.1 for the case in which diode D is operated at a junction temperature of 75 C.
Assume that D has a temperature factor of P = 3.5. Compare the diode voltage result obtained here-
with with the diode voltage computed in the example and deduce the average temperature coeffi-
cient, AV
d
/AT, of the diode.
PROBLEM #2.9
In the circuit of Figure (P2.9), the indicated voltages, V
1
, and V
2
, are constrained to be equal by addi-
tional circuitry that is not shown in the diagram. Diodes D1 and D2 are identical, save for the fact
that their junction areas differ. All resistors have zero temperature coefficients.
D1 D2
R R
R
1
R
2
+V
dd
V
1
V
2
I
d1
I
d2

Figure (P2.9)
(a). What is the relationship between diode current I
d1
and diode current I
d2
?
(b). Derive an expression for diode current I
d1
in terms of the difference between the two diode
voltages.
(c). Which of the two diodes must have a larger junction injection area? Explain why.
(d). If the magnitude of the difference between the two diode voltages is to be nominally 500 mV,
by what factor must one diode junction injection area exceed the injection area of the other di-
ode?
PROBLEM #2.10
Derive equations (2-45) and (2-46).
PROBLEM #2.11
Integrate equation (2-26) from a stipulated position, say X
i
, to any arbitrary position, x. Let position
X
i
be selected as the position where the observed free hole and free electron concentrations lie at
their intrinsic concentration values. Use the fruits of the foregoing integration exercise to confirm
that under equilibrium conditions, p(x)n(x) = n
i
2
, where p(x), n(x), and n
i
respectively symbolize the

- 177 -

free hole concentration at x, the free electron concentration at x, and the intrinsic carrier concentra-
tion of the considered semiconductor.
PROBLEM #2.12
A silicon PN junction diode is doped such that the doping concentration, N
D
, on the n-side of the
junction is much larger than the dopant level, N
A
, on the p-side of the junction; that is, N
D
>> N
A
.
Show that for this typical fabrication scenario, the equilibrium field intensity at the junction can be
approximated as
j
o
2V
(0) ,
W
~ E
where V
j
is the equilibrium built-in potential of the junction and W
o
is the equilibrium width of the
depletion layer.
PROBLEM #2.13
When PN junction diodes are fabricated, the impurity profile resulting from the diffusion of dopants
into the semiconductor crystal can often be best approximated, at least in the immediate neighbor-
hood of the junction transition region, as a linear function of position. This state of affairs gives rise
to the symmetric charge profile, (x), projected by Figure (P2.13), where parameter m is a profile
grade factor having units of atoms/cm
4
. The figure at hand obviously implies
x
+W /2
o
W /2
o 0
(x)
(x) = qmx

Figure (P2.13)
o o
W W
qmx, x
(x) .
2 2
0, elsewhere
s s
=
where q is the magnitude of electron charge, and W
o
represents the equilibrium width of the deple-
tion layer. In addition to the stipulated charge profile, the electric field can be taken as zero outside
of the transition region.
(a). Show that the equilibrium electric field intensity, F(0), at the PN junction of the diode consi-
dered herewith is
2
o
s
qmW
(0) ,
8
= E
where c
s
is the dielectric constant of the semiconductor.
(b). Demonstrate that the equilibrium width, W
o
, of the junction depletion region is expressible as
1 3
s j
o
12 V
W ,
qm
| |
=
|
\ .

where V
j
is the equilibrium value of the junction built-in potential.
(c). Show that the zero bias value, C
jo
, of the capacitance associated with the depleted junction re-
gion is

- 178 -

1 3
2
s
jo
j
qm
C .
12V
| |
= |
|
\ .

(d). If the dopant concentration at x = W
o
/2 is N
o
, show that the equilibrium built-in potential, V
j
,
of the considered PN junction is given by
3
o
j
2
s
2qN
V .
3m
=
PROBLEM #2.14
Consider the network depicted in Figure (P2.14). In this system, the operational amplifiers are ideal
in the senses of delivering an infinitely large open loop voltage gain, infinitely large input imped-
ance, and zero output impedance. When diodes D1 and D2 conduct current, their volt-ampere
characteristics can be presumed to abide by the simplified low frequency volt-ampere relationships,
d1 T d2 T
V V V V
d1 s1 d2 s2
I I ; I I , e e ~ ~
where I
di
, the forward current conducted by diode Di, corresponds to V
di
, the forward voltage applied
across the terminals of diode Di. Assume that the two diodes are matched, thereby ensuring that I
s1

I
s2
I
s
. Note that the buffer embedded on the signal source side of the network is an ideal voltage
buffer, which is to say that it is characterized by infinitely large input impedance, zero output imped-
ance, and unity voltage gain.
+
+

+
Op-Amp
Op-Amp
D1
D2
Ideal
Voltage
Buffer
V
s
R
s
R
f
R
f
V
o
V
g

Figure (P2.14)
(a). In terms of signal voltage V
s
, diode parameters, and circuit parameters, determine the expres-
sion for the interstage voltage, V
g
.
(b). In terms of signal voltage V
s
, diode parameters, and circuit parameters, determine the expres-
sion for the output voltage, V
o
.
PROBLEM #2.15
The two silicon PN junction diodes in the circuit of Figure (P2.15) are not identical. The
current source is ideal and supplies a constant current in the indicated amount of I
k
. Assume
that the input voltage, V, and current I
k
are chosen to ensure that both diodes are forward bi-
ased at large enough voltages to enable the simplifying approximations,
+
D1 D2
I
k
V
I
d1
I
d2
+
V
d1
+
V
d2

Figure (P2.15)

- 179 -

( )
( )
d1 T d1 T
o1
d2 T d2 T
02
V nV V nV
d o1
V nV V nV
d o2
I I 1 I
.
I I 1 I
e e
e e
= ~
= ~

In terms of voltage V, current I
k
, and diode parameters, derive expressions for the two diode
currents, I
d1
and I
d2
.
PROBLEM #2.16
Recall that the steady state, static volt-ampere relationship of a PN junction diode is given by the
Boltzmann function,
( )
d T d T
V nV V nV
d s s
I I 1 I , e e = ~
where the approximation reflects the assumption of a diode operated under strong forward biased
conditions. In the indicated expression, I
d
is the forward biased diode current, V
d
is the forward bias
diode voltage corresponding to the current, I
d
, n is the junction injection coefficient (typically about
one), and V
T
= kT/q symbolizes the Boltzmann voltage. Because the diode saturation current, I
s
, is
functionally dependent on carrier mobility, intrinsic carrier concentration, and other physical
parameters, it is strongly dependent on the junction operating temperature, T. Although an analyti-
cal quantification of this temperature dependence is a challenging undertaking, one of numerously
deployed empirical relationships is
( ) ( ) ( )
( )
o
T T 10
s s o s
I T I T K ,
=
where I
s
(T) is the saturation current at an arbitrary absolute junction temperature, T, and I
s
(T
o
) is the
saturation current at a given reference temperature, T
o
, which is generally taken to be 27 C or
300.16 K. In addition, (T T
o
) is the change in junction operating temperature, and K
s
is a
dimensionless empirical constant whose value is typically in the range of 2 -to- 5. The subject
relationship effectively portrays I
s
as increasing by a factor of K
s
for each 10 C rise in junction
temperature. Observe that by virtue of the relationship between Kelvin and centigrade temperatures,
a temperature difference, (T T
o
), expressed in absolute degrees is equivalent numerically to
differential temperature cast in centigrade degrees. Obviously, the temperature-induced increased in
diode saturation current implies that for fixed voltage biasing, the diode current increases in propor-
tion to the change in I
s
. In turn, this situation means that in order to control the diode current in the
face of temperature increases, the diode voltage must be appropriately reduced.
(a). For a given diode under strong forward biasing, suppose that the diode current at absolute
temperature T, say I
d
(T), is to be rendered identical to the diode current at absolute temperature
T
o
, say I
d
(T
o
), where it is understood that AT = (T T
o
) > 0. Show that the requisite change in
forward diode voltage, AV
d
= [V
d
(T) V
d
(T
o
)], is expressible as
( )
( ) ( )
d o d
T 10
s o s
I T V nk
.
T q
I T K
ln
(
(
=
(

(b). Evaluate AV
d
/AT at I
d
(T
o
) = 5 mA for the case of I
s
(T
o
) = 5 fA, T
o
= 27 C, T = 75 C, n = 1,
and K
s
= 3.25. The temperatures in the preceding expression must be cast in absolute units.
PROBLEM #2.17
A silicon diode has a p-side dopant concentration of 10
16
atoms/cm
3
, and an n-side dopant
concentration of (8)(10
17
) atoms/cm
3
. For equilibrium and room temperature conditions, calculate
the built-in potential of the junction, the width of the junction transition layer, the maximum magni-
tude of the equilibrium electric field internal to the junction, and the zero bias value of the junction
capacitance density in units of fF/cm
2
. Assume the validity of the depletion approximation and take
the intrinsic carrier concentration at room temperature to be (1.5)(10
10
) atoms/cm
3
.

- 180 -

PROBLEM #2.18
A silicon PN junction diode operates at room temperature (27 C). It has a p-side dopant concentra-
tion of (6)(10
16
) atoms/cm
3
, an n-side dopant concentration of (8)(10
17
) atoms/cm
3
, a junction injec-
tion coefficient (n) of 1.02, a junction grading coefficient (m
j
) of 0.5, a junction cross section area of
100 m
2
, and an average free charge carrier lifetime (t
d
) of 75 pSEC. The saturation current of the
subject diode is I
o
= 15 fA. Develop a plot of the total capacitance, C
T
, as a function of the diode
current, say I
d
, flowing through the forward biased diode. On the same graph, plot separately the
diffusion and depletion components of this total capacitance. In arriving at the depletion
capacitance characteristic, do not assume that the turn on voltage, V
on
, is a constant. Instead, replace
values of V
on
that are calculated as a function of specifically considered diode currents.
(a). Compare, and comment on, the magnitudes of the diffusion and depletion capacitance compo-
nents.
(b). Develop an empirical relationship for the depletion capacitance across a forward biased junc-
tion as a function of the diode current supported by the junction.
PROBLEM #2.19
The design philosophy underlying the deployment of a speedup capacitance, as suggested in Figure
(2.19), to reduce the switching time of a resistance-diode network is commonly applied to linear net-
works. An electrical measurement system is a notable system modeled by these structures, where
the voltage v
i
(t), is to be measured, as accurately as possible, by a voltmeter whose parasitic input
impedance is comprised of the shunt interconnection of a resistance, R
i
, and a capacitance, C
i
. The
resistance, R
p
, in Figure (2.19a) represents the characteristic impedance of the measurement probe.
It is generally true that R
p
<< R
i
. The speedup capacitance, C
p
, in Figure (2.19b) is adjusted ma-
nually to a value that achieves an observable measured voltage, v
m
(t), that is independent of the fre-
quency spectrum embraced by the voltage, v
i
(t), sensed for ultimate measurement.
v (t)
m
v (t)
i
(a).
v (t)
m
v (t)
i
(b).

Figure (P2.19)
(a). Assuming that R
p
<< R
i
and that v
i
(t) is a sinusoid of radial frequency
i
, derive an expression
for the maximum tolerable value of parasitic instrumentation capacitance C
i
, in Figure (2.19a)
such that the measured amplitude of voltage v
m
(t) differs from the sensed amplitude of v
i
(t) by
less than 5%.
(b). Deduce a design-oriented relationship for capacitance C
p
in Figure (2.19b) such that the meas-
ured amplitude of voltage v
m
(t) is independent of the frequencies implicit to the sensed signal,
v
i
(t).
(c). Discuss any engineering shortcomings implicit to the capacitor relationship deduced in the
preceding part of this problem.
PROBLEM #2.20
The silicon diode in the circuit of Figure (2.20) has a PN junction injection area of 150 m
2
, an
approximately constant p-side dopant concentration of 10
17
atoms/cm
3
, an approximate n-side con-
stant dopant concentration of (9)(10
18
) atoms/cm
3
, and a free carrier lifetime (in the junction transi-

- 181 -

tion region) of 125 pSEC. For relevant computational purposes, assume room temperature operating
conditions and take the intrinsic carrier concentration at room temperature to be (1.5)(10
10
)
atoms/cm
3
. The circuit at hand uses V
F
= V
R
= 3 volts, while resistance R is 300 O
(a). With no speedup capacitor utilized (C = 0), calculate the diode turn off time and comment as
to the relative contributions of storage and depletion capacitance effects on this turn off time.
(b). Find an optimum value of speedup capacitance commensurate with the minimization of the
turn off transient. What is the corresponding estimate of the diode turn off time?
PROBLEM #2.21
In the circuit of Figure (P2.21), V
BB
= 5 volts, R
s
= 300 O, and the input signal, v
s
(t), is a 30 mV step
function. The silicon PN junction diode is biased to conduct 10 mA of current at room temperature.
At room temperature, this diode has a saturation current of 25 fA, unity junction injection coeffi-
cient, a built-in junction potential of 850 mV, a zero bias junction depletion capacitance of 25 fF, a
junction grading coefficient of 0.5, and an average carrier lifetime in its junction transition layer of
150 pSEC.

V
BB

R
l
v (t)
d
+
i (t)
d
v (t)
l
+
R
s
v (t)
s

Figure (P2.21)
(a). What value of the resistance, R
l
, is required to support the 10 mA current biasing of the PN
junction diode?
(b). Because the input signal is a step function with a small voltage amplitude, the diode can be re-
placed by a small signal model comprised of the shunt interconnection of a resistance and a
capacitance. Calculate the small signal resistance of the diode and the effective capacitance
that it shunts. In arriving at the depletion component of the net diode capacitance, assume that
the turn on voltage of the diode is one Boltzmann voltage level below the quiescent diode vol-
tage.
(c). Derive an expression for the small signal Laplace transform, say V
l
(s), of the indicated load
voltage, v
l
(t).
(d). Give an expression for the time domain response, v
l
(t), to the input step voltage, v
s
(t).
(e). What is the circuit time constant pervasive of the time domain response determined in the
preceding part of this problem?
PROBLEM #2.22
Reconsider the diode and circuit topology studied in Problem #2.21, but let the input signal, v
s
(t), be
the sinusoid, v
s
(t) = V
m
cos(t), where the amplitude, V
m
, of the subject sinusoid is small enough to
justify the use of a small signal model for the PN junction diode.
(a). Derive an expression for the transfer function, H(j) = V
l
(j)/V
s
(j).
(b). Above what radial frequency is the magnitude response determined in Part (a) nominally
independent of the radial frequency, , of the input sinusoid?
(c). The steady state load voltage phasor, V
l
(je), has a nonzero phase angle, say (). Derive an
expression for this phase response.
PROBLEM #2.23
In the circuit of Figure (P2.9), the two PN junction diodes are forward biased by the application of

- 182 -

the supply line voltage, V
dd
. In addition to this input static voltage, a small signal, v
s
(t), is inserted
directly in series with V
dd
. Derive general expressions for the low frequency, small signal compo-
nents of each of the indicated diode currents. Assume that the two diodes are identical, are biased
identically, and are characterized by a small signal resistance of r
d
at their quiescent operating
points.
PROBLEM #2.24
The volt-ampere characteristic of a certain nonlinear resistance is
k
k
V
I I ,
V
tanh
| |
=
|
\ .

where I
k
and V
k
are known constants, and, of course, V is the terminal voltage and I is the
corresponding current conducted by the subject element.
(a). Evaluate the small signal resistance, say r, at zero quiescent terminal voltage.
(b). Over what range of terminal voltage and corresponding element current does the small signal
resistance model deliver volt-ampere characteristics that differ from the actual characteristics
of the nonlinear element by no more than 10%?
PROBLEM #2.25
The nonlinear resistance in Figure (2.28) has = 0.05 siemens/volt, V
h
= 600 mV, and V
k
= 15 volts.
The voltage, V, applied across the nonlinearity is a superposition of a quiescent voltage that is 50%
larger than the voltage parameter, V
h
, and a sinusoid whose amplitude is V
m
and whose radial fre-
quency is ; specifically,
( )
h m
V 1.5V V t . cos = +
(a). Evaluate the quiescent current conducted by the nonlinear resistance.
(b). In terms of voltage amplitude V
m
, derive expressions for the amplitudes of the fundamental
frequency component, the second harmonic, and the third harmonic.
(c). Evaluate the percentage total harmonic distortion for V
m
= V
h
/2, V
m
= V
h
/3, V
m
= V
h
/4, V
m
=
V
h
/5, and V
m
= V
h
/10.
(d). What is the maximum signal amplitude commensurate with a total harmonic distortion that is
at most 10%?
PROBLEM #2.26
Assume that the volt-ampere characteristic of the nonlinear resistance addressed in Problem #2.24
can be represented adequately by the truncated power series,
3 5
k k k k k
I V V V 2 V
,
I V V V 15 V
tanh
| | | | | | | |
= ~ +
| | | |
\ . \ . \ . \ .

where the current parameter, I
k
, is 5 mA. The applied voltage, V, is the sinusoid,
( ) ( )
m k
V V t kV t , cos cos = =
with constant k representing a positive, less than unity constant.
(a). In terms of parameter k, derive expressions for the current amplitudes of the fundamental fre-
quency component, the third harmonic, and the fifth harmonic.
(b). Plot the percentage total harmonic distortion as a function of parameter k.
PROBLEM #2.27
In the compression amplifier of Figure (2.34), represent the operational amplifier by the model in
Figure (P2.27), which accounts for the effects of finite open loop gain (A
o
) and nonzero output resis-
tance (r
o
). Derive an expression for the resultant output voltage, V
o
, of the logarithmic amplifier,
and compare this result to the idealized disclosure postured by (2-127).

- 183 -

+
+
v
r
o
i
Op-Amp V
o
V
o
+
v
i

+
A v
o

Figure (P2.27)
PROBLEM #2.28
In the expander circuit of Figure (2.35), represent the operational amplifier by the model offered in
Figure (P2.27). Derive an expression for the resultant output voltage, V
o
, of the expander, and com-
pare this result to the idealized disclosure advanced by (2-127).
PROBLEM #2.29
An inductance, L, is inserted in series with the diode in the half wave rectifier of Figure (2.42a).
The resultantly filtered power supply adopts the schematic portrayal offered in Figure (P2.29).
+
I
d
+
R
s
R
Leff
v (t)
s
v (t)
o
v (t)
i
V
d
C
L
L

Figure (P2.29)
(a). Show that the transfer function, H(s) = V
o
(s)/V
i
(s), of the imposed filter is of the form
o
2
i
n n
V (s) 1
H(s) ,
V (s)
2 s s
1

= =
| |
+ +
|
\ .

where
n
represents the undamped natural frequency of oscillation of the filter, and is its
damping factor. Give expressions for
n
and in terms of the elemental branch parameters of
the filter.
(b). What circuit conditions give rise to a damping factor of = 1/ 2 ? What is the engineering
significance of this particular value of filter damping factor?
(c). The filtered power supply is to be capable of delivering 12 volts at 50 mA with less than 2%
ripple. Determine the requisite values of capacitance C
L
and inductance L, given that a damp-
ing factor of = 1/ 2 is to be achieved in the filter.
PROBLEM #2.30
The half wave rectifier with capacitive filter does not strictly produce a constant output voltage, but
rather, it generates exponentially decaying, periodic pulses, as depicted in Figure (2.43). Demon-
strate that within reasonable approximations, the average, or DC value, say V
DC
, of the generated
output response abides by the expression,
DC
DC omax
L
I
V V ,
4 f C
~
where I
DC
represents the average current delivered to the effective load resistance in the supply,
while V
omax
is the maximum value of output voltage. Discuss the significance of capacitance C
L
in
achieving a nominally constant static response.

- 184 -

PROBLEM #2.31
Repeat Example #2.6, but realize the quoted operating specifications through use of a half wave rec-
tifier. The diode model parameters for SPICE circuit simulation are itemized in Table (2.1). Simu-
late the circuit and discuss simulation results in light of the responses predicted by analyses underta-
ken in the text.
PROBLEM #2.32
Repeat Example #2.6, but realize the quoted operating specifications through use of a bridge full
wave rectifier. The diode model parameters for SPICE circuit simulation are itemized in Table
(2.1). Simulate the circuit and discuss simulation results in light of the responses predicted by ana-
lyses undertaken in the text.
PROBLEM #2.33
In the precision rectifier of Figure (2.47), assume for the purpose of this problem that the
operational amplifier behaves as an ideal voltage controlled voltage source of voltage gain
A
o
. The diode has a carrier lifetime of
d
and a zero bias depletion capacitance of C
jo
. Let
the input signal, v
s
(t), be the pulse waveform pictured in Figure (P2.33), were it is unders-
tood that the positive voltage level, V
F
, prevails for a very long time prior to its change to
V
R
at time t = 0. Derive an approximate relationship for and sketch the diode current re-
sponse for t > 0+.
v (t)
s
time (t)
V
F
V
R
0

Figure (P2.33)
PROBLEM #2.34
Use SPICE or comparable circuit simulation software to simulate the time domain response, v
o
(t), of
the precision rectifier in Figure (2.47). The SPICE model parameters of the diode are those deli-
neated in Table (P2.34).
SPICE
SYMBOL
TEXT
SYMBOL
DESCRIPTION
OF PARAMETER
VALUE UNITS
IS I
o
Saturation Current 4.5 fA
RS Net Ohmic Resistance 0.2 O
N n Injection Coefficient 1.03
CJO C
jo
Zero Bias Depletion Capacitance 3.5 fF
VJ V
j
Junction Built-In Potential 800 mV
M m
j
Grading Coefficient 0.5
TT t
d
Average Carrier Transit Time 10 pSEC
Table (P2.34)
Take the input source signal, v
s
(t), to be a sinusoid at a frequency of 2 MHz and an amplitude of 800
V. The Thvenin resistance, R
s
, of this signal source is 50 O. The operational amplifier behaves as
an ideal voltage controlled voltage source of voltage gain 10,000. Depending on the version of

- 185 -

SPICE used in the execution of this problem, it may be necessary to append resistances of at least
100 KO between circuit ground and each of the input terminals of the op-amp. Use SPICE to ex-
amine the sensitivity of response v
o
(t) to a zero bias depletion capacitance that is one-third as large
as the value indicated in the table. Repeat the simulation for a capacitance that is three times larger
than the tabulated value. While adjusting the simulation to account for different junction depletion
capacitance values, keep in mind that the principle vehicle for adjusting the junction depletion
capacitance is junction area to which the diode saturation current is directly proportional.
PROBLEM #2.35
An alternative topology to the precision half wave rectifier of Figure (2.47) is shown in Figure
(P2.35). The two PN junction diodes, D1 and D2, are identical and have a turn on voltage of V
on
.
The operational amplifier has infinitely large input impedance at both of its two input ports, and it
produces an open loop voltage gain of A
o
.
+
+
Op-Amp
v (t)
s
v (t)
i
v (t)
oa
v (t)
o
R
s
R
R
l
v
D1
D2
+

Figure (P2.35)
(a). When the signal voltage, v
s
(t), is sufficiently negative, which of the two PN junction diodes is
turned off and which is turned on?
(b). For suitably negative v
s
(t), derive an expression for the output voltage, v
o
(t). Simplify this
expression for the case of a very large open loop gain in the op-amp.
(c). For suitably positive v
s
(t), derive an expression for the output voltage, v
o
(t). Simplify this
expression for the case of a very large open loop gain in the op-amp.
(d). What is the effect of shunting the load resistance, R
l
, by a large capacitance, say C
l
?
PROBLEM #2.36
The precision full wave rectifier of Figure (2.49) is modified, as shown in Figure (P2.36), by the
addition of two capacitances, C. The purpose of these capacitances is to improve the transient re-
sponse by mitigating, at least in part, the turn off transients in the PN junction diodes. For the pur-
pose of this exercise, assume that the operational amplifiers behave as ideal voltage controlled
voltage sources whose open loop voltage gains are each 10,000 volts/volt. The SPICE parameters of
the two diodes are those exploited in Example #2.7, while the input voltage, v
s
(t), is a 250 MHz, 5
mV sinusoid. Use SPICE to explore the effectiveness of the introduced compensation capacitances
for capacitance values of C = 20 fF, 50 fF, 100 fF, and 250 fF. Submit a design recommendation
for the selection of capacitances C, and provide engineering rationale to support your conclusion.

- 186 -

+
+
Op-Amp
1
v (t)
s
v (t)
oa
v (t)
o
R
t
R
l
v
1
D1
D2
+
R R R
R
v
2
+
Op-Amp
2
C
C
Figure (P2.36)

Chapter 2 - Analog Integrated Circuit Design by John Choma

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