2-bit ripple binary counter using JK

flip flops (asynchronous counters)

K Q(t+1)
0
0
1
1
0
1
0
1
Q(t)
0
1
Q(t)
J
K





J
K





Q
1
Q
1




Q
0
Q
0




1
CP
CP
J
Q
0

Q
0
Q
1
0
0
1
0
0
1
1
1
0
0
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3-bit ripple binary counter using JK
flip flops (asynchronous counters)
J
K





J
K





Q
1
Q
1




Q
0
Q
0




1
CP
J
K





Q
2
Q
2




Q
0

Q
0
CP
Q
1
Q
2
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Simple Registers

No external gates.

Example: A 4!it register. A ne" 4!it #ata is loa#e#

on e$er% &lo&' &%&le.
A
4
A
3
A
2 A
1
I
4
I
3
I
2
I
1
CP

!
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4-bit register with parallel load
Load
Clear
CP
"
"
"
"
#
#
#
#
I
1
I
2
I
3
I
4
A
1
A
2
A
3
A
4
((ontrol Signal)
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Register "it) *arallel +oa# ,sing - .lip
.lops
!
!
!
!
Load
Clear
CP
I
1
I
2
I
3
I
4
A
1
A
2
A
3
A
4
$oa% A
1
& $oa% I
1
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'sing #egisters to i(ple(ent "e)uential
Circuits
/
A se01ential &ir&1it ma% &onsist o2 a register (memor%) an# a
&om!inational &ir&1it.
Nextstate $al1e

/
3)e external inp1ts an# present states o2 t)e register #etermine
t)e next states o2 t)e register an# t)e external o1tp1ts4 t)ro1g)
t)e &om!inational &ir&1it.
/
3)e &om!inational &ir&1it ma% !e implemente# !% an% o2 t)e
met)o#s &o$ere# in 5S6 &omponents an# *rogramma!le
+ogi& -e$i&es.
Combinational
Circuit
Register
Inputs
Outputs
Clock
Pulse
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,sing Registers to implement
Se01ential (ir&1its
/
*+a(ple 1: -esign a Se01ential (ir&1it ")ose state ta!le is gi$en !elo" 1sing t"o 2lip2lops.
A
1
+
7 8 m(449) 7 A
1
. x
:
A
;
+
7 8 m(14;4<49) 7 A
;
.x: + A
:
;
.x 7 A
;
x
% 7 8 m(=4>) 7 A
;
.x
Present
State
A
1
A
2
Input
Next
State
A
1
+
A
2
+
x
Output
y
"tate ,able
1 0 0 1 1 1
0 1 1 0 1 1
0 1 0 1 0 1
0 0 1 0 0 1
1 0 0 1 1 0
0 1 0 0 1 0
0 1 0 1 0 0
0 0 0 0 0 0
A
1
- +.
A
2
+
x
y
$ogic !iagra(
"e)uential Circuit I(ple(entation
A1
A2
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,sing Registers to implement Se01ential
(ir&1its
/
Example ;: Repeat example 14 !1t 1se a R?5 @Register.
A%%ress /utputs
1 2 3 1 2 3
A
1
A
2
+ A
1
A
2
y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 0 0 1
1 0 0 1 0 0
1 0 1 0 1 0
1 1 0 1 1 0
1 1 1 0 0 1
R?5 tr1t) ta!le
1 1
2 2
3 3
A
1
A
2
8 X 3
ROM

!
Sequential circuit using a register and a ROM
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Serial 6NASerial ?1t S)i2t Registers
"
Accepts #ata seriall! $ one bit at a time an# also
pro#uces output seriall!%
! !
!
!
C$K
"erial Input
("I)

3
"erial /utput
("/)
"hift #egister
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"erial In1"erial /ut "hift #egisters
/
Appli&ation: Serial trans2er o2 #ata 2rom one register to anot)er.
S)i2t register A S)i2t register B
S?
S? S6
S6
(*
(lo&'
S)i2t (ontrol
(lo&'
&or#time
1011 0010
3
1
3
;
3
=
3
4
(*
S)i2t (ontrol
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"erial In1"erial /ut "hift #egisters

Serialtrans2er example.
3iming *1lse
6nitial $al1e
A2ter 3
1
A2ter 3
2
A2ter 3
=
A2ter 3
4
S)i2t Register A
1
1
1
0
1
0
1
1
1
0
1
0
1
1
1
1
1
0
1
1
S)i2t Register B
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
Serial o1tp1t o2 B
0
1
0
0
1
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Q
-

Q
-

Q
-

Q
-

'1
()*
0 1 2 3
'1
()*
0 1 2 3
'1
()*
0 1 2 3
'1
()*
0 1 2 3
A
=
A
;
A
4
A
1
6
=
6
;
6
4
6
1
Serial
inp1t 2or
s)i2tle2t
Serial
inp1t 2or
s)i2trig)t
*arallel inp1ts
*arallel o1tp1ts
(lear
(+K
S
1
S
0
2i%irectional "hift #egisters

4-bit bi%irectional shift register 3ith parallel loa%

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Bi#ire&tional S)i2t Registers
/
4!it !i#ire&tional s)i2t register "it) parallel
loa#.
5o#e (ontrol
s
1
s
0
Register ?peration
0 0 No &)ange
0 1 S)i2t rig)t
1 0 S)i2t le2t
1 1 *arallel loa#
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An Application-"erial A%%ition
/
5ost operations in #igital &omp1ters are #one in parallel.
Serial operations are slo"er !1t re01ire less e01ipment.
/
A serial a##er is s)o"n !elo". A A+B.
S)i2t register A
S)i2t register B
S6
S6
.A
x
%
C
S
(
Q -
(lear
1010
0111
S?
S?
External inp1t
S)i2trig)t
(*
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S 7 x + % + Q
JQ 7 x%
KQ 7 x% 7(x+%)
*+citation table for a serial a%%er
Example: -esign a serial a##er 1sing a se01ential logi&
pro&e#1re
"it) JK 2lip2lops.
Next
State 6np1ts ?1tp1t
*resent
State
.lip2lop
inp1ts
Q x % S JQ KQ Q
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
0
1
D
D
D
D
D
D
D
D
1
0
0
0
Q(t) Q(t+1) J
0
0
1
1
0
1
0
1
0
1
D
D
D
D
1
0
K
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S)i2t register A
S)i2t register B
S S?7x
S?7%
External inp1t
S)i2trig)t
(*
J
K
Q
(lear
Second form of a serial adder
S 7 x + % + Q
JQ 7 x%
KQ 7 x% 7(x+%)
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4-bit binary ripple counter
J K Q(t+1)
0
0
1
1
0
1
0
1
Q(t)
0
1
Q(t)
3o next stage
Q J
Q J Q J Q J
1 1 1 1
(o1nt
p1lses
1 1 1 1 K K K K
A
=
A
;
A
4
A
1
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Count se)uence for a binary ripple counter
A
4
0
0
0
0
0
0
0
0
1
A
=
0
0
0
0
1
1
1
1
0
A
;
0
0
1
1
0
0
1
1
0
A
1
0
1
0
1
0
1
0
1
0
(omplement A
1
(omplement A
1
(omplement A
1
(omplement A
1
(omplement A
1
(omplement A
1
(omplement A
1
(omplement A
1
An# so onEE
A
1
"ill go 2rom 1 to 0 an# &omplement A
;
A
1
"ill go 2rom 1 to 0 an# &omplement A
;
A
;
"ill go 2rom 1 to 0 an# &omplement A
=
A
1
"ill go 2rom 1 to 0 an# &omplement A
;
A
1
"ill go 2rom 1 to 0 an# &omplement A
;F
A
;
"ill go 2rom 1 to 0 an# &omplement A
=F
A
=
"ill go 2rom 1 to 0 an# &omplement A
4
(o1nt se01en&e (on#ition 2or &omplementing 2lip2lops
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"tate %iagra( of a %eci(al 2C! counter
0000 0001 0010 0011 0100
1001 1000 0111 0110 0101
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$ogic %iagra( of a 2C! ripple counter
J K Q(t+1)
0
0
1
1
0
1
0
1
Q(t)
0
1
Q(t)
Q J
Q J Q J Q J
1
1
(o1nt
p1lses
1 1 1
1
K K K
Q
4
Q
G
0 0
Q
;
0
Q
1
0
0 1 0 1
Q K
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1 1 1 1
0 0 0 0
1
0 0
0
0
0
0
0
1
0
0
1
1
1
0
1
1
0
0
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
Timing diagram for the decimal counter
Q
1
Q
;
Q
=
Q
4
Q
<
(o1nt
p1lses
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B(-
(o1nter
B(-
(o1nter
B(-
(o1nter
(o1nt
p1lses
10
;
#igit 10
1
#igit 10
0
#igit
0HHH 0HH 0H
Block diagram of a 3-decade decimal BCD counter
Q
1
Q
;
Q
4
Q
G
Q
1
Q
;
Q
4
Q
G
Q
1
Q
;
Q
4
Q
G
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A
4
A
3
A
2 A
1

J K
K K K
(o1nt
ena!le
(*
3o
next
stage
J K Q(t+1)
0
0
1
1
0
1
0
1
Q(t)
0
1
Q(t)
4-bit synchronous binary counter

1
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A
4
A
3
A
2 A
1
CP

1
,
, ,
,
'P
!o3n
4-bit up-down binary counter
3o
Next
stage
3 Q(t+1)
0
1
Q(t)
Q(t)
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1 1 0 0 1 1 0 0 1
0 1 0 0 0 0 0 0 1
0 1 1 1 1 1 1 1 0
0 1 0 0 0 0 1 1 0
0 1 1 0 0 1 0 1 0
0 1 0 0 0 0 0 1 0
0 1 1 1 0 1 1 0 0
0 1 0 0 0 0 1 0 0
0 1 1 0 0 1 0 0 0
0 1 0 0 0 0 0 0 0
% 3Q
1
3Q
;
3Q
4
3Q
G
Q
1
Q
;
Q
4
Q
G
?1tp1t (arr% .lip2lop inp1ts (o1nt Se01en&e
,sing Kmaps4 "e get
3Q
1
71
3Q
;
7 Q
A
G
Q
1
3Q
4
7 Q
;
Q
1
3Q
G
7 Q
G
Q
1
+ Q
4
Q
;
Q
1
% 7 Q
G
Q
1
Q(t) Q(t+1) 3
0
0
1
1
0
1
0
1
0
1
1
0
!esign a 2C! counter using , flip-flops
*+citation table for a 2C! counter
4o3 logic %iagra( can be %ra3n for 2C! synchronous
counter
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y
CP
Q
1
Q
;
Q
4
Q
G
Q
1
Q
;
Q
4
Q
G
, , , ,
1
3Q
1
71
3Q
;
7 Q
A
G
Q
1
3Q
4
7 Q
;
Q
1
3Q
G
7 Q
G
Q
1
+ Q
4
Q
;
Q
1
% 7 Q
G
Q
1
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J
J
J
J
K
K
K
K
Count
+oa#
A
4
A
3
A
2
A
1
I
4
I
3
I
2
I
1
Clear
CP Carr!
out
Counters 3ith Parallel $oa%

4!it &o1nter "it)

parallel loa#.
,et -tate
.counting/
1 0 1
+oa# inputs * 1 1
,o C0ange 0 0 * 1
Clear to 0 * * * 0
1unction Count +oa# CP Clear
J K Q(t+1)
0
0
1
1
0
1
0
1
Q(t)
0
1
Q(t)
4!it !inar% &o1nter "it) parallel loa#
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A
4
A
3
A
2
A
1
Count 2 1
Clear 2 1
CP
Inputs 2 0
+oa#
(a) 2inary states 05152535456
A
4
A
3
A
2
A
1
Count 2 1
Clear 2 1
CP
+oa#
(c) 2inary states 10511512513514516
A
4
A
3
A
2
A
1
Count 2 1
+oa# 2 0
CP
Clear
(b) 2inary states 05152535456
A
4
A
3
A
2
A
1
Count 2 1
Clear 2 1
CP
+oa#
(%) 2inary states 35456575859
1 0 1 0 0 0 1 1
Carr!3out
Counters 3ith Parallel $oa%

-i22erent "a%s o2 getting a 5?-9 &o1nter

I
'
I
3
I
2
I
1
I
'
I
3
I
2
I
1
I
'
I
3
I
2
I
1
I
'
I
3
I
2
I
1
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"
#
33bit counter
Count enable
CP
CP
-tart
-top
&or#3time
control
&or#3time 2 4 pulses
,i(ing "e)uences
(a) (ir&1it -iagram
(!) Ieneration o2 a "or#time &ontrol 2or serial operations
CP
-tart
-top
Q
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5
3
5
2
5
1
5
0
2 * '
#eco#er
23bit counter
5
0
5
1
5
2
5
3
Count
enable
-0i6t rig0t
CP
5
0
5
1
5
2
5
3
(a) ring&o1nter (initial $al1e 7 1000)
(!) (o1nter an# -e&o#er

(&) Se01en&e o2 2o1r timing signals
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!

1
!

1
!

1
!

1
CP
A 2 C *
(a) 4-stage s3itch tail ring counter
A
1
2
1
C
1
*
1
C
1
* 1 0 0 0 9
2
1
C 1 1 0 0 8
A
1
2 1 1 1 0 7
A * 1 1 1 1 6
C *
1
0 1 1 1 4
2 C
1
0 0 1 1 3
A 2
1
0 0 0 1 2
A
1
*
1
0 0 0 0 1
An% gate re)uire%
for outputs
:lip-flop outputs
A 2 C *
"e)uence
nu(ber
b! Count
se"uence and
re"uired
decoding
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