Binary Parallel Adders

Subscript i

4 3 2 1

Full adder

Input carry

0 1 1 0

Ci

Augend

1 0 1 1

Ai

Addend
A

0 0 1 1

c
.
rs

Bi
e
e

Sum

n
E
1

Output carry

O
o

D
a
a

n
i
g1 1 0

0 0 1 1

m
o

Z
X
Y

Si

Ci + 1

B4 A4

C5

FA
S4

B3

C4

FA
S3

A3

B1 A1

B2 A2

C3

FA

C2

m
o

c
.
rs

e
e
in
S2

FA

g
n
4-BIT FULL
ADDER
E
O
An n-bit parallel adder
requires n full adders
o
Dhas 14 terminals
An IC of 4-bitaFA
a
It is an MSI
F function

C1
0

S1

The classical method would require a truth table with 512 entries
(9 input variable) (too cumbersome)

Not used
C5
A1
A2

S1

BCD
INPUT

Excess-3
Output

S2

A3
A4

S3

m
o

c
.
rs

S4

e
e
in

g
n

E
O

a
a
F

o
D
B1
B2
B3
B4

C1

BCD -to -Excess 3 Code

Converter

Z
CD

D
C

c
.
rs

(C+D)

e
e
in

C+D
B

g
n

E
O

m
o
X

o
D

a
a
F
A

Classical Method

Truth table for four inputs

K-maps for four outputs
Algebraic manipulation of expressions
Logic diagram using gates 4 x AND gates, 4 x OR gates
& 3 x inverters
Requires 3 IC packages & 14 wire connections
(excluding 1/0 connections)

m
o

c
.
rs

e
e
in

g
n

E
O

Alternate Design
o Methods

D
a
a

1 IC package , MS1 function , 5 wire connections

(excluding 1/O connections)

Ai
Pi

Si

Bi

Gi

c
.
s

r
e

e
in

Ci

g
n
Full Adder Circuit
E
O
o
D
a
a
F

m
o

Pi = Ai Bi

(Gi

carry generate )

Gi = Ai Bi

( Pi

carry propagate from Ci to Ci + 1)

Si = Pi Ci
Ci + 1 = Gi + PiCi

C2 = G1 + P1C1
C3 = G2 + P2C2 = G2 + P2 (G1 + P1C1) = G2 +P2G1 + P2P1C1
C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1C1

Ci + 1

C4

m
o

P3

c
.
rs

G3

e
e
in

g
n

E
O

P2
G2

P1
G1
C1

C3

o
D

a
a
F

C2

Logic diagram of a look - ahead carry generator

C2 = G1 + P1C1
C3 = G2 + P2G1 + P2P1C1
C4 = G3 + P3G2 + P3P2G1 + P3P2P1C1

B4
A4

C5

P4

C5
P4

G4

S4

C4

B3
P3
A3
G3

Look - ahead
Carry
Generator
C3

P2
G2

o
D

P1

A1

C1

g
n

E
O

B1

a
a
F

c
.
rs
P3

e
e
in

B2
A2

m
o

P2

S3

S2

C2

G1
C1

P1

4-Bits full adders with look - ahead carry

S1

Derivation of a BCD adder

Input

Binary Sum

K Z8 Z4
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 1
0 0 1
0 1 0
0 1 0

Z2

Z1

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

C
0
0
0
0
0
0
0
0
0
0

B C D Sum

S8

S4

S2

0
0
0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

S1 Decimal
0
0
1
1
0
2
1
3
0
4
1
5
0
6
1
7
0
8
1
9

m
o

c
.
rs

e
e
in

g
n

E
O

o
D

a
a
F

Output

K Z8 Z4 Z2 Z1
0 1 0
1
0
0 1 0
1
1
0 1 1
0
0
0 1 1
0
1
0 1 1
1
0
0 1 1
1
1
1 0 0
0
0
1 0 0
0
1
1 0 0
1
0
1 0 0
1
1

C
1
1
1
1
1
1
1
1
1
1

a
a
F

m
o

c
.
rs

e
e
in

g
n

E
O

o
D

S8 S4 S2 S1 Decimal
0 0
0
0
10
0 0
0
1
11
0 0
1
0
12
0 0
1
1
13
0 1
0
0
14
0 1
0
1
15
0 1
1
0
16
0 1
1
1
17
1 0
0
0
18
1 0
0
1
19

C = K + Z8 Z4 + Z8 Z2

Addend

Augend

4-bit binary adder

carry out

m
o

c
.
rs

Z8

Z4

carry in

Z2

Z1

e
e
in

Output
Carry

g
n

E
O

o
D

a
a
F

0 1 10

BLOCK DIAGRAM OF A BCD ADDER

4-bit binary adder

S8

S4

S2

S1

MAGNITUDE COMPARATOR
A = A3 A2 A1 A0

m
o

B = B3 B2 B1 B0
Xi = Ai Bi + Ai Bi

c
.
rs

(A = B) = x3x2x1x0

e
e
in

( i = 0, 1, 2, 3 )

g
n

E
O

o
(A > B) = A3 B3
+ x3 A2 B2 + x3 x2 A1B1+ x3x2x1A0B0
D
a
a
F
(A < B) = A3 B3 + x3 A2 B2 + x3 x2 A1B1+x3x2x1A0B0

A3
x3
B3

m
o

A2

c
.
rs

x2

ee

B2

n
i
g

A1

n
E

O
o

D
a
a

B1
A0

(A < B)

x1

(A > B)
x0

B0

(A = B)
4 bit magnitude comparator

D0

x y z

D1

x y z

D2

m
o

D3

x y z

D4

x y z

D5

x y z

D6

x y z

D7

x y z

c
.
rs

e
e
in

g
n

x
Input lines = n

o
D

E
O

a
a
F

x y z

Output lines = 2n (Maximum)

n to m decoder
M 2n

A 3 to 8 line decoder (Binary to Octal application)

Truth table of a 3 to 8 line decoder

Outputs

Inputs
x

D0

D1

D2

D3

D4

g
n

aa

F1

E
O0

D
m
o

D7

D5

c
.
0
s
r

e0
e
in
0

o
D0

Design a BCD to Decimal Decoder

y

yz

00

01

11

D0 = w x y z

m
o

10

D1 = w x y z

c
.
rs

wx

00

D0

D3

e
e
in

D2

D
01 D D D ng
E
O
11 XDo
X X X
a
a
F
10 D D X X
4

D1

D2 = x y z
D3 = x y z
D4 = x y z
D5 = x y z
D6 = x y z
D7 = x y z
D8 = w z
D9 = w z

z
Map for simplifying a BCD to decimal decoder

D0 = w x y z
D1 = w x y z

w
D2 = x y z

m
o

c
.
rs

D3 = x y z

ee

n
i
g

n
E

O
o

D
a
a

F
z

D4 = x y z
D5 = x y z
D6 = x y z
D7 = x y z
D8 = w z
D9 = w z

BCD TO DECIMAL DECODER ( 4 LINE TO 10 LINE)

PARTIAL TRUTH TABLE

Inputs

Outputs

m
D D DcoD D
.
s
r
0 e0 0 0 1
e

D0 D1 D2 D3

a
F

n
i
1 0 0 0 g1 0
n
0 0 O
0E 0 0 1
o
a1 D0 0 0 0 0

D9

x
y
z

0
1
22
2
3
3
x
8
21
decoder 4
5
20
6
7

S (x, y, z) =

(1, 2, 4, 7)

c (x, y, z) =

(3, 5, 6, 7)

m
o

c
.
rs

e
e
in

g
n

E
O

o
D

a
a
F

Implementation of a full adder with

a decoder and two OR gates

DEMULTIPLEXERS

A decoder with an enable input can function as

m
o
a demultiplexer. It receives information
on a
c
.
s
r
single line and transmits this
information
on
e
e
n
one of 2 possible outputin
lines.
g
n
A 2 to 4 line decoder
with E input is shown
E
O circuit operates as a decoder
When E = 0,othe
D
a
with comlemented
outputs.
a

 The decoder can function as a demultiplexer if E line is taken

as a data input line and A & B lines are taken as the selection
line.
2 decoders (3x8) can be connected to form a larger decoder
circuit (4x16)

m
o

c
.
rs

when:

e
e
in

W = 0, top decoder is inabled

(0000 0111)
W = 1, bottom decoder is enabled
(1000 1111)

g
n

E
O

a
a
F

o
D

Digital function can be easily expanded to accommodate more

inputs and outputs by using e lines

Demultiplexer
A
0
0
1
1

(A B ) = A + B

B
0
1
0
1

D0

m
o

(A B ) = A + B

c
.
rs

e
e
in

g
n

E
O

o
D

a
a
F

D1

(A B ) = A + B
D2
(A B ) = A + B

(a) LOGIC DIAGRAM WITH NAND GATES

D3

D0

D1

D2

D3

ee

n
i
g 1

n
E1

O
o

m
o 1

c
.
rs

DTRUTH TABLE
a
a

A 2 TO 4 LINE DECODER WITH ENABLE E INPUT

D0

A
Inputs

2X4

D0

D1

Decoder

D2
D3

Input

D1

1X4

m
o

Demultiplexer

c
.
rs

e
e
iEn

g
n

E
O

Enable

o
D

a
a
F

(a) Decoder with enable can

function as demultiplexer

Select

(b) Demultiplexer

D2
D3

3X8
y

D0 to D7

Decoder

0000 to 0111

m
o

c
.
rs

e
e
in

g
n

E
O

aa

o
D

3X8

Decoder

D8 to D15
1000 to 1111

A 4x16 Decoder Constructed with two 3x8 Decoders

ENCODERS
An encoder produces a reverse operation of a decoder
Input lines
Output lines

m
o

c
.
rs

2n
n

e
e
An octal-to-binary encoder circuit
has 8 inputs and 3
n
i
g
outputs.
n
E
Only one input line
can be equal to one at any time.
O
o
Possible input
combinations
= 2 = 256
D
a
a
Meaningful combinations
= 8
F
Dont care conditions
= 248
8

 Priority encoder establishes an input priority to

ensure that the highest priority input line is encoded.
D2

If input

1
D5

c
.
rs

e
e
line
D5in is
encoded
g
n
because
of higherpriority
E
O
o

Output

m
o

D
a
a

When D0 is not connected to any OR gate, then

binary output is 000.

D0

x = D4+ D5 + D6 + D7

D1

m
o

D2

c
.
rs

e
e
in

D3

g
n

E
O

D4
D5
D6
D7

y = D2+ D3 + D6 + D7

o
D

a
a
F

Octal to binary encoder

z = D1+ D3 + D5 + D7

TRUTH TABLE
0
1
2
3
4
5
6
7

D0

INPUTS (Octal)
D1 D2 D3 D4 D5 D6 D7

1
0
0
0
0
0
0
0

0
1
0
0
0
0
0
0

0
0
1
0
0
0
0
0

0
0
0
1
0
0
0
0

0
0
0
0
1
0
0
0

0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
1

m
o

c
.
rs

e
e
in

g
n

E
O

o
D

a
a
F

0
0
0
0
0
1
0
0

OUTPUTS (binary)
x
y
z
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

Multiplexers
A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines
and directs it to a single output line.
input lines = 2n
output lines = 1
selection lines = n
An example of 4-line-to-1-line shows that:
input lines = 22 = 4 (I0, I1, I2 & I3)

m
o

c
.
rs

e
e
in

g
n

E
O

o
D

a
a
F

output lines = 1 (Y)

selection lines = 2 (s0 & s1)

 A multiplexer is also called a data selector

since it selects one of many inputs and
steers
m
o
c
the binary information to the output
line.
.
s
r
e enable input to
Multiplexer ICs can haveean
n
i
control the operation g
of the unit. When E is in
n
E
disable state, outputs
= 0. When E is in enable
O
o
state, the circuit
functions as a normal MUX.
D
a
a
The F
E strobe can used to expand two or more
ICs (MUXs) to provide a larger number of
inputs.

I0

(a) Logic Diagram

I1
Y

m
o

I2

c
.
rs

I3

e
e
A
4-to-1 Line Multiplexer
n
i

S0

E
O
0

I0

I1

I2

I3

S1

o
D

S1
S0

a
a
F

g
n

(c) Function Table

inputs
0
1 4x1 Y
MUX
2
3 S
S0
1

Select
(b) Block Diagram

output

A1

Y1

A2

Y2

m
o

A3

Y3

c
.
rs

A4

e
e
in

B1

g
n

E
O

B2

o
D

B3

a
a
F

B4

Y4

Function Table
E
1
0
0

S
X
0
1

Output Y
all 0s
Select A
Select B

S
(Select)
E

(Enable)

Quadruple 2-to-1 Line multiplexer

4 x MUXs
E = 1, Y1 -Y4 = 0
When E = 0, S = 0:

Function Table
E
1
0
0

S
X
0
1

Y1 = A1
Y2 = A2
Y3 = A3
Y4 = A4
When E = 0, S=1 Y1 = B1 ,Y2=B2, Y3=B3 & Y4=B4

Output Y
all Os
Select A
Select B

c
.
rs

m
o

e
e
in

g
n

E
O

o
D

Applications:Used for connecting 2 or more sources to a single

destination among computer units.
Used for constructing a common bus system

a
a
F

Boolean Function Implementation

Example :- F(A,B,C)= (1,3,5,6)
0

I0
I1
I2
I3

1
A
A

4x1
MUX
S1

Minterm

S0

g
n

C
(c) Multiplexer Implementation

4
0

I1

I2

o
D

E
O

a
a
F

I3

(b)Implementation Table

A B C

0
0
0
0
1
1
1
1

0
1
0
1
0
1
1
0

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

m
o

c
.
rs

e
e
in

I0

0
1
2
3
4
5
6
7

S1 S0

(a) Truth Table

It is possible to generate any
function of n+1 variables with
2n-to-1 Multiplexer

Implementing F(A,B,C)= (1,3,5,6) with a multiplexer

Alternate implementation for F(A,B,C)= (1,3,5,6)

C
C

I0

I1

I2

I3

S1 S0

A
0
0
1
1
0
0
1
1

1
C

3
C

(b) Implementation Table

C
0
0
0
0
1
1
1
1

F
0
0
0
0
1
1
1
1

(a) Truth Table

m
o

I0
I1
I2
I3

c
.
rs

e
e
in

g
n

E
O

o
D

a
a
F

0
2
4
6
1
3
5
7

B
0
1
0
1
0
1
0
1

4x1
MUX

S1

s0

A
B
(c) Multiplexer Implementation

Example:- F(A,B,C,D)= (0,1,3,4,8,9,15)

I0
I1
I2
I3
I4
I5
I6

1
0

8x1
MUX

I7 S2

S1

e
e
in

g
n

I1
1

F
A

S1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

S0
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

m
o

I2

E
O

I3

I4

I5

I6

I7

o
D

aa

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

c
.
rs

S0

C
D

I0

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

S2
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

10

11

12

13

14

15

F
1
1
0
1
1
0
0
0
1
1
0
0
0
0
0
1

READ ONLY MEMORY ROM

ROM is a device that includes both the decoder and the OR gates within a
single IC package.
It is usually used to implement a complex comb. circuit in one IC package
and eliminates all interconnecting wires between a decoder and OR gates.
It is a memory device in which binary information is stored fusing or
breaking internal links in order to form required circuit paths.

m
o

c
.
rs

e
e
in

If a ROM has:
input lines
output lines

=n

g
n

o
D

E
O
=m

a
a
F

Then:

Distinct Addresses (words)

= 2n

Total no. of bits stored in ROM = 2n x m

(Where m denotes no. of bits per word)

32 x 8 ROM means:

Words = 32 of 8 bits each

Output lines = 8
Input lines = 5
Total bits = 256 (25 x 8)

m
o

c
.
Internal construction of a 32 x 4 ROM can
be shown using a
s
r
decoder and four OR gates
e
e
n
i
g
n
E
O
o
D
a
a
F
ROM BLOCK DIAGRAM

n inputs
2n x m
ROM

m outputs

ADDRESS
INPUTS

Logic Construction of a 32 x 4 ROM

(32words of 4 bits each)
Total bits stored = 32 x 4 = 128

A0

A1

A2
A3
A4

INPUTS = 5

m
o

MINTERMS

5 x 32
decoder

e
e
in

g
n

E
O
2

o
D

a
a
F

c
.
rs

31

128 LINKS

WORDS = 32
BITS/WORD = 4
OUTPUTS = 4

F1

F2

F3

F4

Combinational Logic Implementation - ROM

For an n-input, m-output combinational circuit of a 2n x m ROM is needed

The opening of the links is referred to as programming
ROM program table gives the information for the required paths in the
ROM
Example:
F1(A1, A0) = (1,2,3)

m
o

c
.
rs

F2(A1, A0) = (0,2)

Truth Table A1 A0 F1 F2

E
O

g
n

e
e
in

0 0 0 1
0 1 1 0
1 0 1 1
1 1 1 0
Combinational circuit implementation with a 4 x 2 ROM is shown:
With AND OR gates
With AND-OR-Inverter gates

a
a
F

o
D

00
A0

ROM with
AND-OR gates

01

2x4
decoder

m
o

10

c
.
rs

11

A1

e
e
in

g
n

TRUTH TABLE
A0

A1

F1

0
0
3
4

0
1
0
1

0
1
1
1

E
O

F2

a
a
F

o
D
1
0
1
0

F1

F2

Combinational Circuit Implementation With a 4 x 2 ROM

Combinational Circuit Implementation With a 4 x 2 ROM

00
A0

ROM with
AND-OR-INVERTER
gates

01

2x4
decoder

m
o

10

c
.
rs

11

A1

e
e
in

g
n

E
O

TRUTH TABLE
A0

A1

0
0
3
4

0
1
0
1

F1

o
D

a
a
F
0
1
1
1

F2
1
0
1
0

F1

F2

F1

F2

 Types of ROM
Mask programming (ROM)

m
o

PROM

c
.
rs

EPROM

e
e
in

EAROM

Uses

g
n

E
O

to implement complex CC from truth tables

o
D

to convert one binary code to another

a
a
F

to implement arithmetic functions

to display of characters on CRT
to design microprogrammed control units

(i)

TRUTH TABLE

Inputs (3)

Outputs (6)

Decimal

A2

A1

A0

B5

B4

B3

B2

B1

B0

0
O
o

n
E

a
F1

0
D
a
1

1
c
.
rs
0

0
e
e0 0

0
1

16

25

36

49

n
i
g
1

m
o

Example: Design a comb. circuit using a ROM. The circuit

accepts a 3-bit number and generates an output binary
number equal to the square of the input number.

A2

(ii)
A1

(iii)

A0

8x4
ROM
F1

B5

F2

B4

F3

B3

F4

o
D

B1

BLOCK DIAGRAM

a
a
F

A1

A0

F1

F2

F3

F4

m
o

e
e
in

B0

c
.
rs

g
n

E
O

B2

A2

ROM TRUTH TABLE

ROM Implementation

Programmable Logic Array (PLA)

All the bit patterns available in the ROM are not used due to dont care
conditions which results into wastage of equipment

m
o

c
.
rs

Size of the ROM required to convert a 12-bit card code to a 6-bit internal
alphanumeric code:
4096
212

e
e
in

input

E
O

output

o
D

valid entries = 47

aa

dont care conditions = 4049

g
n

A-Z

26

Numbers =

10

other char=

11
47

It is more economical to use PLA (LSI) in such cases to avoid wastage.

Programmable Logic Array (PLA)

A block diagram of the PLA consists of:

n inputs

m
o

m outputs

c
.
rs

k product terms

e
e
in

m sum terms

Output function:

AND-OR form

g
n

AND-OR-INVERTOR form

E
O

o
D

A typical PLA has : n = 16, m = 8, k = 48 programmed links

a
a
F

PLA

2n * k + k * m + m

ROM
2n * m = 216 x 8

1928

524288

272

nxk

Links
kxm

K Product
terms
Inputs n x k

(AND gates)

Links

Links
m
o

c
.
rs

e
e
in (OR

Links

g
n

E
O

m Sum
terms

gates)

o
D

a
a
F

PLA BLOCK DIAGRAM

m output

IMPLEMENTATION OF PLA COMB CIRCUIT

Mask programmable (PLA)

Field programmable (FPLA)
PLA program table is required to program a PLA
Truth table of the comb. Circuit can be used to simplify the function to get
the minimum AND gates (sum of products)

m
o

c
.
Paths are specified in its AND OR or AND s
OR - INVERT
r
pattern by programming PLA
e
e
n
PLA program table contains:
i
g
n
E
O
o
T is written if the output
inverter is to be bypassed
D
a
C is written
if the output inverter is not to be bypassed
a
F Variable is unprimed
3

1st column - lists product terms numerically

2nd column - specifies the required paths between OR gates and AND gates

0
-

variable is primed
Variable is absent

EXAMPLE#1
F1 (A, B,C) = (4,5,7)
F2 (A,B,C) = (3,5,7)

m
o

c
.
rs

e
e
in

g
n

E
O

a
a
F

o
D

B
BC

00

01

11

10

BC

11

01

A
0

00

C
F1(A,B,C)=(4,5,7)
F1=AB+AC

a
a
F

g
n

E
O

o
D

c
.
1
s
r

e
e
in
1

Map simplification

m
o
1

C
F2(A,B,C)=(3,5,7)
F2=AC+BC

10

TRUTH TABLE
A

F1

F2

BC

PLA Program table

c
.
rs
1

ee

n
i
g

n
E

O
o

D
a
a

AB
AC

Product
term
1
2
3

m
o

Inputs
A B
1
0
1
1

C
1
1

1
0

Outputs
F1
F2
1
1
1
1
T

STEPS REQUIRED IN PLA IMPLEMENTATION

T/C

A
AB + AC

AB

m
o

B
2
AC

c
.
rs

n
i
g

AC + BC
e
e

n
E

O
o

D3
a
a

BC

PLA Links = 26

F1

F2

n=3
m=2
K=3
K *m +
(6)

m
(2)

PLA with 3 inputs, 3 product terms, and 2 outputs; it

implements the combinational circuit

EXAMPLE#2
F1(A,B,C)=(3,5,6,7)

m
o

F2(A,B,C)=(0,2,4,7)

c
.
rs

e
e
in

g
n

E
O

a
a
F

o
D

BC
00
0
1

01

11

BC
00

01

11

1A

n
i
g

n
E

O
o 0

D
a
a
0
F

C
F1=BC+AC+AB

BC

0 A
A
1

10

1
1

m
o

c
.
rs

ee

10

11

01

F2=BC+AC+ABC
B

00

0 A

F1=AC+AB+BC

10

BC

00

C
B

01

11

10

C
F2=BC+AC+ABC

PLA Program Table

BC
AC
AB
ABC

Product
term
1
2
3
4

A
0
0
1

aa

Examples
F1(A,B,C)=(3,5,6,7)

F2(A,B,C)=(0,2,4,7)
F1=(BC+AC+AB)
F2 =BC+AC+ABC

C
0
0
1

Outputs
F1
F2
1
1
1
1
1
1

m
o

c
.
rs

e
e
in

g
n

E
O

o
D

Inputs
B
0
0
1

Condition
Inputs=3
Product term=4
Outputs =2

T/C

m
o

c
.
HOME ASSIGNMENT
s
r
e THE
DRAW CIRCUIT FROM
e
n
i
g
PLA IMPLEMENTATION
TABLE
n
E
O

a
a
F

o
D