VLSI Design There are many different styles of design Full custom Every gate is special Basically not done anymore Application Specific Integrated Circuits (ASIC) Gates all come from library, but connections all unique System on Chip (SOC) Chip consists of blocks that were all created before Silicon printed circuit board Real VLSI chips often use a little bit of all three styles in them Might be one custom analog block, ASIC gates, and a couple of larger IP blocks Levels of Abstraction Have different levels of details Top level is your goal Initially not executable Often becomes C++ code Then create microArch Rough hardware resources Rough communication Can be executable VLSI 2008 (7) March (7) Most of the students of Electronics Engineering ar... THE VLSI DESIGN PROCESS MOST OF TODAYS VLSI DESIGNS ARE CLASSIFIED INTO T... DEVELOPMENTS IN THE FIELD OF VLSI Evolution of Integrated Circuits Steps involved in VLSI Design Fundamentals of VLSI Chip Design About Me INDIAN GIRL I completed my B.Tech in E.C.E. and I have lot of interest in VLSI & Embedded Systems. View my complete profile NEWS Apple Google Microsoft Report: Apple May Charge $100 More Yahoo News Our checks indicate Apple has started negotiating with carriers on a $100 iPhone 6 price increase. The initial response has been no, but there seems to be an admission that there is no other game-changing device this year. A new iPhone 5s 0 More Next Blog Create Blog Sign In VLSI VLSI: Steps involved in VLSI Design http://vlsisource.blogspot.in/2008/03/steps-involved-in-vlsi-design.html 1 of 11 4/15/2014 9:10 PM Functional Model Design is never top down or bottom up. It is really iterations to match the constraints on both ends: hardware and spec. Validation Remember that those polygons must match specification Ensure each implementation matches specification But typically only simulate the system at the top levels Automatic tools only work at the bottom levels Implies need to create a lot of testing infrastructure Use higher level simulation to drive and check implementation Check the correspondence using formal methods (math) VLSI design is mostly about validation Not about creating the circuit/function But about making sure that unit meets spec Functional, area, and power Design Methodologies and Flows Design Flows: with 16 GB ... Related Articles Apple antitrust compliance off to a Reuters In a 77-page report filed in U.S. District Court in New York, Bromwich said the relationship between his team and Apple has "significantly improved" since a federal appeals court in February rejected the iPhone maker's bid to halt his work. But ... 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Related Articles powered by VLSI: Steps involved in VLSI Design http://vlsisource.blogspot.in/2008/03/steps-involved-in-vlsi-design.html 2 of 11 4/15/2014 9:10 PM Left fork: Full custom Center fork: ASIC Right fork: System on Chip Full Custom Design Flow Gives the designer the most freedom Lots of rope Can be clever Can hang yourselves too For a specific function Can achieve best performance Speed, power, area, etc Most work/time per function Optimizations are at a low level Circuit better be important Think assembler, only worse VLSI: Steps involved in VLSI Design http://vlsisource.blogspot.in/2008/03/steps-involved-in-vlsi-design.html 3 of 11 4/15/2014 9:10 PM Schematic Capture/Simulation Circuit drawn many levels Transistor, gate, and block Uses hierarchy Blocks inside other blocks Allows reuse of designs Tool create simulation netlists Components and all connections Layout Draw and place transistors for all devices in schematic Rearrange transistors to minimize interconnect length Connect all devices with routing layers Possible to place blocks within other blocks Layout hierarchy should match schematic hierarchy VLSI: Steps involved in VLSI Design http://vlsisource.blogspot.in/2008/03/steps-involved-in-vlsi-design.html 4 of 11 4/15/2014 9:10 PM Design Rule Checking Fab has rules for the polygons Required for manufacturability DRC checker looks for errors Width Space Enclosure Overlap Lots of complex stuff (more later) Violations flagged for later fixup Layout Versus Schematic Extracts netlist from layout by analyzing polygon VLSI: Steps involved in VLSI Design http://vlsisource.blogspot.in/2008/03/steps-involved-in-vlsi-design.html 5 of 11 4/15/2014 9:10 PM overlaps Compares extracted netlist with original schematic netlist When discrepancies occur, tries to narrow down location Layout Parasitic Extraction (LPE) Estimates capacitance between structures in the layout Calculates resistance of wires Output is either a simulation netlist or a file of interblock delays ASIC Design Flow Separate teams to design and verify VLSI: Steps involved in VLSI Design http://vlsisource.blogspot.in/2008/03/steps-involved-in-vlsi-design.html 6 of 11 4/15/2014 9:10 PM Physical design is (semi-) automated Loops to get device operating frequency correct can be troubling Register Transfer Level (RTL) Sections of combinational Goo separated by timing statements Defines behavior of part on every clock cycle boundary Construct Logic Synthesis Changes cloud of combinational functionality into standard cells VLSI: Steps involved in VLSI Design http://vlsisource.blogspot.in/2008/03/steps-involved-in-vlsi-design.html 7 of 11 4/15/2014 9:10 PM (gates) from fab-specific library Chooses standard cell flipflop/ latches for timing statements Attempts to minimize delay and area of resulting logic Standard Cell Placement and Routing Place layout for each gate (cell) in design into block Rearrange cell layouts to minimize routing Connect up cells VLSI: Steps involved in VLSI Design http://vlsisource.blogspot.in/2008/03/steps-involved-in-vlsi-design.html 8 of 11 4/15/2014 9:10 PM System On Chip Design Flow Can buy Intellectual Property (IP) from various vendors Soft IP: RTL or gate level description Synthesize and Place and Route for your process. Examples: Ethernet MAC, USB Hard IP: Polygon level description Just hook it up Examples: XAUI Backplane driver, embedded DRAM Also: Standard cell libraries for ASIC flow Chip Assembly Integrate blocks from previous steps Real chips have different types of blocks VLSI: Steps involved in VLSI Design http://vlsisource.blogspot.in/2008/03/steps-involved-in-vlsi-design.html 9 of 11 4/15/2014 9:10 PM Posted by INDIAN GIRL at 11:51 PM Can resemble picture on right Key is to have a early plan And continue to update it Need to have accurate floorplan Early Floorplanning is key Sets the specs for the components Functional, physical, timing Validation and Tape Out Making a mistake is very expensive Have a tool check all previous types of mistakes Check all errors, sign off on false positives, fix errors Run check tool again Tape out Used to write 9-track computer tapes for mask making Now, transfer polygons to fabrication company via ftp Youre done! (Except for documentation, test vector generation, device bringup, skew lots, reliability tests, burnin) VLSI: Steps involved in VLSI Design http://vlsisource.blogspot.in/2008/03/steps-involved-in-vlsi-design.html 10 of 11 4/15/2014 9:10 PM Newer Post Older Post No comments: Post a Comment Links to this post Create a Link Home Subscribe to: Post Comments (Atom) VLSI: Steps involved in VLSI Design http://vlsisource.blogspot.in/2008/03/steps-involved-in-vlsi-design.html 11 of 11 4/15/2014 9:10 PM