Magma ASIC Design Flow

Magma For You in Three Hours (MYTH) - Hour I

MYTH is not a myth
V. Kamakoti and Shankar Balachandran
Reconfigurable Intelligent Systems Engineering Lab
Department of CSE, IIT Madras
1. About The Document:
This document briefly explains the usage of Magma Electronic Design Automation (EDA) Tool for the design of
the Application Specific Integrated Circuit (ASIC) Flow. This tool will take you from Register Transfer Level (RTL)
to Graphical Design Standard II (GDSII) format.
2. The basic requirement to use this document:
This document is prepared aiming the person with little digital circuit design knowledge using any HDL language.
Assuming the person is aware of the ASIC Design flow and Digital Optimization techniques (Is explained briefly
below).
3. Introduction to ASIC Design Flow:
Any IC other than a general purpose IC which contain the functionality of thousands of gates is usually called an
ASIC (Application Specific Integrated Circuit). ASICs are designed to fit a certain application. An ASIC is a digital
or mixed-signal circuit designed to meet specifications set by a specific project. The basic ASIC Design Flow is
Shown in Figure 3.1.
Figure 3.1: ASIC Design Flow
ASIC Design Tutorial using Magma Blast Fusion http://nptel.iitk.ac.in/courses/Webcourse-contents/IIT-MADRAS/CAD fo...
1 of 6 4/15/2014 7:54 PM
Figure 3.2: EDA Tool Flow for ASIC Design
The EDA Tool that is used for synthesis of a RTL code to GDS II format is Magma Blast Fusion. The details of the
Magma Design Flow is explained below
4. Introduction Magma ASIC Design Flow:
Blast Plan Pro is used for the hierarchical design of large integrated circuits (ICs) and systems-on-chip (SoCs)
with Magma's production-proven RTL-to-GDSII flow. Hierarchical design methodologies are typically adopted to
handle very large designs or to support the concurrent design of a complex chip by a design team. Blast Plan
Pro meets both of these requirements and delivers the additional benefit of predictable design closure.
The Magma tools form an integrated set of design engines that are combined with a Tcl interpreter and a
sophisticated graphical user interface (GUI). These tools are software applications developed and distributed by
Magma Design Automation Incorporated.
The typical simplified design flow of the Magma Blast Fusion is shown in the below Figure 3.
This tutorial describes how to use the Magma Blast Fusion using command prompt to run these steps on a
provided design. Follow the instructions provided in this tutorial to create scripts that perform the steps for the
provided design.
The following Figure 4 shows the structure of this tutorial. The instructions for importing the design and
constraints depend on whether you start from a netlist or from RTL. After you import the design and
ASIC Design Tutorial using Magma Blast Fusion http://nptel.iitk.ac.in/courses/Webcourse-contents/IIT-MADRAS/CAD fo...
2 of 6 4/15/2014 7:54 PM
constraints, the remaining flow steps are the same.
These instructions use only the options applicable to the provided design, but the other options in the command
prompt are operational. The Magma tool flow supports design entry using the GUI mode and Text mode. The
RTL to GDSII flow is explained using a sequential circuit.
5. The Magma RTL to GDSII using command prompt:
The detailed flow is explained in the three stages as follows:
Stage 1: Invoking Mantle, Import RTL Design and Imoport Design Constraints
Invoking Mantle
Step - 1: Create a directory where you want put all your magma synthesis documents. In this example, aes is
the working directory.
bash-2.05b$ mkdir aes
This will create a directory called "aes" . Copy your all RTL Code in to the created directory. Then go to the
directory to invoke the magma tool.
bash-2.05b$ cd aes
Step - 2: Invoke the mantle using the path "/magma/2004_12_29.0014/linux24_x86_64/bin/mantle". Mantle is
the command prompt of the Magma Blast Fusion Tool.
bash-2.05b$ /magma/2004_12_29.0014/linux24_x86_64/bin/mantle
MEM-4 WARNING: Unusually large stacksize of 17592186044416.0MB reserved by
user's shell resource limits. This may inhibit utilization of all
available system memory resources. Recommended is 8000k
Copyright (C) 1997-2004 Magma Design Automation Inc.
mantle version 4.1.57-linux24_x86_64 (compiled Dec 28 2004 23:43:34)
LIC-1 Setting default license file to
'/magma/2004_12_29.0014/common/license'.
LIC-12 The following features have been checked out: BLAST_VIEW BLAST_WRAP
BLAST_SPEED BLAST_BUILDER BLAST_PLAN BLAST_RTL BLAST_LOGIC BLAST_SI
BLAST_RAIL
OSD-100 Running /magma/2004_12_29.0014/linux24_x86_64/bin/mantle on host
"vlsi2" with pid 30575 for user "temp" started on Thu Mar 01
01:18:55 PM IST 2007 in directory /home/temp/noors/aes
mantle[1]>
Note: If you have any problem in opening the mantle please contact to CS623 TAs. If you come across any
error stating Error UI-39 in invoking the tool ask System Administrator to run "nscd" demon. If you come
across any license related problems, then use "export LM_LICENSE_FILE=2700@10.6.5.27" at your command
ASIC Design Tutorial using Magma Blast Fusion http://nptel.iitk.ac.in/courses/Webcourse-contents/IIT-MADRAS/CAD fo...
3 of 6 4/15/2014 7:54 PM
prompt. Still if you have any problem please contact System Administrator.
Directory Structure Generated by Magma
Files generated by Magma: You can also review the contents of two automatically-generated directories. The
logfiles directory contains logs of the sessions you run, and the snap directory contains volcanos and reports of
design statistics that reflect the design at the end of each part of the flow.
Logfiles Directory: When you start the tool, a file called mantle.log is created. This file is usually the most
useful file in the logfiles directory. It contains a full record of your latest session. With each new session you
start, the file is renamed to mantle#.log (# is a number) and the mantle.log file is overwritten with the latest
information. In the tool, to find where the file has been saved, use the query logfile command.
Snap Directory: The snap directory is created locally in the directory where you have started the tool. This
directory stores snapshot volcanos and status reports that show design statistics during the flow. Use a text
editor to review the snapshot reports or use a snapshot volcano to rerun the flow from a specific step. There
are several config, query and report commands related to snap, which are identified in the man pages.
Step - 3: To invoke the Graphical User Interface (GUI) use the following command.
mantle[1]> ui start
The above command will opens the GUI based work space of the Magma Blast Fusion as shown in the Figure
5.1.
Importing the Library Volcano
To use the provided design library, import the library and technology rules together in the form of a Volcano. A
Volcano is a Magma database that stores design information.
Step - 4: Import the library using the following command where all the logic cells are stored. (Please verify the
library path with course TA). In this example we are using the Magma 130nm library cell for synthesis. Import
volcano command reads the data model from a disk.
mantle[0]:> import volcano /magma/cl013lv.volcano
mantle[0]:>import volcano /magma/cl013lv.volcano
MSG-10 While running 'import volcano /magma/cl013lv.volcano':
LAVA-333 This volcano erupted Tue Jan 21 12:42:38 2003 EST for user jwalston (Joe Walston)
(v14c1)
LAVA-24 'import volcano' importing global config settings from volcano, existing settings
maybe overwritten
LAVA-27 Reading library /cl013lv
LAVA-874 All cells were bound as a result of this 'import volcano'.
LAVA-902 Melted back from volcano '/magma/cl013lv.volcano' ( 2 seconds elapsed of which
2 on CPU).
LAVA-249 Volcano file size: 34.6 MByte (57.1 MB data, Compression = 1.65x)
LAVA-251 Data throughput 21.631 MB/s (2.64 s elapsed)
"Set l " set the variable for library name. The library name that we are using is cl013lv.
mantle[0]:>set l /cl013lv
mantle[0]:>set l /cl013lv
/cl013lv
Import the RTL Design
Step - 5: Now import your RTL code in a sequence of top module file is followed by the rest of the design files.
For purpose of clear explanation here we are using a standard AES design. It is designed using verilog and
whose topmodule name is "aes_cipher_top". AES design contains the following verilog files.
aes_cipher_top.v (Top Module)
aes_sbox.v
aes_rcon.v
aes_key_expand_128.v
Step - 6: "import rtl" reads the RTL files. To analyze RTL code use "-analyze" at the end. "-analyze" is optional
command.
mantle[0]:> import rtl aes_cipher_top.v aes_sbox.v aes_rcon.v aes_key_expand_128.v
ASIC Design Tutorial using Magma Blast Fusion http://nptel.iitk.ac.in/courses/Webcourse-contents/IIT-MADRAS/CAD fo...
4 of 6 4/15/2014 7:54 PM
mantle[0]:>import rtl aes_cipher_top.v aes_sbox.v aes_rcon.v aes_key_expand_128.v
MSG-10 While running 'import rtl aes_cipher_top.v aes_sbox.v aes_rcon.v
aes_key_expand_128.v':
RTL-3 Building model aes_cipher_top(aes_cipher_top)
RTL-3 Building model aes_key_expand_128(aes_key_expand_128)
RTL-3 Building model aes_sbox(aes_sbox)
RTL-3 Building model aes_rcon(aes_rcon)
/work/aes_cipher_top/aes_cipher_top
Step - 7: "set m" set the variable for the top level Design. In this design the top level model is "/work
/aes_cipher_top/aes_cipher_top". The top level model path is displayed at the end of the report of the "import
rtl" command.
mantle[0]:>set m /work/aes_cipher_top/aes_cipher_top
mantle[4]:>set m /work/aes_cipher_top/aes_cipher_top
/work/aes_cipher_top/aes_cipher_top
Step - 8: "fix rtl" performs RTL optimizations.
mantle[5]:> fix rtl $m
To See the mantle Report click here
Step - 9: "fix netlist" performs the logical optimizations.
mantle[5]:> fix netlist $m $l
To See the mantle Report click here
Step - 10: "export verilog netlist" saves the verilog netlist file to specified file name for example
"filename_netlist.v". The proper usage of export command is shown below.
mantle[5]:> export verilog netlist $m aes_cipher_top_netlist.v
To See the mantle Report click here
Note: The Netlist to GDSII flow will start from next point. You can import any netlist file to the magma flow.
Step - 11: "run bind logical" will bind the unbound cells to the target library.
mantle[5]:> run bind logical $m $l
To See the mantle Report click here
Step - 12: "report model" Checks the model for basic netlist and floorplan integrity (for example, cell overlap
and dangling input pins, etc.,).
mantle[5]:> report model $m
To See the mantle Report click here
Now you can see the circuit model schematic by selecting the "Open Schmatic viewer" in the "Viewers" tab of
the GUI. It will ask the schematic model name, Specify the model name in this design example is "/work
/aes_cipher_top/aes_cipher_top". The schematic diagram of the whole design (AES) is shown in Schematic1,
Schematic2 (zoom) and Schematic3 (zoom), Schematic4 (zoom), and worst path in Schematic viewer.
Import Design Constraints
Import the design constraints to review a timing check and timing report to make sure the constraints are
complete and to establish a timing baseline for later comparison.
Step - 13: "force timing clock" will assign the timing constraint to the clock. To estimate the Worst late slack
assign the clock period, rise and fall times of the clock. In this design example we are assigning the clock period
as 1000ns (1 MHz clock) and, rise and fall times are 5ns and 10ns respectively.
Note: This command is used only in case of sequential circuits. (This command is not required in case of
combinational circuit ). In general the combinational ciruit will have the +INF worst late slack.
mantle[11]:> force timing clock {/work/aes_cipher_top/aes_cipher_top/mpin:clk} 1000n -waveform
ASIC Design Tutorial using Magma Blast Fusion http://nptel.iitk.ac.in/courses/Webcourse-contents/IIT-MADRAS/CAD fo...
5 of 6 4/15/2014 7:54 PM
{-rise 5n -fall 10n}
Step - 14: "report force timing" will report the timing summary for the forced or defined clock signal.
mantle[11]:> report force timing $m
To See the mantle Report click here
Step - 15: "force wire model" will defines the design wire model to either constant or wireload model. In this
design example we are defining the wire model as a constant model using the following command.
mantle[11]:> force wire model constant $m
Step - 16: "report timing summary" will generates a timing analysis summary report for the model.
mantle[11]:> report timing summary $m
To See the mantle Report click here
Note: In general, check the timing summary report and find what is value of Worst Late Slack. If it is positive
with small integer then proceed to next step (try to make the worst late slack as either 0 or 1). If the worst late
slack is negative then make it positive by varying the timing information that is defined for the clock (Period,
Rise and Fall times). Do this until you get the positive slack (0 is preferred). Make the iterative run of the
previous three commands to get the positive slack of significant amount. The following report will give the idea
of how to achieve the significant positive slack.
To See the mantle Report click here
Step - 17: "check timing" will Checks and reports on the completeness of the timing constraints.
mantle[38]:> check timing $m
To See the mantle Report click here
Step - 18: "data flatten" will flattens the hierarchy under a model or cell.
mantle[38]:> data flatten $m
Step - 19: "run gate sweep" will Successively eliminates all unreachable cells, single-input cells, and constant
cells from the design.
mantle[38]:> run gate sweep $m
To See the mantle Report click here
Lecture 39: Logic Optimization, Floor Planing and Power Planning.
Lecture 40: Physical Optimization, Clock Design and Detailed Routing.
Note: Adding IO Pads to the chip is not explained in this tutorial.
[MAIN] NEXT>>
ASIC Design Tutorial using Magma Blast Fusion http://nptel.iitk.ac.in/courses/Webcourse-contents/IIT-MADRAS/CAD fo...
6 of 6 4/15/2014 7:54 PM