Objectives:

The objective of this experiment is to find out the characteristics of gates (Quad 2 AND,
OR and
NOT! After comp"eting this experiment #e #i"" $no#%
&! About the AND, OR and NOT gates!
2! About the operation of AND, OR and NOT gates!
'! The characteristics of AND, OR and NOT gates!
(! About the truth tab"e of AND, OR and NOT gates!
)! About the *oo"ean +xpression of AND, OR and NOT gates!
,! -e #i"" $no# the .ogic s/mbo" of AND, OR and NOT gates!
0! -e #i"" $no# the 1+++ s/mbo" of AND, OR and NOT gates!
2! -e #i"" $no# the function diagram (circuit diagram of AND, OR and NOT gates!

Theory:

Gate: The e"ement #hich performs "ogic function is ca""ed "ogic gate!

74LS32 (Quad 2 OR):

The 3OR4 gate is a circuit #hich #i"" give a high output if one input is high!
.ogic s/mbo"%
This OR gate has t#o
inputs and one output
termina"!

I Sy!bo":



5ig% 1+++ 6/mbo" of OR
gate!

5ig% 5unction Diagram of 0(.6'2 (Quad 2 OR
Objectives:

The objective of this experiment is to find out the characteristics of gates (Quad 2
NAND, 78OR, NOR! After comp"eting this experiment #e #i"" $no#%
&! About the NAND, 78OR, NAND, NOR gates!
2! About the operation of NAND, 78OR, NOR gates!
'! The characteristics of NAND, 78OR , NOR gates!
(! About the truth tab"e of NAND, 78OR, NOR gates!
)! About the *oo"ean +xpression of NAND, 78OR, NOR gates!
,! -e #i"" $no# the .ogic s/mbo" of NAND, 78OR, NOR gates!
0! -e #i"" $no# the 1+++ s/mbo" of NAND, 78OR, NOR gates!
2! -e #i"" $no# the function diagram (circuit diagram of NAND, 78OR, NOR gates!
Theory:
Gate: The e"ement #hich performs NAND "ogic function is ca""ed "ogic gate!

74LS## (Quad 2 $%$&):

The 3NAND4 gate is a circuit #hich #i"" give a "o# output if both input is high!
.ogic s/mbo"%
5ig% 6/mbo" of
NAND gate!
This NAND gate
has t#o inputs and
one output
termina"!
Truth Tab"e:
5rom this truth tab"e #e
can see that 3NAND4 gate
#i"" give a "o# (9 output
if both inputs are high!
'oo"ea( )*ressio(:
:ere Q is the output
parameter and A, * is the
input parameter!

+u(ctio(a" &ia,ra!:
5ig% 5unction Diagram of 0(.6'2 (Quad 2 NAND
5rom the function diagram of NAND 1; #e can see that the 1; has &( pin NAND
connection! <in number 0 is of NAND ground connection and pin number &( is NAND
=cc connection! <in number & and 2 is NAND input and pin number ' is output! This 1;
has ( "ogic gates inside it!

Resu"t:

This "ab i""ustrated the uses of circuits, chips, and gave a ph/sica" representation of the
digita" "ogic #hich 1 have been "earning about in c"ass! 1t taught me the uses of the
Trainer board a"ong #ith the 0(.699 #hich #e attached to the Trainer! 1t gave me a
better understanding of this chips!
-autio(:
-e have to ver/ carefu" about the pin of this chip because the/ are ver/ #ee$! A"so #e
have to carefu" about the connection of trainer board!

&iscussio(:
-e shou"d be carefu" #hen #e connect the 1c chip! -e compare the resu"t #ith the truth
tab"e and the resu"t #as the expected! There are on error occurred!
74LS./ (Quad 2 01OR):

The 378OR4 gate is a circuit #hich #i"" give a "o# output if both input is same bit!
Lo,ic sy!bo":
5ig% 6/mbo" of 78OR gate!
This 78OR gate has t#o inputs and one output termina"!

Truth Tab"e:
5rom this truth tab"e #e can see that 378OR4 gate #i"" give a high (& output if input is
same bit!
:ere Q is the output
parameter and A, * is the input
parameter!
1+++ 6>?*O.6%
+u(ctio(a" &ia,ra!:
5ig% 5unction Diagram of 0(.62, (Quad 2 78OR
5rom the function diagram of 78OR 1; #e can see that the 1; has &( pin for connection!
<in number 0 is for ground connection and pin number &( is for =cc connection! <in
number & and 2 is for input and pin number ' is output! This 1; has ( "ogic gates inside it!

Resu"t:
This "ab i""ustrated the uses of circuits, chips, and gave a ph/sica" representation of the
digita" "ogic #hich 1 have been "earning about in c"ass! 1t taught me the uses of the
Trainer board a"ong #ith the 0(.62, #hich #e attached to the Trainer! 1t gave me a
better understanding of this chips!
74LS#2 (Quad 2 $OR):

The 3NOR4 gate is a circuit #hich #i"" give a high output if both inputs are "o#!
Lo,ic sy!bo":
5ig% 6/mbo" of OR gate!
This NOR gate has t#o inputs and one output termina"!
1+++ 6>?*O.6%
Truth Tab"e:
5rom this
truth tab"e
#e can see
that 3NOR4
gate #i""
give a high
(& output if
both inputs
are "o#
!
'oo"ea(
)*ressio(:
:ere Q is
the output
parameter
and A, * is
the input
parameter!
+u(ctio(a" &ia,ra!:
5ig% 5unction Diagram of 0(.692 (Quad 2 NOR
5rom the function diagram of OR 1; #e can see that the 1; has &( pin for connection! <in
number 0 is for ground connection and pin number &( is for =cc connection! <in number
& and 2 is for input and pin number ' is output! This 1; has ( "ogic gates inside it!

Resu"t:
This "ab i""ustrated the uses of circuits, chips, and gave a ph/sica" representation of the
digita" "ogic #hich 1 have been "earning about in c"ass! 1t taught me the uses of the
Trainer board a"ong #ith the 0(.692 #hich #e attached to the Trainer! 1t gave me a
better understanding of this chips!
-autio(:
-e have to ver/ carefu" about the pin of this chip because the/ are ver/ #ee$! A"so #e
have to
carefu" about the connection of trainer board!

&iscussio(:
-e shou"d be carefu" #hen #e connect the 1c chip! -e compare the resu"t #ith the truth
tab"e
and the resu"t #as the expected! There are on error occurred!
Objectives:

The objective of this experiment is to find out the characteristics of gates (Quad '
NAND, AND! After comp"eting this experiment #e #i"" $no#%
&! About the NAND, AND gates!
2! About the operation of NAND, AND gates!
'! The characteristics of NAND, AND gates!
(! About the truth tab"e of NAND, AND gates!
)! About the *oo"ean +xpression of NAND, AND gates!
,! -e #i"" $no# the .ogic s/mbo" of NAND, AND gates!
0! -e #i"" $no# the 1+++ s/mbo" of ANAND, AND gates!
2! -e #i"" $no# the function diagram (circuit diagram of NAND, AND gates!
74LS2# (Quad 3 $%$&):
The 3NAND4 gate is a circuit #hich #i"" give a "o# output if a"" inputs are high!
Lo,ic sy!bo":
5ig%
6/mbo" of
'8input
NAND
gate!
This
NAND gate has three inputs and one output termina"!
Truth Tab"e:
5rom this truth tab"e #e can see that 3NAND4 gate #i"" give a "o# (9 output if three
inputs are high!
'oo"ea( )*ressio(:
:ere Q is the output parameter
and A, *, ; is the input parameter!
+u(ctio(a" &ia,ra!:
5ig% 5unction Diagram of 0(.6&9 (Quad ' AND
5rom the function diagram of OR 1; #e can see that the 1; has &( pin for connection! <in
number 0 is for ground connection and pin number &( is for =cc connection! <in number
&, 2 and &' is for input and pin number &2 is output! This 1; has ' "ogic gates inside it!
Resu"t:
This "ab i""ustrated the uses of circuits, chips, and gave a ph/sica" representation of the
digita" "ogic #hich 1 have been "earning about in c"ass! 1t taught me the uses of the
Trainer board a"ong #ith the 0(.6&9 #hich #e attached to the Trainer! 1t gave me a
better understanding of this chips!
74LS22 (Quad 3 %$&):
The 3AND4 gate is a circuit #hich #i"" give a "o# output if a"" inputs are high!
Lo,ic sy!bo":
5ig% 6/mbo"
of AND gate!
This AND
gate has three inputs and
one output termina"!
Truth Tab"e:
5rom this truth tab"e #e
can see that 3AND4 gate
#i"" give a high (& output
if a"" inputs are high!
'oo"ea( )*ressio(:
:ere Q is the output
parameter and A, *,; is
the input parameter!
+u(ctio(a" &ia,ra!:
5ig%
5unction
Diagram of
0(.6&&
(Quad '
AND
5rom the
function
diagram of
OR 1; #e
can see that
the 1; has
&( pin for
connection!
<in
number 0 is for ground connection and pin number &( is for =cc connection! <in number
&, 2 and &' is for input and pin number &2 is output! This 1; has ' "ogic gates inside it!

Resu"t:

This "ab i""ustrated the uses of circuits, chips, and gave a ph/sica" representation of the
digita" "ogic #hich 1 have been "earning about in c"ass! 1t taught me the uses of the
Trainer board a"ong #ith the 0(.6&& #hich #e attached to the Trainer! 1t gave me a better
understanding of this chips!
Objectives:

The objective of this experiment is to find out the imp"ementation of 78NOR operation
using basic gates!
Theory:
The +xc"usive8NOR @ate function or +x8NOR for short, is a digita" "ogic gate that is the
reverse or comp"ementar/ form of the +xc"usive8OR function #e "oo$ at in the previous
tutoria"! *asica""/ the A+xc"usive8NOR @ateB is a combination of the +xc"usive8OR gate
and the NOT gate but has a truth tab"e simi"ar to the standard NOR gate in that it has an
output that is norma""/ at "ogic "eve" A&C and goes A.O-B to "ogic "eve" A9C #hen AN>
of its inputs are at "ogic "eve" A&C!
:o#ever, an output A&C is on"/ obtained if *OT: of its inputs are at the same "ogic "eve",
either binar/ A&C or A9C! 5or examp"e, A99C or A&&C! This input combination #ou"d then
give us the *oo"ean expression of%
Si!*"i3ied 4uatio(:
Truth Tab"e:
-ircuit &ia,ra!:
%**aratus:
&! 0(.6'2 (& piece
2!0(.692 (& piece
'! 0(.69( (& piece
(! ;onnecting -ire
)! *read *oard etc!
Resu"t :
This "ab i""ustrated the uses of circuits, chips, and gave a ph/sica" representation of the
digita" "ogic #hich 1 have been "earning about in c"ass! 1t taught me the uses of the
Trainer board a"ong #ith the 1;s #hich #e attached to the Trainer! 1t gave me a better
understanding of this chips!
?atch the resu"t #ith corresponding truth tab"e!
6tud/ of universa"it/ of NAND D NOR gates
Objectives:
1mp"ements basic gates #ith universa" gates!
he objectives of this "esson are to "earn about%
&! Eniversa" gates 8 NAND and NOR!
2! :o# to imp"ement NOT, AND, and OR gate using NAND gates on"/!
'! :o# to imp"ement NOT, AND, and OR gate using NOR gates on"/!
(! +Fuiva"ent gates!
)! T#o8"eve" digita" circuit imp"ementations using universa" gates on"/!
,! T#o8"eve" digita" circuit imp"ementations using other gates!
Theory:
-e have discussed about different t/pes of "ogic gates in previous artic"es! No# coming
to the topic of this artic"e #e are going to discuss about the Eniversa" @ate! AND, NOT
and OR gates are the basic gatesG #e can create an/ "ogic gate or an/ *oo"ean expression
b/ combining them! No# NOR and NAND gates have the particu"ar propert/ that an/
one of them can create an/ "ogica" *oo"ean expression if designed in a proper #a/! No#
#e #i"" "oo$ at the operation of each gate separate"/ as universa" gates!
$OR Gate as a 5(iversa" Gate
The NOR gate is a"so used as a Eniversa" @ate as the NOR @ate can be used in a
combination to perform the function of a AND, OR and NOT gates!
$OT Gate I!*"e!e(tatio(
A NOT gate can be imp"emented using a NOR gate b/ connecting both the inputs of the
NOR gate together! */ connecting the t#o inputs together, the combinations #ith
dissimi"ar inputs become redundant! The 5unction Tab"e of the 28input NOR @ate reduces
to that of the NOT gate!
OR Gate I!*"e!e(tatio(
A NOR @ate performs the OR8NOT function! Removing the NOT gate at the output of
the NOR gate resu"ts in an OR gate! The effect of the NOT gate at the output of the NOR
gate can be cance"ed b/ connecting a NOT gate at the output of the NOR @ate! The t#o
NOT gates cance" each other out! A NOT @ate imp"emented using a NOR gate (2 is
connected to the output of a NOR gate (&!
%$& Gate I!*"e!e(tatio(
An AND @ate can be imp"emented using a combination of three NOR gates! The
imp"ementation is based on the a"ternate s/mbo"ic representation of the AND gate! The
AND gate is represented as an OR gate #ith bubb"es at the inputs and outputs! The t#o
bubb"es at the input can be rep"aced b/ t#o NOT gates (& D (2 imp"emented using t#o
NOR gates! 1f the t#o bubb"es are removed from the t#o inputs, the OR gate #ith the
bubb"e at the output represents a NOR gate ('!
$%$& Gate as a 5(iversa" Gate
The NOR gate is a"so used as a Eniversa" @ate as the NOR @ate can be used in a
combination to perform the function of a AND, OR and NOT gates!
$OT Gate I!*"e!e(tatio(
This is the circuit diagram of a NAND gate used to ma$e #or$ "i$e a NOT gate, the
origina" "ogic gate diagram of NOT gate is given beside!
OR Gate I!*"e!e(tatio(
The above diagram is of an OR gate made from combinations of NAND gates, arranged
in a proper manner! The truth tab"e of an OR gate is a"so given beside the diagram! No#
#e #i"" see the design of an AND gate from NAND gates!
%$& Gate I!*"e!e(tatio(
The above diagram is of an AND gate made from NAND gate! 6o #e can see that a"" the
three basic gates can be made b/ on"/ using NAND gates, that4s #h/ this gate is ca""ed
Eniversa" @ate and it is appropriate!
Resu"t:
This "ab i""ustrated the uses of circuits, chips, and gave a ph/sica" representation of the
digita" "ogic #hich 1 have been "earning about in c"ass! 1t taught me the uses of the
Trainer board a"ong #ith the 0(.699 #hich #e attached to the Trainer! 1t gave me a
better understanding of this chips!
?atch the resu"t #ith truth tab"e!
To design and imp"ementation of parit/ generator and parit/ chec$er
Theory:
6arity Ge(eratio( a(d -hec7i(,:
A parit/ bit is used for the purpose of detecting errors during transmission of binar/
information! A parit/ bit is an extra bit inc"uded #ith a binar/ message to ma$e the
number of &4s either odd or even! The message inc"uding the parit/ bit is transmitted and
then chec$ed at the receiving end for errors! An error is detected if the chec$ed parit/
does not correspond #ith the one transmitted! The circuit that generates the parit/ bit in
the transmitter is ca""ed a parit/ generator and the circuit that chec$s the parit/ in the
receiver is ca""ed a parit/ chec$er!
1n even parit/ the added parit/ bit #i"" ma$e the tota" number of &4s an even amount and
in odd parit/ the added parit/ bit #i"" ma$e the tota" number of &4s an odd amount!
1n a three bit odd parit/ generator the three bits in the message together #ith the parit/ bit
are transmitted to their destination, #here the/ are app"ied to the parit/ chec$er circuit!
The parit/ chec$er circuit chec$s for possib"e errors in the transmission!
6ince the information #as transmitted #ith odd parit/ the four bits received must have an
odd number of &4s! An error occurs during the transmission if the four bits received have
an even number of &4s, indicating that one bit has changed during transmission! The
output of the parit/ chec$er is denoted b/ <+; (parit/ error chec$ and it #i"" be eFua" to
& if an error occurs, i!e!, if the four bits received has an even number of &4s!

The circuit that generates the parit/ bit at the transmitter side is ca""ed a parit/ generator!
The circuit that chec$s the parit/ at the receiver side is ca""ed a parit/ chec$er!
The three bits, 7, >, and H,
constitute the message and
are the inputs to the even parit/
generator circuit #hose output is the parit/ bit <!
5or even parit/, #henever the message bits (7, >D H have an odd number of &4s, the
parit/ bit < must be &! Other#ise, < must be 9!
Therefore, < can be expressed as a three8variab"e exc"usive8OR function%
< I 7 > H
RS5LT:
The design of the three bit even <arit/ generator and chec$er circuits #as done and their
truth tab"es #ere verified!