EXPER

Name of


Roll No.


Date of E


Report S




Marks O

Remark

Signatur


USM


DEP






RIMENT
f Student: __
: _________
Experiment
Submitted o
Obtained
s if any
re
MAN IN
H
PARTMEN
V







T # 03: Bui
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__________
t
on



STITUT
HAMDAR
NT OF EL
VLSI DES
SPR





ilding Comb
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: _____
: _____
: _____
: _____
: _____
TE OF T
RD UNIV
LECTRICA
SIGN (EE
RING-201





binational Lo
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______Grou
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TECHNO
VERSITY
AL ENGIN
E-411)
4






ogic Circuits
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up:________
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OLOGY
Y
NEERING

Engr. Z
Engr. K
Engr. S
Engr. S
s Using Gate
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Zohaib Jawa
Kashif Ali Ar
S. Aimen Nas
Sameer Ahm
e Level Mode
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aid
rshad
seem
med
eling
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COMBIN

In digital
logic) is
where the
combinat
outputs f

The outp
current in
and any c
output. In
the comb
combinat



GATE L

Verilog






NATION L
l circuit theo
a type of dig
e output is a
tional logic c
from certain
puts of Comb
nput state, lo
changes to th
n other word
bination of it
tional circuit
LEVEL MO
code using g
LOGIC CIR
ory, combina
gital logic wh
a pure functio
circuits. Com
inputs.
binational L
ogic "0" or lo
he signals be
ds, in a Comb
ts inputs and
ts have "no m
ODELING O
gate level mo
RCUITS:
ational logic
hich is imple
on of the pre
mbinational
Logic Circuit
ogic "1", at a
eing applied
binational L
d if one of its
memory" or
OF COMBIN
odeling for t
c (sometime
emented by
esent input o
logic is used
ts are only de
any given in
to their inpu
Logic Circuit
s inputs cond
"feedback l


NATIONAL
the Combina


s also referre
various com
only. Memor
d to build cir
etermined by
nstant in time
uts will imm
t, the output
dition chang
oops".
L LOGIC C
ational Logic
ed to as time
mbinations of
ry option is n
rcuits that pr
y the logical
e as they hav
mediately hav
is dependen
es state so d
CIRCUITS:
c Circuit is s
e-independe
f logic gates
not available
roduce speci
l function of
ve no feedba
ve an effect a
nt at all times
does the outp

:
show below:

ent
,
e in
fied
f their
ack,
at the
s on
put as



LAB TASKS:

1. Write Gate Level verilog module of the following circuits shown below:
(a)
(b)

2. Write Gate Level verilog module of the following Boolean expressions shown below:
(a)
(b)
3. Design a circuit that could give a complete control mechanism for the automatic home
overhead water filling system. The system must check if the upper tank is empty, if water lies in
the lower tank it would turn on the motor for the duration till either the upper tank is filled or the
lower tank gets empty. The tanks status and motor status must be represented by LEDs.
Write the verilog Gate Level module for the following logic, also write the test bench to verify
the output and implement this logic on trainer.