STUDY OF OP-AMP

An operational amplifier or op-amp is a linear integrated circuit that has a very high voltage
gain, high input impedance and low output impedance. Op-amp is basically a differential amplifier
whose basic function is to amplify the difference between two input signals.
Op-amp has five basic terminals, that is, two input terminals, one o/p terminal and two power
supply terminals. Pin2 is called the inverting input terminal and it gives opposite polarity at the output
if a signal is applied to it. It produces a phase shift of !"
o
between input and output. Pin# is called the
non-inverting terminal that amplifies the input signal without inversion, i.e., there is no phase shift or
i/p is in phase with o/p. $he op-amp usually amplifies the difference between the voltages applied to
its two input terminals. $wo further terminals pins % and & are provided for the connection of positive
and negative power supply voltages respectively. $erminals and ' are used for dc offset. $he pin !
mar(ed )* indicates +)o *onnection,.
S t u d y o f o p - a m p
B l o c k s c h e m a t i c o f o p - a m p

2
&
#
-
%
!
) o n I n v e r t i n g
i / p
) / *
O / p
.
/
O f f s e t ) u l l
'
O f f s e t ) u l l
I n v e r t i n g i / p
.
-
I C ! "
0 i f f
a m p
0 i f f
a m p
1 u f f e r 2 l e v e l
t r a n s l a t o r
O / p
d r i v e r
/
-
. 2
.
. "
$he bloc( diagram of op-amp shows two difference amplifiers, a buffer for less loading, a level
translator for ad3usting operating point to original level and o/p stage. An ideal op-amp should have the
following characteristics4
. Infinite bandwidth
2. Infinite input resistance
#. Infinite open loop gain
&. 5ero output resistance
'. 5ero offset.
Op-amps have two operating configurations6 open loop and closed loop. In open loop
configuration, it can operate as a switch but gain is uncontrolled. In closed loop configuration, gain can
controlled by feed bac( resistance 7
f
and input resistance 7
in
.

#$%&o'
D#SI(& A&D T#STI&( OF I&)#*TI&(+ &O&-I&)#*TI&( A&D
DIFF#*#&TIA, AMP,IFI#*S
Aim'
$o design Inverting, )on-inverting and differential amplifiers using op-amp and test its
performance.
Appa-atus -e.ui-ed'
S%&o Compo/e/ts *a/0e 1ua/tity
. Op-amp I* %&
2. 0ual trace supply 8"-#"9 .
#. :unction ;enerator 8"-9 <=>
&. 7esistors
'. *apacitors
- *7O 8"-#"9 <=>
a2 I/3e-ti/0 amplifie-' 4Closed ,oop Co/fi0u-atio/5
Desi0/'
A
*?
@ .
o
/.
in
@ - 7
f
/ 7
in
6
Assume A
*?
@ 2"
=> - 7
f
/ 7
in
@ -2"
)ow Assume 7
f
@ 22(; => 7
in
@ .( 1(

Ci-cuit Dia0-am'
Model (-aph'
2
CRO
+
~
+

+12V
7
6
4
v
0
-12V
R
f
= 22k
IC741
2
3
R
in
= 1k
F.G
(V)
V
in
V
o
(V)
t(sec)
t(sec)
Inverting amp
62 &o/ i/3e-ti/0 amplifie-' 4Closed ,oop Co/fi0u-atio/5
Desi0/'
A
*?
@ .
o
/ .
in
@ / 7
f
/ 7
in6
Assume A
*?
@ "6
=> " @ / 7
f
/ 7
in

Assume 7
f
@ "(;
=> 7
in
@ .( 1(
Ci-cuit Dia0-am

Model (-aph'
#
CRO
+
~
+

+12V
7
6
4
v
0
-12V
2
3
F.G
R
in
= 1k
Rf = 10k
(V)
V
in
V
o
(V)
t(sec)
t(sec)
Non-Inverting amp
62 Diffe-e/tial Amplifie-' 4Closed ,oop Co/fi0u-atio/5
IC741
7
4
6
2
3
R1 = 1k
R1=1k
R2=10k
R2=10k
D
M
M
V1
V2
+12V
-12V
*esult'
$hus Inverting, )on-inverting and 0ifferential amplifier using op-amp was designed and
tested.
&
#$%&o'
D#SI(& A&D T#STI&( OF I&T#(*ATO* A&D DIFF#*#&TIATO*
Aim'
$o design Integrator and 0ifferentiator using op-amp and test its performance.
Appa-atus -e.ui-ed'
S%&o Compo/e/ts *a/0e 1ua/tity
. Op-amp I* %&
2. 0ual trace supply 8"-#"9 .
#. :unction ;enerator 8"-9 <=>
&. 7esistors
'. *apacitors
- *7O 8"-#"9 <=>
a2 Diffe-e/tiato-'
Desi0/'
Atep4 Aelect f
a
eBual to the highest freBuency of the input signal to be differentiated. $hen
assuming a value of *

C :. *alculate the value of 7

f
.
Atep24 *hoose f
b
@ 2" f
a
and calculate the values of 7

and *
f
so that 7

@ 7
f
*
f
.
f
a
@ D=> 6 f
b
@ D=> 6*

@ ". Ef6 7
*O<P
@ 7
f
6 7
?
@ "DF
f
a
@ / G2H7
f
*

I6 7
f
@ /2H *

f
a
6 f
b
@ / G2H7

I67

@ /2H *

f
b6
7

@ 7
f
*
f
6 *
f
@ 7*/ 7
f

Ci-cuit Dia0-am

'
*f @ ".":
* @ ".:
R1 = 1.5k Rf = 15k
Vin
RL
R1
+12V
-12V
Cf
Rf
Vo = -Rf C1[dVin/dt]
Rcomp
C1
+
-
IC 741
3
2
6
7
4
0
O6se-3atio/'
:or sine wave input4
Pea( to pea( amplitude of the input @ volts.
:reBuency of the input @ =>
Pea( to pea( amplitude of the output @ volts.
:reBuency of the output @ =>
:or sBuare wave input4
Pea( to pea( amplitude of the input @ volts.
:reBuency of the input @ =>
Pea( to pea( amplitude of the output @ volts.
:reBuency of the output @ =>

Model (-aph'
62 I/te0-ato-'
Desi0/'
;enerally the value of the f
a
and in turn 7

*
f
and 7
f
*
f
values should be selected such that f
a
C f
b
. :rom
the freBuency response we can observe that f
a
is the freBuency at which the gain is " db and f
b
is the
freBuency at which the gain is limited. <aJimum input signal freBuency @ D=>.
*ondition is time period of the input signal is larger than or eBual to 7
f
*
f
8i.e.9 $
f
7 *
f
b
@ D=> 6 f
a
@ f
b
/"6 7
f
@ "7

6 7
*O<P
@ 7
6
7
? 2
7

@ "DF
f
a
@ / G2H7
f
*
f
I6 7f

*
f
@ msec 26 *f @ msec/""D
-
I V
V i n
V o
t
t
- I V
M o d e l g r a p h
2 V
- 2 V
I V
V i n
V o
t
t
- I V
M o d e l g r a p h
Ci-cuit Dia0-am'
O6se-3atio/'
:or sine wave input4
Pea( to pea( amplitude of the input @ volts.
:reBuency of the input @ =>
Pea( to pea( amplitude of the output @ volts.
:reBuency of the output @ =>
:or sBuare wave input4
Pea( to pea( amplitude of the input @ volts.
:reBuency of the input @ =>
Pea( to pea( amplitude of the output @ volts.
:reBuency of the output @ =>
Model (-aph'

*esult'
$hus Integrator and 0ifferentiator using op-amp was designed and tested.
%
V i n
V o
t
t
M o d e l g r a p h
t
t
.
O
@ - G/7

*
f
I K.in dt
Vin
RL
+12V
-12V
Rcomp = Rf
+
-
IC 741
3
2
6
7
4
0
R1

= 1.5k *
f
@ ".:
Rf

= 15M
A%&
#$%&o'
D#SI(& A&D T#STI&( OF I&ST*UM#&TATIO& AMP,IFI#*
AIM'
$o design and test the operation of Instrumentation Amplifier for various gain
values.
IC741
7
4
6
2
3
100k
100k
100k
3
100k
D
M
M
+12V
-12V
IC741
7
4
6
2
3
100k
V1
V2
+12V
-12V
IC741
7
4
6
2
3
470k
+12V
-12V
470k
APPA*ATUS *#1UI*#D '
i. I* %& L # )O.
ii. 7esistors
iii. 7PA, 0<<
T7#O*Y '
Instrumentation amplifier is an amplifier that reali>es high input impedance
and very low offset and drift voltage values. $his configuration is better than inverting or
non-inverting amplifier because it has minimum non-linearity, stable voltage gain and
high *<77 8 M "" d1.9. $his type of amplifier is used in thermocouples, strain gauges
and biomedical probes.
Output voltage
P*OC#DU*#'
8i9 *onnect the instrumentation amplifier circuit.
8ii9 :or various input voltage . and .2 measure and record the output voltage and
tabulate.
!
*#SU,T' $hus the instrumentation amplifier is designed, constructed and tested
N
OJ. )o
Asta6le a/d Mo/osta6le Multi3i6-ato-s usi/0 op-amp
Aim
$o design Astable and monostable <ultivibrators 2 Achimitt $rigger using op-amp and to plot
its waveforms.
Appa-atus *e.ui-ed'
A.)o *omponent 7ange Puantity
. Op amp I* %&
2. 0$A 8"-#"9 .
#. *7O
&. 7esistor
'. *apacitors L L
-. 0iode I)&"" 2
%. Probes L
Desi0/'
"% Mo/osta6le Multi3i6-ato-s'
Q @ 7
2
/7

/7
2
GQ @ ".' 2 7

@ " DI
:ind 7
2
@ 6 7# @ D6 7& @ "D6
?et : @RRRRRD=> 6 *@ mfd6 *& @ ".mfd
Pulse width, $ @ ".-N7*
:ind 7 @
Ci-cuit Dia0-am

"
C R O
+

+ 1 0 V
7
4
- 1 0 V
2
3
I C 7 4 1
R
V s a t
C 4 D 2
R 4
D 1
C
V C
6
R 3
V O
R 1
R 2
V i n
Model 0-aph'
P-ocedu-e'
. <a(e the connections as shown in circuit diagram.
2. A trigger pulse is given through differentiator circuit through pin no.#
#. Observe the pulse waveform at pin no.- using *7O and note down the time period.
&. Plot the waveform on the graph.
8% Asta6le Multi3i6-ato-s'
Desi0/'
$ @ 27*
7

@ .- 7
2
;iven f
O
@ RRRRRRRD=>
:reBuency of Oscillation fo @ / 2 7* if 7

@ .-7
2

?et 7
2
@ " D
7

@ " 1.16 = 11.6
?et * @ "."' :
7 @ / 2 f* @ / 82 1 10
3
0.05 10
6
) =

V i n
V C
V O
V s a t
V s a t
V D
t
t
t
T
V s a t
T P
Ci-cuit Dia0-am
Model 0-aph

V o l t a ! i n " o l t #
V o l t a ! a c $ o # # t % ! c a p a c i t o $
t & m # ! '
" o
P-ocedu-e'
. <a(e the connections as shown in the circuit diagram
2. Deep the *7O channel switch in ground and ad3ust the hori>ontal line on the J aJis so that it
coincides with the central line.
#. Aelect the suitable voltage sensitivity and time base on the *7O.
&. *hec( for the correct polarity of the supply voltage to op-amp and switch on power supply to
the circuit.
'. Observe the waveform at the output and across the capacitor. <easure the freBuency of
oscillation and the amplitude. *ompare with the designed value.
-. Plot the Saveform on the graph.
2
2
+ 1 0 V
I C 7 4 1
R
+
C R O
C
3
1 0 V
1 0
R 1
R 2
1 1 . 6
V O
4
7

6
1 0 k
0 . 0 5 f
1uestio/s'
. Shat is other name for Astable <ultivibratorsT
2. =ow an Op-amp is used to generate sBuare waveT
#. Shat are the changes to be done in a symmetric sBuare wave generator to generate asymmetric
sBuare waveT
92 Schmitt T-i00e-'
Desi0/
.
**
@ 2 .6 .
AA$
@ ".N .
**
: 7@ &%DF6 72 @ 2"F
.
U$
@ / G.
AA$
7
2
I / G7

/7
2
I 2 .
?$
@ - G.
AA$
7
2
I / G7

/7
2
I 2 =VA$O7AIA G=I @ .
U$
- .
?$

Ci-cuit Dia0-am
Model (-aph
P-ocedu-e
. *onnect the circuit as shown in the circuit
2. Aet the input voltage as '. 8p-p9 at D=>. 8Input should be always less than .
cc
9
#. )ote down the output voltage at *7O
#
V i n
+ 1 2 V
R 1
- 1 2 V
R 2
0
+
-
3
2
6
7
4
R L = 1 0 (
&. $o observe the phase difference between the input and the output, set the *7O in dual <ode
and switch the trigger source in *7O to *=I.
'. Plot the input and output waveforms on the graph.
O6se-3atio/'
Pea( to pea( amplitude of the output @ .olts.
:reBuency @ =>.
Upper threshold voltage @ .olts.
?ower threshold voltage @ .olts.
)i3a 1uestio/s'
. Shat is =ysteresisT Shat parameter determines =ysteresisT
2. =ow would you recogni>e that positive feedbac( is being used in the Op-amp circuitT
#. Shat do you mean by upper and lower threshold voltage in Achmitt $riggerT
&. Shat is the difference between a basic comparator and the Achmitt triggerT
'. Shat is a sample and hold circuitT Shy is it neededT
-. Shat is a voltage limiting, and why is it neededT
%. Shat is the name of the circuit that is used to detect the pea( value of the )onsinusoidal input
waveformsT
!. =ow will you produce, definite =ysteris in a Achmitt trigger using op-ampT
*esult'
$hus Astable 2 <onostable <ultivibrators and Achimitt trigger were designed using op-amp
and the waveforms were plotted.
&
#$P%&O'
MU,TI)IB*ATO*S USI&( IC ;;;
Aim'
$o design and test an Astable and <onostable <ultivibrators using ''' timer with duty cycles
ratio.

Appa-atus *e.ui-ed'
S%&o Compo/e/t *a/0e 1ua/tity
. ''' $I<O7
2. 7esistors #.#D, -.!(
#. *apacitors ". :, "." : 2
&. 0iode In&""
'. *7O
-. Power supply
15 V

%. Probe 2
!. 1read 1oard
Asta6le Multi3i6-ato-s usi/0 ;;;
:ig shows the ''' timer connected as an Astable <ultivibrators. Initially, when the output is
high. *apacitor * starts charging towards .
cc
through 7
A
and 7
1
. As soon as capacitor voltage eBuals
2/# .
cc
upper comparator 8U*9 triggers the flip flop and the output switches low. )ow capacitor *
starts discharging through 7
1
and transistor P

.
Shen the voltage across * eBuals /# .
cc
lower comparator 8?*9, output triggers the flip-flop
and the output goes high. $hen the cycle repeats.
$he capacitor is periodically charged and discharged between 2/# .
cc
and /# .
cc
respectively.
$he time during which the capacitor charges form /# .
cc
to 2/# .
cc
is eBual to the time the output is
high and is given by
$
c
@ ".-N87
A
/7
1
9* 89
Shere 7
A
and 7
1
are in Ohms and * is in farads. Aimilarly the time during which the capacitor
discharges from 2/# .
cc
to /# .
cc
is eBual to the time the output is low and is given by
$
d
@ ".-N 7
1
* 829
'
$he total period of the output waveform is
T < T
c
= T
d
< >%?@ A*
A
= 8*
B
2 C 8#9
$he freBuency of oscillation
f
o
@

/ $ @.&' / 87
A
/27
1
9* 8&9
OBn 8&9 shows that fo is independent of supply voltage .cc
$he duty cycle is the ratio of the time t
d
during which the output is low to the total time period
$. $his definition is applicable to ''' Astable <ultivibrators only6 conventionally the duty cycle ratio
is defined as the ratio as the time during which the output is high to the total time period.
0uty cycle < t
d
$ 100
7
1
/ 7
A
/ 27
1
100 (5)
obtain '"% duty cycle a diode should be connected across 7
1
and 7
A
must be a
combination of a fiJed resistor and a potentiometer. Ao that the potentiometer can be ad3usted for the
eJact sBuare waves
D#SI(&'
0esign an Astable <ultivibrators for a freBuency of RRRRRRD=> with a duty cycle ratio of
0 @ '" %
fo < "BT < "%!; B A*
A
=8*
B
2C
*hoosing * @ :6 7
A
@ '-"
0 @ 7
1
/ 7
A
/27
1
@ ".' G'"WI
7
1
@ RRRRRR
Pi/ dia0-am'

-
V C C
D i s ! " a # $ %
T " # % s " & ' (
C & n t # & ' V & ' t a $ %
T # i $ $ % #
O ) t * ) t
R % s % t
G # & ) n (
+ + + +
Ci-cuit Dia0-am
Model (-aph
%
V !
t , - s .
V / T
V / T
t " i $ "
t ' & 0
t , - s .
V O
V O D
R 1
6 . 2 k
V ! !
+ + V
0 . 0 1 F
0 . 1 F
R 3
3 . 3 k
7
2
6
1 +
2 4
3
+ + + +
P-ocedu-e'
. 7ig-up the circuit of ''' Astable <ultivibrators as shown in fig with the designed value of
components.
2. *onnect the *7O probes to pin # and 2 to display the output signal and the voltage across the
timing capacitor. Aet suitable voltage sensitively and time-base on the *7O.
#. Awitch on the power supply to *7O and the circuit.
&. Observe the waveforms on the *7O and draw to scale on a graph sheet. <easure the voltage
levels at which the capacitor starts charging and discharging, output high and low timings and
freBuency.
'. Awitch off the power supply. *onnect a diode across 7
1
as shown in dashed lines in fig to
ma(e the Astable with '" % duty cycle ratio. Awitch on the power supply. Observe the output
waveform. 0raw to scale on a graph sheet.
Mo/osta6le Multi3i6-ato-s usi/0 ;;;
<onostable <ultivibrators has one stable state and other is a Buasi stable state. $he circuit is
useful for generating single output pulse at ad3ustable time duration in response to a triggering signal.
$he width of the output pulse depends only on eJternal components, resistor and a capacitor.
$he stable state is the output low and Buasi stable state is the output high. In the stable state
transistor P is +on, and capacitor * is shorted out to ground. =owever upon application of a negative
trigger pulse to pin2, P is turned +off, which releases the short circuit across the eJternal capacitor *
and drives the output high. $he capacitor * now starts charging up towards .
cc
through 7
A
. =owever
when the voltage across * eBual 2/# .
cc
the upper comparator output switches form low to high which
in turn drives the output to its low state via the output of the flip flop. At the same time the output of
the flip flop turns P +on, and hence * rapidly discharges through the transistor. $he output remains
low until a trigger is again applied. $hen the cycle repeats.
$he pulse width of the trigger input must be smaller than the eJpected pulse width of the
output. $he trigger pulse must be of negative going signal with amplitude larger than /# .cc. $he
width of the output pulse is given by,
$ @ . 7
A
*
!
Desi0/'
;iven a pulse width of duration of "" s
?et * @ "." mfd6 : @ RRRRRRRRRD=>
=ere, $@ . 7
A
*
Ao, 7
A
@
Ci-cuit Dia0-am'

Model Dia0-am'
N
V O
R 1
1 0 k
V ! !
+ + V
0 . 0 1 F
0 . 1 F
7
6
1 +
2 4
3
+ + +
2
T # i $ $ % # i 4 *
0 . 0 1 F
V ! !
0 V
, i . T # i $ $ % # i n * ) t
, i i . O ) t * ) t
, i i . C a * a ! i t & #
V & ' t a $ %
0 V
0 V
V ! !
P-ocedu-e'
. 7ig-up the circuit of ''' monostable <ultivibrators as shown in fig with the designed value of
components.
2. *onnect the trigger input to pin 2 of ''' timer form the function generator.
#. *onnect the *7O probes to pin # and 2 to display the output signal and the voltage across the
timing capacitor. Aet suitable voltage sensitively and time-base on the *7O.
&. Awitch on the power supply to *7O and the circuit.
'. Observe the waveforms on the *7O and draw to scale on a graph sheet. <easure the voltage
levels at which the capacitor starts charging and discharging, output high and low timings
along with trigger pulse.
1uestio/s'
. Shat are the features of ''' timerT
2. Shat are the applications of ''' timerT
#. 0efine duty cycle ratio.
&. Shat are the applications of monostable <ultivibratorsT
'. Shat is meant by Buasi stable stateT
-. Shat should be the amplitude of trigger pulseT
*esult'
$hus the Astable <ultivibrators and <onostable <ultivibrators using ''' timer is designed
and tested.
2"
#$%&o'
F*#1U#&CY *#SPO&S# OF 8
/d
O*D#* ,PF C 7PF
Aim'-
$o design and test the freBuency response of a second order ?P: and =P:.
Compo/e/ts *e.ui-ed'-
A.)o *omponents 7ange Puantity
. Op-amp I* %&
2. 7esistors
#. *apacitor O."f 2
&. *7O
'. Power Aupply X '.
-. Probe 2
%. 1read 1oard
Theo-y'-
,PF'-
A ?P: allows only low freBuency signals up to a certain brea(-point f
=
to pass through, while
suppressing high freBuency components. $he range of freBuency from " to higher cut off freBuency f
=
is called pass band and the range of freBuencies beyond f
=
is called stop band.
$he following steps are used for the design of active ?P:.
. $he value of high cut off freBuency f
=
is chosen.
2. $he value of capacitor * is selected such that its value is Y:.
#. 1y (nowing the values of f
=
and *, the value of 7 can be calculated using
RC
H
f
2

=
&. :inally the values of 7

and 7
f
are selected depending on the designed pass band gain by
using

+ =

R
f
R
A
2
Ci-cuit Dia0-am'-
Seco/d O-de- ,PF'
+ 1 0 V
+
-
L M 7 4 1 C
3
2
6
71
45
R = 7 . ) 5 k
R f = 1 0 k
R
0 . 0 1 * f
R = 7 . ) 5 k
+ * n c t i o n ! n ! $ a t o $
- 1 0 V
V o
0 . 0 1 * f
R = 1 0 k
Desi0/'-
Seco/d o-de-'-
;iven freBuency, f
=
@ 2 D=> and gain @2
?et *@"."f
$he freBuency, f
=
@

-
" " . "
#
" 2 2

Aet,
R R R = =
# 2

C C C = =
# 2

RC
H
f
2

=
Ta6ulatio/
Seco/d o-de- ,PF .in@.
A.)o :reBuency 8=>9 O/p voltage8v9 ;ain@.o/.in ;ain@2"log8.o/.in9
22
Model 0-aph'-
Seco/d o-de- 7PF'
Theo-y'-
$he high pass filter is the complement of the low pass filter. $hus the high pass filter can be
obtained by interchanging 7 and * in the circuit of low pass configuration. A high pass filter allows
only freBuencies above a certain bread point to pass through and at terminates the low freBuency
components. $he range of freBuencies beyond its lower cut off freBuency f
?
is called stop band.
Ci-cuit Dia0-am'-
Seco/d O-de- 7PF'
+
-
L M 7 4 1 C
3
2
6
71
45
+ * n c t i o n ! n ! $ a t o $
R = 1 0 k
0 . 0 1 * f
R f = 1 0 k
R
- 1 0 V
0 . 0 1 * f
R = 7 . ) 5 k R = 7 . ) 5 k
+ 1 0 V
V o
2#
Desi0/'-
9 8 "

N' . %
# 2
2

# 2
# 2
# 2
# 2 # 2
2

2 ,
" . "
2
given k R
f
R
R
f
R
A
k R R
fLC
R R
C C C
R R R Let
C C R R
L
f
Av Gain
F C
HZ
L
f
= =
= + =
= =
= =
= =
= =
=
=
=
=

D
.in@.
A.)o :reBuency 8=>9 O/p voltage8v9 ;ain@.o/.in ;ain@2"log8.o/.in9
2&
Model 0-aph'-
P-ocedu-e'-
,PF'-
. *onnections are given as per the circuit diagram.
2. Input signal is connected to the circuit from the signal generator.
#. $he input and output signals of the filter channels and 2 of the *7O are connected.
&. Auitable voltage sensitivity and time-base on *7O is selected.
'. $he correct polarity is chec(ed.
-. $he above steps are repeated for second order filter.
7PF
. *onnections are given as per the circuit diagram.
2. Input signal is connected to the circuit from the signal generator.
#. $he input and output signals of the filter channels and 2 of the *7O are connected.
&. Auitable voltage sensitivity and time-base on *7O is selected.
'. $he correct polarity is chec(ed.
-. $he above steps are repeated for second order filter.
*esult'-
$hus the second order ?ow pass filter and =igh pass filter were designed using Op-amp and its
cut off freBuency was determined.
2'
#$%&o'
F*#1#&CY *#SPO&S# OF 8
/d
O*D#* BSF C BPF
Aim'-
$o design and test the freBuency response of a second order ?P: and =P:.
Compo/e/ts *e.ui-ed'-
A.)o *omponents 7ange Puantity
. Op-amp I* %& #
2. 7esistors
#. *apacitor O."f, O."'f 2
&. *7O
'. Power Aupply X '.
-. Probe 2
%. 1read 1oard
Theo-y'-
BSF'-
1A: is the logical inverse of band pass filter which does not allows a specified range of
freBuencies to pass through. It has two pass bands in the range of freBuencies between " to f
?
and
beyond f
=
. $he band between f
?
and f
=
is called stop band. 1A: is also called 1and 7e3ect :ilter
817:9 or 1and Olimination :ilter 81O:9.
BPF'-
$he 1P: is the combination of high and low pass filters and this allows a specified range of
freBuencies to pass through. It has two stop bands in range of freBuencies between " to f
?
and beyond
f
=
. $he band b/w f
?
and f
=
is called pass band. =ence its bandwidth is 8f
?
-f
=
9. $his filter has a
maJimum gain at the resonant freBuency 8f
r9
which is defined as
L H r
f f f =
$he figure of merit 8or9 Buality factor P is given by
BW
f
f f
f
Q
r
L H
r
=

=
2-
Ci-cuit Dia0-am'-
BPF
C = 0 . 0 1
C
=
0
.
0
1
R f = 1 0
f n ! n
C = 0 . 0 1
R = 7 . ) 5
V o
R = 1 0
C
=
0
.
0
1
R = 1 0
R
=
7
.
)
5
R = 7 . ) 5
+
-
L M 7 4 1
3
2
6
71
45
R = 1 0
R = 1 0
R
=
7
.
)
5
+
-
L M 7 4 1
3
2
6
71
45
Desi0/'-
BSF'-
f
=
@2""=>
f
?
@(=>
,oE pass sectio/4-
f
=
@2""=>
?et *

@"."'f
$hen,
f C
K R
R
c f
R
H

"' . "
N . '
9 " "' . " 98 2"" 8 2

=
=

=
=

2%
7i0h Pass Sectio/'-
( )
=

=
=
=
=

N . '
" " . " " 8 2

" . "

- 9 #
R
C f
R
f C
f
L
L

;ain, Av@2 for each section

= = = = "

f f
R R R R
Model 0-aph'-
BPF'-
Ta6ulatio/'-
BPF .in@'"mv
A.)o :reBuency 8=>9 .o8volts9 ;ain@2"log8.o/.in9
2!
Ci-cuit Dia0-am'-
BSF
+
-
L M 7 4 1
3
2
6
71
45
+
-
L M 7 4 1
3
2
6
71
45
C
=
0
.
0
5
R = 1 0
C = 0 . 0 5
R = 1 5 . )
R f = 1 0
R = 1 5 . )
R
=
1
5
.
)
f n ! n
C = 0 . 0 1 C = 0 . 0 1
R
L
=
1
0
R = 1 0
R = 1 0
V o
R = 1 0
R = 3 . 3
R f = 1 0
R
=
1
5
.
)
R = 1 0
+
-
L M 7 4 1
3
2
6
71
45
Model 0-aph'-
BSF'-
2N
Ta6ulatio/'-
BSF
.in@'"mv
A.)o :reBuency 8=>9 .o8volts9 ;ain@2"log8.o/.in9
P-ocedu-e'
BSF+BPF'-
. $he input signal is connected to the circuit from the signal generator.
2. $he input and output signals are connected to the filter.
#. $he suitable voltage is selected.
&. $he correct polarity is chec(ed.
'. $he steps are repeated.
*esult'-
$hus the freBuency response of second order 1P: and 1A: filter was designed and tested.
#"
#$P%&O%'

OSCI,,ATO*S USI&( OP#*ATIO&A, AMP,IFI#*
Aim'
$o design the following sine wave oscillators
a9 Sein 1ridge Oscillator with the freBuency of D=>.
b9 7* Phase shift oscillator with the freBuency of 2"" =>.
Compo/e/ts *e.ui-ed'
S%&o Compo/e/ts *a/0e 1ua/tity
. Op-amp I* %&
2. 0ual trace supply 8"-#"9 .
#. :unction ;enerator 8"-29 <=>
&. 7esistors
'. *apacitors
- *7O 8"-#"9 <=>
% Probes -- --
#.uatio/s *elated to the #Fpe-ime/ts'
a9 Sein 1ridge Oscillator
*losed loop gain A
v
@ 8/7
f
/7

9 @ #
:reBuency of Oscillation f
a
@ /827*9
b9 7* Phase shift Oscillator4
;ain A
v
@ G7
f
/7

I @ 2N
:reBuency of oscillation f
a
@ - Z 2Z Z 7*
"2 Gei/ B-id0e Oscillato-'
Desi0/'
;ain reBuired for sustained oscillation is A
v
@ / @ #
8PAAA 1A)0 ;AI)9 8i.e.9 /7
f
/7

@ #
7
f
@ 27

:reBuency of Oscillation f
o
@ /2 7 *
;iven f
o
@ D=>
?et * @ "."' :
7 @ /2 f
o
*
7 @ #.2 D
?et 7 @ " D 7f @ 2 Z " D
#
Model (-aph'
t
+ V *
V O
V *
P-ocedu-e'
. *onnect the components as shown in the circuit '.
Ci-cuit ;%"'
C R O
+

+ 1 0 V
7
6
4
- 1 0 V
2
3
I C 5 4 1
R 1 = 1 0 k
R f = 2 0 k
3 . 2 k
R
C
0 . 0 + f
3 . 2 k R =
C 0 . 0 + f
V O
2. Awitch on the power supply and *7O.
#. )ote down the output voltage at *7O.
&. Plot the output waveform on the graph.
'. 7edesign the circuit to generate the sine wave of freBuency 2D=>.
-. *ompare the output with the theoretical value of oscillation.
O6se-3atio/'
Pea( to pea( amplitude of the output @ .olts.
:reBuency of oscillation @ =>.
#2
1uestio/s'
. Atate the two conditions for oscillations.
2. *lassify the OscillatorsT
#. 0efine an oscillatorT
&. Shat is the freBuency range generated by Sein 1ridge OscillatorT
'. Shat is freBuency stabilityT
82 *C Phase Shift Oscillato-s'
Desi0/'
:reBuency of oscillation fo @ /8-Z2ZZ7*9
Av @ G7f/7I @ 2N
7

@ " 7
7
f
@ 2N 7

;iven fo @ 2"" =>.

?et * @ ".:
( )
( )
-
7 / - Z 2 Zfo Z *
/ - Z 2Z Z 2"" Z".Z"
D
$o prevent the loading of amplifier by 7* networ(, 7 "7
7 "Z D
Aince 7f 2N7
7f 2N Z
<

=
=
=

= =
=
=
=
Model (-aph'
V O
t
##
P-ocedu-e'
. *onnect the circuits as shown in the circuit '.2
2. Awitch on the power supply.
Ci-cuit ;%8'
C R O
+

+ 1 0 V
7
6
4
- 1 0 V
2
3
I C 7 4 1
R 1
1 -
3 . 3 k
C
V O
0 . 0 1 f
C C
R R R 3 . 3 k 3 . 3 k
0 . 0 1 f
0 . 0 1 f
3 2 k
3 3 k
R f
D R 3
#. )ote down the output voltage on the *7O.
&. Plot the output waveforms on the graph.
'. 7edesign the circuit to generate the sine wave of D=>.
-. Plot the output waveform on the graph.
%. *ompare the practical value of the freBuency with the theoretical value.
O6se-3atio/'
Pea( to pea( amplitude of the sine wave @ .olts
:reBuency of Oscillation 8obtained9 @ =>.
1uestio/s'
. Shat is the freBuency range generated by 7* phase shift OscillatorT
2. In 7* phase shift oscillator how the total phase shift of !" around the loop is achievedT
*esult'
$hus wien bridge oscillator and 7* Phase shift oscillator was designed using op-amp and
tested.
#&
#$P%&O%' )O,TA(# *#(U,ATIO& USI&( IC ,M89
AIM '
$o design a high current, low voltage and high voltage linear variable dc regulated power supply
and test its line and load regulation.
COMPO&#&TS *#1UI*#D '
A.)O *O<PO)O)$A APO*I:I*A$IO) PUA)$I$V
. $ransistors $IP22,2)#"'' each
2. Integrated *ircuit ?<%2#
#. 0igital Ammeter 8 " L " 9 A
&. 0igital .oltmeter 8 " L 2" 9 .
'. .ariable Power Aupply 8 " L #" 9 .-2A
-. 7esistors
#"",&#",D,-%!D,-%!

each
2
%. *apacitors
".:,""p:
each
N. 7heostat 8 " L #'" 9
CI*CUIT DIA(*AM ' ,oE )olta0e *e0ulato-
430
1k
0.5
2N3055
Unregulated
DC Poer
!u""l# 12 11
$
5
R1
R2
V+ V%
Vo
C&
C!
'NV
C()P V-
N'
Vref
0*1
U+
,'P122
100"+
R-%
10
2
3
.
13 /
&oad
0
+ -
V
+
-
:ig. .
#'
?<%2#
D#SI(&'
Output voltage [ .
O
7eference voltage[ .ref
7protect [ <inimum 7esistance to protect the output from short circuit.
,oE )olta0e *e0ulato- '
(i3e/ ' )o<;)+ )-ef < %"; )
$o calculate 7, 72 ,7# and 7sc.
.o

@

.ref 8 72 / 8 7 / 72 9 9
' / %.' @ 8 72 / 8 7 / 72 9 9
8 7 / 72 9 ".-NN@ 72
".-NN7 @ ".#" 72 , 7 @ ".&#"- 72
Aelect *8 < " D
7 @ D Z ".&#"- @ &#"
*" < !9>
7# @ 7 Z 72 / 8 7 / 729 , 7# @ &#".- Z""" /8&#".-/""" 9
*9 < 9>>
7sc @ .
sense
/ I
limit
@ ".' /A @ ".' , *sc < >%;
CI*CUIT DIA(*AM ' 7i0h )olta0e *e0ulato- '
:ig. .2
#-
7i0h )olta0e *e0ulato- '

(i3e/ ' )o<"8)+ )-ef < %"; )
$o calculate 7, 72 ,7# and 7sc.
.o

@

.ref 8 / 87 / 729 9
2 / %.' @ / 87 / 729
82 / %.'9 - @ 87 / 729
87 / 729 @ ".-%!
Aelect *8 < " D
7 @ D Z ".-%! @ -%!
*"< ?H
7sc @ .
sense
/ I
limit
@ ".' /A @ ".'
*sc < >%;
Ta6ulatio/ of the Measu-eme/ts '
,OG )O,TA(# *#(U,ATO* '
,i/e *e0ulatio/ '
S%&o% ?oad 7esistance 7
?
@ ?oad 7esistance 7
?2
@ ?oad 7esistance 7
?#
@
Input
.oltage
.in8.olts
9
Output
.oltage
.
?
8.olts9
Input
.oltage
.in8.olts
9
Output
.oltage
.
?
8.olts9
Input
.oltage
.in8.olts
9
Output
.oltage
.
?
8.olts9
,oad *e0ulatio/ '
S%&o% Input .oltage .
in
@ Input .oltage .
in2
@ Input .oltage .
in#
@
Output
*urrent
I
?
8 A 9
Output
.oltage
.
?
8.olts9
Output
*urrent
I
?
8 A 9
Output
.oltage
.
?
8.olts9
Output
*urrent
I
?
8 A 9
Output
.oltage
.
?
8.olts9
7I(7 )O,TA(# *#(U,ATO* '
,i/e *e0ulatio/ '
S%&o% ?oad 7esistance 7
?
@ ?oad 7esistance 7
?2
@ ?oad 7esistance 7
?#
@
#%
Input
.oltage
.in8.olts
9
Output
.oltage
.
?
8.olts9
Input
.oltage
.in8.olts
9
Output
.oltage
.
?
8.olts9
Input
.oltage
.in8.olts
9
Output
.oltage
.
?
8.olts9
,oad *e0ulatio/ '
S%&o% Input .oltage .
in
@ Input .oltage .
in2
@ Input .oltage .
in#
@
Output
*urrent
I
?
8 A 9
Output
.oltage
.
?
8.olts9
Output
*urrent
I
?
8 A 9
Output
.oltage
.
?
8.olts9
Output
*urrent
I
?
8 A 9
Output
.oltage
.
?
8.olts9
Calculatio/ of I )olta0e *e0ulatio/ '
W .oltage 7egulation @ 8 .
dc
8 )? 9 - .
dc
8 :? 9 9 / .
dc
8 :? 9
.
dc
8 )? 9 @ 0.*. output voltage on no load
.
dc
8 :? 9 @ 0.*. output voltage on full load
Model (-aph '
,i/e *e0ulatio/ ' ,oad *e0ulatio/ '
I/put )olta0e )s Output )olta0e ' Output Cu--e/t )s Output )olta0e

I L
V 0 V 0
V
in
Loa, $!*lation Lin! $!*lation
P*OC#DU*# '
,OG )O,TA(# *#(U,ATO* '
,i/e *e0ulatio/ '
. ;ive the circuit connection as per the circuit diagram shown in :ig ..
2. Aet the load 7esistance to give load current of ".2'A.
#!
#. .ary the input voltage from %. to !. and note down the corresponding output voltages.
&. Aimilarly set the load current 8 I
?
9 to ".'A 2 ".NA and ma(e two more sets of measurements.
#N
,oad *e0ulatio/ '
. Aet the input voltage to "..
2. .ary the load resistance in eBual steps from #'" to ' and note down the corresponding
output voltage and load current.
#.Aimilarly set the input voltage 8 .in 9 to &. 2 !. and ma(e two more sets of measurements.
,a6 *epo-t '
.Plot the line regulation by ta(ing Input .oltage 8.in9 along \-aJis and Output .oltage 8.
?
9
along V-aJis for various load currents.
2.Plot the load regulation by ta(ing load current 8I
?
9 along \-aJis and Output .oltage 8.
?
9 along
V-aJis for various input voltages.
#.*alculate its W .oltage 7egulation using the formula.
7I(7 )O,TA(# *#(U,ATO* '
,i/e *e0ulatio/ '
.;ive the circuit connection as per the circuit diagram shown in :ig .2.
2.Aet the load 7esistance to give load current I
?
of ".2'A.
#..ary the input voltage from %. to !. and note down the corresponding output voltages.
&.Aimilarly set the load current 8 I
?
9 to ".'A 2 ".NA and ma(e two more sets of measurements.
,oad *e0ulatio/ '
. Aet the input voltage to "..
2. .ary the load resistance in eBual steps from #'" to ' and note down the corresponding
output voltage and load current.
#.Aimilarly set the input voltage 8 .in 9 to &. 2 !. and ma(e two more sets of measurements.
,a6 *epo-t '
.Plot the line regulation by ta(ing Input .oltage 8.in9 along \-aJis and Output .oltage 8.
?
9
along V-aJis for various load currents.
2.Plot the load regulation by ta(ing load current 8I
?
9 along \-aJis and Output .oltage 8.
?
9 along
V-aJis for various input voltages.
#.*alculate its W .oltage 7egulation using the formula.
*esult '
$hus the line and load regulation of a high current, low voltage and high voltage linear variable
dc regulated power supply was designed and tested.
A.)o ?ow .oltage 7egulator =igh .oltage 7egulator
W .oltage 7egulation
&"
1uestio/s '
i9 Shy minimum protect resistance in load is reBuiredT Shat will happen if it is not thereT
ii9 0id you short circuit the output and chec( whether the short circuit protection is wor(ingT
iii9 Shat will you do if you are as(ed to design both high and low voltage regulators in one circuitT
iv9 ;ive " eJample applications of the above circuitsT
v9 Shy do you use a ""p: capacitor between # 2 #,&T
&
)O,TA(# *#(U,ATIO& USI&( IC 9"
AIM'
$o design, construct and test voltage regulator using I* #%.
APPA*ATUS *#1UI*#D'
i. I* #%
ii. 7esistors, capacitors
iii. 7PA
T7#O*Y'
One of the most popular variable voltage regulators is the I* #% regulator. $he ?< #% is an
ad3ustable three terminal positive voltage regulator. $hey are capable of supplying output current of
".A to .'A, over a range of .2. to #%..
$he basic circuit connection is as shown in the diagram. $he ?< #% needs two resistors 7,
72 for setting the output voltage. Usually the input capacitor is of disc type and the output is of
electrolytic type to improve the transient response. $he unregulated input is applied at .i , which is
normally 2.
more than the reBuired output voltage.
Shen the circuit is connected as shown the value of .ref @.2'., between the output and the
ad3ustable terminals. $his voltage is dropped across 7, driving a current I@ .ref/7. Ao the net
current flowing through 72 is I/IA0]. 1ut as IA0] is very small, .O@.ref8/72/79 where the
reference voltage is .2'.
D67IG89
?et capacitors *@".u: and *2@u:.
If resistor 7@2&" ohms and if 72 @""" ohms6
$hen regulated output@.2'Z8/72/79@-.&- volts
If a variable resistor is used in the place of 72, we can get can ad3ustable output voltage.
&2
CI*CUIT DIA(*AM'
P*OC#DU*#'
i. ;ive the circuit connections as per the circuit diagram.
ii. 1y varying the input voltage observe the output voltage.
iii. )ow change the resistor values to get a different .O.
iv. Once again by varying the supply observe the output.
v. 0raw the regulation curve.
*#SU,T'
$hus the voltage regulator using ?< #% is designed, constructed and tested.
&#
F*#1U#&CY MU,TIP,I#* USI&( P,, IC
AIM'
$o study the operation of )O '-' P?? as a freBuency multiplier.
APPA*ATUS *#1UI*#D'
i. 7PA
ii. 7esistors, *apacitors
iii. I* )O'-', I* %&N"
iv. $ransistor 2)##N
v. 1readboard, connecting wires.
T7#O*Y'
:igure shows the bloc( diagram of a freBuency multiplier using the '-' P??. $he
freBuency counter is inserted between the .*O and the phase comparator. Aince the
output of the divider is loc(ed to the input freBuency fI), the .*O is actually running at a
multiple of the input freBuency.
$he desired amount of multiplication can be obtained by selecting a proper divide
by ) networ(, where ) is an integer. :or eJample, to obtain the output freBuency fOU$ @
' fI), a divide by ) @ ' networ( is needed. $he & bit binary counter 8%&N"9 is configured
as a divide by ' circuit. $he transistor P is used as a driver stage to increase the driving
capability of the )O '-'. *# is used to eliminate possible oscillation. *2 should be large
enough to stabili>e the .*O freBuency.
P*OC#DU*#'
. *onnect the circuit as shown in figure.
2. Ad3ust the signal generator so that .i @. p-p sBuare wave at '""=>
#. $he free running freBuency fOU$ of .*O is varied by ad3usting 7 and *
and the output freBuency is determined and it should be ' times the input freBuency.
&. 0etermine the output freBuency for different input freBuency of D=> and .' D=>.
&&
*#SU,T'
$he freBuency multiplier using P?? principle is studied and the output waveform is observed.
&'