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FPGA FPGA FPGA FPGA IEEE802.11 b/g IEEE802.11 b/g IEEE802.11 b/g IEEE802.

11 b/g

FPGA IMPLEMENTATION OF IEEE
802.11 b/g MAC LAYER RECEIVER PART










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http://thesis.lib.ncu.edu.tw/paper.htm
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FPGA FPGA FPGA FPGA IEEE802.11 b/g IEEE802.11 b/g IEEE802.11 b/g IEEE802.11 b/g



1999 IEEE 802.11

802.11
802.11Media Access control(MAC)
802.11b VHSIC
Hardware Description Language(VHDL) 802.11 MAC












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FPGA IMPLEMENTATION OF IEEE 802.11 b/g
MAC LAYER RECEIVER PART

ABSTRACT

There are many new technologies are updated everyday, more and more
electric equipments and products move towards the realm of the wireless
communication. After the IEEE associations define 802.11 specifications in
1997, for various manufacturers do the best to realize and improve these
specifications which create the limitless business opportunity and make
greatest convenience for everyone. Development duration, products for
802.11 become more and more mature. In the same time, cost down and
customize specific part will be a trend.
In this thesis, we will focus on 802.11 MAC section in receiver part
which include frame formats, and some important parts, synchronization and
defragmentation frame function. We use VHDL (VHSIC Hardware
Description Language) to design a MAC receiver part based on 802.11b
parameters. For fulfilled that cost down and customize requirement.






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iii
CONTENTS

ABSTRACT (in Chinese)..................................................................................i
ABSTRACT (in English)..................................................................................ii
ACKNOWLEDGEMENTS (in Chinese)........................iii
CONTENTS................................................................................ iv
LIST OF FIG.S...............................................................................................vii
LIST OF TABLES...........................................................................................xi
CHAPTER 1 INTRODUCTION......................................................................1
1-1 Introduction..................................................................................1
1-2 Motivation....................................................................................1
1-3 Organization of the Thesis...........................................................2
CHAPTER 2 DESCRIPTION OF STANDARD..............................................5
2-1 Characteristics of wireless LANs.................................................5
2-2 IEEE 802.11 Overview................................................................6
2-2-1 IEEE 802 Concepts.......................................................................6
2-2-2 802.11 Physical Components.......................................................7
2-2-2-1 Distribution System......................................................................8
2-2-2-2 Access points................................................................................8
2-2-2-3 Wireless medium..........................................................................8
2-2-2-4 Station...........................................................................................8
2-2-3 802.11 Network Topologies.........................................................9
2-2-3-1 Independent Networks..................................................................9
2-2-3-2 Infrastructure Networks..............................................................11
2-3 MAC Layer Function Description.............................................13
iv
2-3-1 MAC Layer Operation................................................................13
2-3-1-1 Fragmentation/Defragmentation................................................14
2-3-1-2 Carrier-Sensing Function and Network Allocation
Vector............................................................15
2-3-2 DCF............................................................................................16
2-3-2-1 CSMA/CA..................................................................................16
2-3-2-2 RTS/CTS....................................................................................20
2-3-2-3 CTS-to-itself...............................................................................21
2-3-2-4 Protection Mechanism................................22
2-3-3 PCF.............................................................................................23
2-4 MAC Frame Format...................................................................23
2-4-1 Frame Control Field....................................................................24
2-4-2 Duration Field.............................................................................27
2-4-3 Address Field..............................................................................28
2-4-4 Sequence Control Field..............................................................29
2-4-5 Frame Body Field.......................................................................29
2-4-6 FCS Field....................................................................................30
2-5 Format of individual frame types...............................................30
2-5-1 Data Frame.................................................................................30
2-5-2 Control Frame.............................................................................30
2-5-2-1 Request To Send (RTS) frame format........................................31
2-5-2-2 Clear To Send (CTS) frame format............................................31
2-5-2-3 Acknowledgement (ACK) frame format....................................32
2-6 Synchronization.........................................................................32
2-6-1 Passive Scan...............................................................................33
v
2-6-2 Active Scan.............................33
CHAPTER 3 802.11 b/g MAC RECEIVER DESIGN
IMPLEMENTATION...............................................................35
3-1 Introduced of FPGA...................................................................35
3-2 MAC Receiver Design Architecture and
Implementation..........................................................................36
3-2-1 Design flow and tools.................................................................37
3-2-2 Verification equipment and test configuration...........................39
3-3 Specifications of MAC receiver each module...........................41
3-3-1 Receiver module.........................................................................41
3-3-2 CRC32 Module...........................................................................42
3-3-3 Scan and Synchronization Module.............................................47
3-3-4 Defragmentation Module............................................................50
3-3-5 Functional Verify Procedure of Receiver Module.....................50
CHAPTER 4 SIMULATION AND VERIFY RESULTS..............................55
4-1 Simulation and Results..............................................................55
4-1-1 CRC32 function..........................................................................55
4-1-2 Scan and synchronization function.............................................57
4-1-3 Defragmentation function...........................................................58
4-1-4 Full function verification............................................................62
4-2 Hardware full function verification and Results........................64
4-3 MAC Design Method Comparison............................................68
CHAPTER 5 CONCLUSIONS.......................................................................73
REFERENCES................................................................................................75
APPENDIX A.................................................................................................77
vi
A-1 Medium Access Control receiver schematic...............................77
vii
LIST OF FIG.S

Fig. 1 The seven-layer OSI reference model.....................................................6
Fig. 2 IEEE802 families and its relation to the OSI model...............................7
Fig. 3 Components of 802.11 LANs...............................................................10
Fig. 4 Independent BSS (ad hoc)....................................................................10
Fig. 5 Infrastructure BSS.................................................................................12
Fig. 6 MAC architecture..................................................................................14
Fig. 7 Fragmentation/Defragmentation...........................................................15
Fig. 8 Some IFS relationships.........................................................................17
Fig. 9 Growth of contention window..............................................................19
Fig. 10 The hidden node problem...................................20
Fig. 11 RTS/CTS/data/ACK and NAV setting...............................................21
Fig. 12 CTS-to-itself.......................................................................................22
Fig. 13 Frame control field with MAC frame format.....................................24
Fig. 14 Sequence control field.........................................................................29
Fig. 15 Frame control field subfield values within control frames.................30
Fig. 16 RTS frame...........................................................................................31
Fig. 17 CTS frame...........................................................................................31
Fig. 18 ACK frame..........................................................................................32
Fig. 19 System Architecture............................................................................36
Fig. 20 Design flow chart................................................................................38
Fig. 21 Spartan-3 Starter Kit and features.......................................................40
Fig. 22 Hardware validation environment.......................................................40
Fig. 23 Receiver part specification..................................................................42
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Fig. 24 Example of CRC generation...............................................................44
Fig. 25 CRC32 validation function Specification...........................................44
Fig. 26 Linear feedback shift register implementation of CRC-32.................45
Fig. 27 Flow chart of CRC32 module.............................................................46
Fig. 28 Active scanning function block diagram............................................47
Fig. 29 Active scanning flow chart.................................................................49
Fig. 30 Defragmentation block diagram.........................................................50
Fig. 31 Defragmentation flow chart................................................................52
Fig. 32 Full function flow chart......................................................................53
Fig. 33 CRC32 generation function validation...............................................55
Fig. 34 CRC32 got a correct RTS frame.........................................................56
Fig. 35 CRC32 got a corrupt RTS frame........................................................57
Fig. 36 Active scanning success......................................................................57
Fig. 37 Active scanning fail............................................................................58
Fig. 38 Defragmentation (Single frame).........................................................59
Fig. 39 Defragmentation (Multiply frames with normal sequence)................60
Fig. 40 Defragmentation (Multiply frames with deranged sequence)............61
Fig. 41 Defragmentation (Multiply frames with one duplicate
frame)..................................................................................................62
Fig. 42 Full function simulated result.........................................63
Fig. 43 Full function simulated result (To LLC data).....................................63
Fig. 44 CRC32 got a correct RTS frame (Hardware).................................64
Fig. 45 Active scanning success (Hardware)..............................65
Fig. 46 Defragmentation (Multiply frames with normal sequence,
Hardware)........................................................................................66
ix
Fig. 47 Full function hardware tested result............................................67
Fig. 48 Full function hardware tested result (To LLC data)...........................67




















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x
LIST OF TABLES

Table 1 Comparison of IEEE802.11abg.......................................................5
Table 2 The IFS and Slot time between different 802.11 modes....................18
Table 3 Valid type and subtype combination..................................................24
Table 4 To DS/From DS combinations in data type frames...........................26
Table 5 Duration field.....................................................................................28
Table 6 Address field contents........................................................................28
Table 7 Verification equipments list...............................................................39
Table 8 Receiver part interface signals...........................................................41
Table 9 CRC32 module interface signals........................................................45
Table 10 Scan and synchronization module interface signals.........................47
Table 11 Defragmentation interface signals....................................................50
Table 12 RTS frame data................................................................................56
Table 13 Three data with sequence number....................................................60
Table 14 Four data frames from PLCP layer..............................................62
Table 15 MAC design method comparison table........................................68
Table 16 VHDL/Verilog compared & contrasted...........................................69

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1
CHAPTER 1

INTRODUCTION

1-1 Introduction
The IEEE 802.11 wireless local area network (WLAN) has emerged as a
prevailing broadband indoor wireless networking technology in recent years.
It is being deployed widely across the enterprise, home, and public
environment. An IEEE 802.11 device runs the MAC along with at least one
physical (PHY) component. The IEEE 802.11b physical layer supporting
transmission rates from 1 to 11Mbps with Complementary Code Keying
(CCK) and Direct Sequence Spread Spectrum (DSSS) modulation schemes at
2.4GHz. A high-speed PHY, IEEE 802.11a, supporting transmission rates
from 6 to 54 Mbps with Orthogonal Frequency Division Multiplexing
(OFDM) at 5GHz. Although 802.11a can support faster transmission rates
than 802.11b, but it cant be backward-compatible with 802.11b since it
operates in different frequency band. In order to solve the problem, the IEEE
802.11 Working Group define a new PHY, called 802.11g, as an extension to
the 802.11b to support 6 Mbps to 54Mbps of transmission rates at 2.4GHz.

1-2 Motivation
The 802.11gs appearance has the same signal rate reach to 54Mbps as
802.11a and can be backward-compatible to operate with the same PHY
modulation at the same frequency band with 802.11b. 802.11b/g wireless
2
systems support three modes, which are 802.11g only-mode, 802.11b/g
mixed-mode, and 802.11b only-mode. In the 802.11b/g mixed-mode, IEEE
802.11g radios are able to receive either CCK or OFDM transmission, which
can realize 802.11b/g coexistence environments by only one access point.
However, when CCK radios and OFDM radios operate on the same channel,
the CCK radios cannot detect the OFDM transmissions. In order to avoid the
problem and the protection mechanism is added to the traditional channel
access protocol.
There are two major ways to implement of the IEEE 802.11 MAC .One
is the CPU-Based system such as Intersil 384. The other is the Cell-Based.
CPU-Based is to put the protocol and I/O into software to operate by CPU.
The advantages are flexible and easy to develop, but the disadvantages are
low-speed and high-cost. The advantage of Cell-Based is high processing
speed and the disadvantage is long developing time. FPGA is getting to use in
recently year, it has both of the advantages of CPU-Based and Cell-Based,
such as flexible, high processing speed, more easily to implement and short
developing time. Therefore the method of using FPGA to implement the
MAC controller bases on the specification of 802.11g to be used in the case
of 802.11b/g mixed-mode with protection mechanism will be the major
purpose of this thesis [1] [2].

1-3 Organization of the Thesis
There are five chapters in this thesis. Chapter 1 is introduction of thesis.
Chapter 2 is brief standard description of 802.11, MAC function and frame
format. Chapter 3 describes design flow, system architecture and the function
3
module of our design proposed in this thesis. Chapter 4 shows simulation and
the verification results. Chapter 5 gives the conclusions.























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CHAPTER 2

DESCRIPTION OF STANDARD

2-1 Characteristics of wireless LANs
Wireless LAN (WLAN) uses over the air infrared light waves, radio
waves, electron-magnetic waves instead of copper wires or optical fiber as the
transmission medium. WLAN provides the same features and benefits of a
tradition LAN, such as Ethernet. Table 1 lists the comparison of the three
kinds of standard.

Table 1 Comparison of IEEE802.11abg
802.11b 802.11a 802.11g
Spectrum 2.4~2.4835 GHz 5.15~5.825 GHz 2.4 GHz
Max Data Rates 11Mbps 54Mbps 54Mbps
Transmission
Range
Typical: 100M
Max to 300M
(Need Repeater)
About 100M,
shorter
Than 802.11b
Transmission
range

About 100M

Advantages Base physical
specification. To
provide longer
distance
transmission
More bandwidth
to
support users
connection
Compatible with
802.11b and data
rates grow up
to 54Mbps
Disadvantages High power
consumption

Spectrum in some
countries is not
open to public
Spectrum 2.4 G is
crowded


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2-2 IEEE 802.11 Overview
2-2-1 IEEE 802 Concepts
The IEEE 802 family consists of a series of specifications for local area
network (LAN) technology. Fig. 2 shows the relationship between various
components of the 802 family and the layer they place in the OSI (Open
system Interconnect, and which is shown in Fig. 1) model. IEEE 802
specification focuses on the two lowest layers of the OSI model because they
incorporate both physical and data link component and the data link layer is
partitioned into the logical link control (LLC) and the media access control
(MAC). All 802 networks have both a MAC and a physical component. The
MAC component is a set of rules to determine how to access the medium and
send the data, and the PHY handles the details of transmission and reception.

Fig. 1 The seven-layer OSI reference model
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Fig. 2 IEEE802 families and its relation to the OSI model

Individual specifications in the 802 series are identified by the other
number. For Example, the management features for 802 networks are
specified in 802.1, and 802.2 specifies the logical link control (LLC) layer.
The 802.3 is the specification for a Carrier Sense Multiple Access network
with Collision Detection (CSMA/CD). The 802.5 is the Token Ring
specification. And the 802.11 incorporate a number of additional features into
the MAC to allow for mobile network access.

2-2-2 802.11 Physical Components
There are four major physical components to form the 802.11 networks,
and they are summarized in Fig. 3. These four components are Distribution
system (DS), Access points (AP), Wireless medium and Station (STA).
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2-2-2-1 Distribution System
When several access points are connected to form a large coverage area,
they must communicate with each other to track the movements of mobile
station. The distribution system is the logical component of 802.11 used to
forward frames to their destination. A distribution system medium is the
backbone network used to transmit frames between access points. Therefore it
is often called the backbone network.

2-2-2-2 Access points
The frame used in 802.11 must be covered to another form for delivery
to other types of network. Access points perform the wireless-to-wired
bridging function. Access points can perform a number of other functions, but
bridging is by far the most important.

2-2-2-3 Wireless medium
The 802.11 standard transmits frames from one station to others with the
wireless medium. There are several physical layers defined; the architecture
allows multiple physical layers to support the 802.11 MAC. Initially, two
radio frequencies (RF) (DSSS/FHSS) and one infrared physical layer were
standardized, though the RF layers have been proved for more and more
popular applications.

2-2-2-4 Station
The purpose of building network is to transmit data between stations.
The station is a computing device with wireless network interfaces. Usually,
9
stations are battery-operated laptop or handheld computers. However, it is not
necessary that stations and it must be portable computing device. In some
environments, wireless networking is used to avoid pulling cables, and
desktops are connected by wireless LANs.

2-2-3 802.11 Network Topologies
The basic service set (BSS) is the basic building block of 802.11
network. It consists of a group of stations that communicate with each other.
BSSs come in two flavors, both of which are Infrastructure BSS and
Independent BSS. The service coverage of BSSs can be created in small
office and homes but they cant provide network coverage to larger area.
802.11 allow linking several BSSs into an extended service set (ESS) to
create wireless networks of arbitrarily large size. An ESS is created by
chaining BSSs together with a backbone network. 802.11 does not specify a
particular backbone technology. It just requires that the backbone provide a
specified set of services. Fig. 3, the ESS is the union of the two BSSs (That
provided that all the access points are configured to be part of the same ESS).

2-2-3-1 Independent Networks
Fig. 4 illustrates an Independent BSS (IBSS), in which the station in an IBSS
communicates directly with each other. Therefore, the stations must be within
direct communication range. The smallest possible 802.11 network is an IBSS
with two stations.
Usually, IBSS are set up for a specific purpose and for a short period of
time with a small number of stations. One common usage is to create a
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Fig. 3 Components of 802.11 LANs


Fig. 4 Independent BSS (ad hoc)
802.11 LAN
IBSS
2

802.11 LAN
IBSS
1

STA
1

STA
4

STA
5

STA
2

STA
3

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short-lived network to support a single meeting in a conference room. As the
meeting beginning, the meeting members create an IBSS to share data, and
the IBSS is dissolved at the end of the meeting. Due to their short duration,
and special purpose, IBSSs are sometimes referred to as ad hoc BSSs or ad
hoc networks.

2-2-3-2 Infrastructure Networks
Fig. 5 illustrates an Infrastructure BSS (IBSS is not short for
infrastructure BSS) which should include at least one Access point. Access
points are used for all communications in infrastructure networks, including
communication between mobile nodes in the same area. If one mobile station
in an infrastructure BSS needs to communicate with a second mobile station,
the communication must take two steps: first, original mobile station transfers
the frame to the access point and second, the access point transfers the frame
to the destination station. Since all communications need to relay through an
access point, the basic service area corresponding to an infrastructure BSS is
defined by the points in which transmissions from the access point can be
received and joined.
Although the multi-step transmission consumes more transmission than a
directed frame from the sender to the receiver, it has two major advantages:
one advantage is that an infrastructure BSS is defined by the distance from
the access point. All mobile stations are required to be within to reach the
area of the access point, but no restriction is placed on the distance between
mobile stations themselves. The advantage of allowing mobile stations direct
communication each other would save transmission capacity but at the cost of
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Fig. 5 Infrastructure BSS

increased physical layer complexity because mobile stations would need to
maintain neighbor relationships with all other mobile stations within the
service area; The other advantage is that the effect of the access point in
infrastructure networks is to assist with stations attempting to save power.
The access point can record that which station enters a power-saving mode
and buffer frame for it. Battery-operated stations can turn the wireless
transceiver off and power it up only to transmit and retrieve buffered frames
from the access point.

Distribution System
Portal
802.x LAN
Access
Point
802.11 LAN
BSS
2

802.11 LAN
BSS
1

Access
Point
STA
1

STA
2
STA
3

ESS
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2-3 MAC Layer Function Description
The key to the IEEE 802.11 specification is the MAC, rides on the
physical to controls the data which transmits on air. It is in charge of the core
framing operations and the interaction with a wired network backbone.

2-3-1 MAC Layer Operation
The MAC sub-layer uses one of two methods to gain access to the
network. The one method is the distributed coordination function (DCF).
Using the DCF, all the stations contended for the channels for each packet
transmission. The other method is the PCF (point coordination function),
which uses a centralized decision maker, such as an AP, to provide
contention-free frame transfers. Fig. 6 illustrates the architecture of these two
coordination functions with the MAC sub-layer. The DCF resides on the top
of the physical layer and the PCF is implemented on top of the DCF. Both the
DCF and the PCF can operate concurrently in the same BSS to provide
alternating contention and contention-free transmission periods. In an ad hoc
network the stations use only the DCF.
In other networks, stations can operate using just the DCF or a
coexisting combination of the DCF and PCF.
14

Fig. 6 MAC architecture

2-3-1-1 Fragmentation/Defragmentation
The process of partitioning a MAC service data unit (MSDU) into
smaller MAC level frames, MAC protocol data units (MPDUs), is called
fragmentation. Fragmentation creates MPDUs smaller than the original
MSDU length to increase reliability, by increasing the probability of
successful transmission of the MSDU in cases where channel characteristics
limit reception reliability for longer frames. Fragmentation is accomplished at
each immediate transmitter.
The process of recombining MPDUs into a single MSDU is defined as
defragmentation. Defragmentation is accomplished at each immediate
recipient. When a directed MSDU is received from the LLC with a length
greater than a Fragmentation Threshold, the MSDU shall be fragmented. The
MSDU is divided into MPDUs. Each fragment is a frame no larger than a
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Fragmentation Threshold. A brief illustration of fragmentation is shown in
Fig. 7 and a MSDU is fragmentation to four MPDUs.


Fig. 7 Fragmentation/Defragmentation

2-3-1-2 Carrier-Sensing Function and Network Allocation Vector
Carrier sensing is used to determine if the medium is available. There are
two types of carrier-sensing function in 802.11: the physical carrier-sensing
and virtual carrier-sensing function. If the carrier-sensing function indicates
that the medium is busy, the MAC reports and indicates this to higher layer.
Physical carrier-sensing functions are provided by the physical layer in
question and depend on the medium and modulation used. It is difficult (or,
more to the point, expensive) to build physical carrier-sensing hardware for
RF-based media, because transceivers can transmit and receive
simultaneously only if they incorporate expensive electronics.
Virtual carrier-sensing is provided by the Network Allocation Vector
(NAV). Most 802.11 frames carry a duration field, which can be used to
reserve the medium for a fixed time period. The NAV is a timer that indicates
the amount of time the medium will be reserved. Stations set the NAV to time
16
for which they expect to use the medium, including any frames necessary to
complete the current operation. Other stations count down from the NAV to 0.
When the NAV is nonzero, the virtual carrier-sensing function indicates that
the medium is busy; when the NAV reaches 0, the virtual carrier-sensing
function indicates that the medium is idle [2] [3].

2-3-2 DCF
2-3-2-1 CSMA/CA
802.11 is similar to Ethernet (IEEE 802.3). The access method of
Ethernet in the PHY is called CSMA/CD (Carrier Sense Multiple Access with
Collision Detection), transmits the frames with collision detected. It is known
that collision detection is not feasible and collision waste valuable
transmission capacity. Therefore the 802.11 uses the CSMA/CA (Carrier
Sense Multiple Access with Collision Avoidance) to instead of CSMA/CD.
With the CSMA/CA model, the station will detect the wireless network
situation. If the intensity of signal detected is under the threshold, it means
that there are no transmitted frames in the channel; In other words, if station
detected transmitted frames, it means the channel is used. Therefore the
station needs to defer to transmit frame. If the station detect the channel is
idle, it will obey the priority-grade, the first is to wait for a IFS (Interval
Frame Space) time, and then if the station still does not detect any transmitted
frames, the station could transmit frames out. IEEE 802.11 sets four different
IFSs defined to provide priority levels for access to the wireless media. Fig. 8
shows some of these relationships.
(1) SIFS: short interframe space
17
(2) PIFS: PCF interframe space
(3) DIFS: DCF interframe space
(4) EIFS: extended interframe space


Fig. 8 Some IFS relationships

SIFS (Short IFS)
SIFS is the shortest of inter-frame spaces and have the supreme priority.
It shall be used for an ACK frame, a CTS frame, the second or subsequence
MPDU of a fragment burst.
PIFS (PCF IFS)
PIFS is used by the PCF during contention-free operation. Stations with
data to transmit in the contention-free period can transmit after the PIFS has
elapsed and preempt any contention-based traffic. It is calculated as SIFS + a
Slot time.
DIFS (DCF IFS)
DCF is the inter frame space used for a station willing to start a new
transmission which is calculated as SIFS + 2 x Slot time.
EIFS ( Extended IFS)
The time that the retransmitted station needs to wait for is according to
Table 2. It is not a fixed interval.
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Table 2 The IFS and Slot time between different 802.11 modes
Protocol Slot time SIFS PIFS DIFS
802.11a 9us 16us 25us 34us
802.11b 20us 10us 30us 50us
802.11g Long=20us,Short=9us 10us Long=30us,
short=19u s
Long=50us,
short=39us

SIFS<PIFS<DIFS<EIFS, the higher priority-grade, the IFS shorter is.
The higher IFS has the higher opportunity to transmit frames but it still has
high opportunity that collision occurred with the same priority-grade of
frames, and the reason why is that all stations transmitted frames after waiting
for the same priority-grade of IFS. The solution to solve this problem is to
add Backoff-Window. While all the stations detect the idle period of channel
reach to the DIFS, they can not transmit the frame immediately. Each station
gains access the CW (Contention Window) directly and execute the backoff
scheme [4] [5].
Each station is assigned a random number gets from the CW with
backoff scheme. The random number is set the value of counter to count
down. As count-down number is zero, the station transmits the frame
immediately. If the counter does not count down to zero and detect the
channel had been occupied, the station need to stop counting at the same time.
Then the station continued to count at the situation that the channel was idle
again. It can be lower the opportunity of collision greatly with that all the
stations possess different backoff time. The formula for the random backoff
time is:
19

Backoff Time = Random( ) a Slot Time

Random ( ): a random number drawn a uniform distribution over the interval
[0, CW], CW is an integer lied between CWmin and CWmax.
The backoff time is an integer multiple of the slot time. The initial value
of CW is CWmin, and will be sequentially ascending integer power of 2
minus 1 when a frame fails during transmission. If the number of
retransmission is equal to five, the contention window stops increasing and
remains the value of the CWmax until the frames is successfully transmitted.
Fig. 9 illustrates the growth of contention window [6].
The IEEE 802.11 defines the range of CW, and the CW of IEEE 802.11
b/g mixed-mode is:

Fig. 9 Growth of contention window
20
2-3-2-2 RTS/CTS
The hidden node problem is a serious problem in wireless networks. The
problem comes from wireless node has limited radio transmitting range and
that each wireless node can not be expected to be able to communicate with
other nodes in the network. The hidden node phenomenon is illustrated with
Fig. 10. The WLAN environment consists of an AP and two stations, station
A and station B just can communicate with AP but can not with each other. If
station A has an ongoing transmission with AP, it may be interfered by the
transmission from B to AP, since B cannot sense the transmission from A. In
this kind of situation, the node B is called to be hidden from node A. It will
cause collision.

Fig. 10 The hidden node problem

IEEE 802.11 provides a solution to the hidden node problem by using
the Request To Send-Clear To Send (RTS/CTS) scheme. In the RTS/CTS
algorithm, the node which wants to send frames sends a RTS frame to the
21
destination node first, and after a SIFS the destination node responds with a
CTS frame immediately. It is when the source node receives the CTS
transmitted from destination node accurately; the source node is allowed to
transmit frames. The RTS and CTS frames contain the duration of the coming
data transmission which allows stations to set the NAV (referred in 2-3-1-2)
to monitor the RTS/CTS exchange to refrain from transmitting during this
period. With the RTS/CTS and NAV scheme can solve the hidden node
problem and reduce the probability of collision greatly. Fig. 11 illustrates the
two schemes [7].


Fig. 11 RTS/CTS/data/ACK and NAV setting

2-3-2-3 CTS-to-itself
CTS-to-itself is similar to RTS/CTS, and this scheme is referred in IEEE
802.11g standard. It is use to solve the co-existing problem of 802.11b and
802.11g. In the scheme (Fig. 12), after the usual sensing time of DIFS and the
22
random back-off time, the sender transmits a CTS message (with its own
address) to inform all the neighboring 802.11b nodes of an upcoming packet
transmission. Following the CTS message, the sender waits for SIFS duration
and then transmits the payload packet and expects an ACK within the SIFS
time as usual.


Fig. 12 CTS-to-itself

2-3-2-4 Protection Mechanism
Because of the different PHY modulation of 802.11b and 802.11g, the
most important purpose of protection mechanism is to let the 802.11b node
can hear the transmission signal of 802.11g. CTS-to-itself and RTS/CTS are
both protection mechanism of 802.11g. The CTS-to-itself mechanism is lower
in network overhead cost than the RTS/CTS mechanism. But it is less robust
against hidden nodes and collisions than the RTS/CTS.
23
2-3-3 PCF
In normal operation all 802.11-compliant stations use the DCF. As an
option the priority-based PCF may be used to provide contention-free frame
transfers. For example, this may be activated to support time-sensitive
information such as audio or video. The price for using the PCF is a greater
overhead on the network since the PCF needs to send out polling frames that
grant a station permission to send a frame to any destination. The point
coordinator (PC) that performs the PCF resides in the AP within a BSS.
When the PC wants to gain control of the medium, it sends out a beacon
at the end of the PIFS interval. The information in the beacon communicates
the length of the contention-free period to all stations and prevents them from
taking control of the medium until the end of this period. The exact methods
for carrying this out are somewhat involved and you can be found in the IEEE
802.11 standards.

2-4 MAC Frame Format
IEEE 802.11 MAC frame composes of three fields:
(1) A MAC header, which comprises frame control, duration, address,
and sequence control information.
(2) A variable length frame body, which contains information specific to
the frame type.
(3) A frame check sequence (FCS), which contains an IEEE 32-bit cyclic
redundancy code (CRC).
Fig. 13 illustrates the Frame control Field with MAC frame format, and
the form of frame control field is introduced as follow:
24
2-4-1 Frame Control Field
Protocol Version: The Protocol Version subfield is two bits in length.
For 802.11 standards the value of protocol version is 00.


Fig. 13 Frame control field with MAC frame format

Type and Subtype: The Type and Subtype fields together identify the
function of the frame. There are three frame types: control, data and
management frame. Each of the frame types have several defined
subtypes, and are defined in Table 3.

Table 3 Valid type and subtype combination
Type value b3 b2

Type Description Subtype Value b7 b6
b5 b4
Subtype Description
00

Management 0000 Association Request
00 Management 0001

Association Response

25
00 Management 0010

Reassociation Request

00 Management 0011

Reassociation Response
00 Management 0100

Probe Request

00 Management 0101

Probe Request
00 Management 0110-0111

Reserved

00 Management 1000

Beacon

00 Management 1001

ATIM

00 Management 1010

Disassociation

00 Management 1011

Authentication

00 Management 1100

Deauthentication

00 Management 1101-1111

Reserved

01

Control

0000-1001

Reserved

01

Control

1010

PS-Poll

01

Control

1011

RTS

01

Control

1100

CTS

01

Control

1101

ACK

01

Control

1110

CF End

01

Control

1111

CF End+CF-Ack

10

Data

0000

Data

10

Data

0001

Data+CF-Ack

10

Data

0010

Data+CF-Poll

10

Data

0011

Data+CF-Ack+CF-Poll

10

Data

0100

Null Function
(no data)
26
10

Data

0101

CF-Ack (no data)

10

Data

0110

CF-Poll (no data)

10

Data

0111

CF-Ack+CF-Poll
(no data)
10

Data

1000-1111

Reserved

11 Reserved

0000-1111

Reserved


To DS/From DS: It is described in Table 4.

Table 4 To DS/From DS combinations in data type frames
To/From DS value Meaning
To DS = 0
From DS = 0

A data frame direct from one STA to
another STA within the same
IBSS, as well as all management and
control type frames
To DS = 1
From DS = 0
Data frame destined for the DS

To DS = 0
From DS = 1
Data frame exiting the DS
To DS = 1
From DS = 1

Wireless distribution system (WDS)
frame being distributed from
one AP to another AP

More Fragments: If the value is 1, it means that there are still other
Fragments wait for transmission.
Retry: If the value is 1, it means that the Data frame (or Management
frame) is the retried frame.
Power Management: A value of 1 indicates that the STA will be in
power-save mode. A value of 0 indicates that the STA will be in the
active mode.
27
More Data: The More Data field is set to 1 in broadcast/multicast frames
transmitted by the AP, when additional broadcast/multicast MSDUs, or
MMPDUs, remain to be transmitted by the AP during this beacon
interval.
WEP: It is set to 1 if the Frame Body field contains information that has
been processed by the WEP algorithm.
Order: It is set to 1 in any data type frame that contains an MSDU, or
fragment thereof, which is being transferred using the Strictly Ordered
service class.

2-4-2 Duration Field
The Duration/ID field is 16 bits in length. The contents of this field are
as follows:
(1) In control type frames of subtype Power Save (PS)-Poll, the
Duration/ID field carries the association identity (AID) of the station that
transmitted the frame in the 14 least significant bits (lsb), with the 2 most
significant bits (msb) both set to 1. The value of the AID is in the range
12007.
(2) In all other frames, the Duration/ID field contains a duration value as
defined for each frame type. For frames transmitted during the contention-free
period (CFP), the duration field is set to 32768. Whenever the contents of the
Duration/ID field are less than 32768, the duration value is used to update the
network allocation vector (NAV). Table 5 shows the Duration field.


28
Table 5 Duration field
Bit 15 Bit 14 Bit 13-0 Usage
0 0-32767 Duration
1 0 0 Fixed value within
frames transmitted
during the CFP
1 0 1-16383 Reserved
1 1 0 Reserved
1 1 1-2007 AID in PS-Poll
frames
1 1 2008-16383 Reserved

2-4-3 Address Field
There are four fields in the MAC frame format. These fields are used to
indicate the BSSID, source address, destination address, transmitting station
address, and receiving station address. The usage of the four address fields in
each frame type is indicated by the abbreviations BSSID, DA, SA, RA, and
TA, indicating basic service set identifier (BSSID), Destination Address,
Source Address, Receiver Address, and Transmitter Address, respectively.
The number of address field used which depends on the type of frame. Most
data frames use three fields for source, destination, and BSSID. The number
and arrangement of address field in a data frame depends on how the frame is
traveling relative to the distribution system, and it can refer the Table 6. Most
transmission used three addresses which is why only three of the four
addresses are contiguous in the frame format.

Table 6 Address field contents
Scenario To
DS
From DS Address 1 Address 2 Address 3 Address 4
29
ad-hoc 0 0 DA SA BSSID N/A
IF network,
from AP
0 1 DA BSSID SA N/A
IF network,
to AP
1 0 BSSID SA DA N/A
IF network,
within DS
1 1 RA TA DA SA

2-4-4 Sequence Control Field
The Sequence Control field is 16 bits in length and consists of two, the
Sequence Number and the Fragment Number. The format of the Sequence
Control field is illustrated in Fig. 14.
Sequence Number field: It is a 12 bits field indicating the sequence
number of an MSDU. The Sequence numbers are assigned from a single
modulo 4096 counter, starting at 0 and incrementing by 1 for each MSDU.
Each fragment of MSDU contains the assigned sequence number.
Fragment Number field: It is a 4 bits field indicating the number of each
fragment of an MSDU. The fragment number is set to zero in the first or
only fragment of an MSDU and is incremented by one for each
successive fragment of the MSDU.

Fig. 14 Sequence control field

2-4-5 Frame Body Field
The frame body, also called the Data field, moves the higher-layer
payload from station to station. 802.11 can transmit frames with a maximum
30
payload of 2312 bytes of higher-level data.

2-4-6 FCS Field
FCS (frame check sequence) field contains a 4-byte cyclic redundancy
check (CRC). It contains the result of applying the CCITT CRC-32
polynomial to the MAC header and frame body.

2-5 Format of individual frame types
Frames can be classified according to the frame types and subtype (cf.
Table 3) they are data frame, control frame, and management frame.

2-5-1 Data Frame
The form of data frame is similar to basic MAC frame format (cf. Fig.
13). The content of Frame Body is received from LLC layer.

2-5-2 Control Frame
In this section we just introduce the RTS frame, CTS frame, and ACK
frame we used in this thesis. Others frame can refer to the specification of
IEEE 802.11. The subfields within the Frame Control field of control frames
are set as illustrated in Fig. 15.

Fig. 15 Frame control field subfield values within control frames
31
2-5-2-1 Request To Send (RTS) frame format
The format for RTS frame is as defined in Fig. 16. The RA of the RTS
frame is the address of the STA, on the WM, that is the intended immediate
recipient of the pending directed data frame. The TA is the address of the
STA transmitting the RTS frame. And the duration value is the time, in
microseconds, required to transmit the pending data frame, plus one CTS
frame, plus one ACK frame, plus three SIFS intervals.


Fig. 16 RTS frame

2-5-2-2 Clear To Send (CTS) frame format
The format for CTS frame is as defined in Fig. 17. The RA of CTS
frame is copied from the TA field of the immediately previous RTS frame to
which the CTS is a response.


Fig. 17 CTS frame

The duration value is the value obtained from the Duration field of the
32
immediately previous RTS frame, minus the time, in microseconds, required
to transmit the CTS frame and its SIFS interval.

2-5-2-3 Acknowledgement (ACK) frame format
The frame format for the ACK frame is as defined in Fig. 18. The RA of
the ACK frame is copied from the Address2 field of the immediately previous
directed data frame.


Fig. 18 ACK frame

If the More Fragment bit was set to 0 in the Frame Control field of the
immediately previous directed data or management frame, the duration value
is set to 0. If the More Fragment was set to 1 in the Frame Control field of the
immediately previous directed data frame, the duration value is the value
obtained from the Duration field of the immediately previous data frame,
minus the time, in microseconds, required to transmit the ACK frame and its
SIFS interval [8].

2-6 Synchronization
A timing synchronization function (TSF) keeps the timer for all STAs in
is the heart of synchronization. Coordinators for data distribution and power
management functions, thus the access point are responsible for transmitting a
33
Beacon frame periodically. All the STA has the same TSF value, which is
received from access point in an infrastructure BSS.

2-6-1 Passive Scan
STAs shall receive beacon frame to each channel scanned for no longer
than maximum duration time, it saves power consumption for the devices
because it does not require to transmitting.

2-6-2 Active Scan
In active scan, STAs generate Probe frames and subsequent processing
of received Probe Response frames. STAs using active scanning procedures
describe as below on each channel:
Move to the channel and wait ProbeDelay time expired or an indication
of an incoming frame. Perform a DCF process to send Probe Request frame.
If no any Probe Response until the Minimum Response Time
(MinChannelTime) there is no network and move to next channel. Otherwise,
save all Probe Response frame information until Maximum Response Time
(MaxChannelTime).
According to 802.11b standard, aCWmin = 31 slots, aSlotTime = 20 us
and DIFS = 50 us. MinChannelTime = DIFS + (aCWmin x aSlotTime) =
670us. MaxChannelTime = 10.24ms.





34































35
CHAPTER 3

802.11 b/g MAC RECEIVER DESIGN
IMPLEMENTATION

3-1 Introduced of FPGA
FPGA (Field-Programmable Gate Array) a type of logic chip that can be
programmed by user.
Before the advent of programmable logic, custom logic circuits were
built at the board level using standard components, or at the gate level in
expensive application-specific (custom) integrated circuits. The FPGA is an
integrated circuit that contains many (64 to over 10,000) identical logic cells
that can be viewed as standard components. Each logic cell can independently
take on any one of a limited set of personalities. The individual cells are
interconnected by a matrix of wires and programmable switches. A user's
design is implemented by specifying the simple logic function for each cell
and selectively closing the switches in the interconnect matrix. The array of
logic cells and interconnects form a fabric of basic building blocks for logic
circuits. Complex designs are created by combining these basic blocks to
create the desired circuit.
How are FPGA programs created? Individually defining the many
switch connections and cell logic functions would be a daunting
task. Fortunately, this task is handled by special software. The software
translates a user's schematic diagrams or textual hardware description
36
language code then places and routes the translated design. Most of the
software packages have hooks to allow the user to influence implementation,
placement and routing to obtain better performance and utilization of the
device. Libraries of more complex function macros further simplify the
design process by providing common circuits that are already optimized for
speed or area. We use FPGA with VHDL hardware description language to
design our MAC receiver part in this thesis.

3-2 MAC Receiver Design Architecture and Implementation
In this chapter we describe how to implementation of MAC receiver in
this thesis. We only realize MAC receiver part. Fig. 19 illustrates system
architecture. We try to divide MAC receiver part to 4 parts. Those are RX
MAIN module, CRC32 module, Scan and synchronization module and
defragmentation module.


Fig. 19 System architecture

Physical
Layer



RX
MAIN
Module
De-fragmentation
Module
Scan and
synchronization
Module
CRC 32 module
MAC receiver
part

LLC

Transmitter
Part
Output
Input

MAC receiver part implementation in this thesis
37
The 3-2-1 section, we describe our design flow and tool. The 3-2-2
section, we describe verification equipment and test configuration. Other
sections will have more detail description for each module [9].

3-2-1 Design flow and tools
Design flow is shown Fig. 20. Firstly, we create MAC receiver function
specification in our thesis and base on 802.11 b/g specification. We define the
MAC system specifics and functions module.
Second, we start to create each function module by VHDL language.
Then we create behavior module and generate test bench as input on Xilinx
ISE7.1i. We simulate each module by ModelSim SE6.0c program and get
simulation results. If simulation results meet our specific and requirement we
can start to implement to FPGA (hardware circuit). After synthesize and fit
out design on Xilinx ISE7.1i program we implement to FPGA and use LA to
check results.
After each module validates done we combine all function modules and
validate MAC receiver total function at last.


38

Fig. 20 Design flow chart

Yes
No
Test waveform
Generate test bench
on Xilinx ISE7.1i as
input
Design function
model by VHDL
on Xilinx ISE7.1i
platform
Output response
Does simulation
result correct?

START
Get simulation result
on ModelSim SE6.0
and check function
Modify each
function module

Implement to FPGA
and used LA to get
test result.
No
Yes
Does test result meet
our requirement?

END
Create MAC
receiver function
specification in
our thesis and
base on 802.11 b/g
specification
39
3-2-2 Verification Equipment and Test Configuration
Table 7 lists test equipment. Item 1 is Spartan-3E Sample Pack as PHY
layer and output MPDUs packages to our design receiver part. Item2
Spartan-3 Starter Kit, we implemented MAC receiver part on the FPGA
emulation board. Fig. 21 is picture of the board and list features. Item3
Tektronix TLA 714 Logic Analyzer as LLC layer and we measured our
design output results. Fig. 22 shows hardware validation environment.

Table 7 Verification equipments list
Item Name Description
1
Spartan-3E Sample Pack
(XC3S100E,TQ144BGQ)
As PHY layer and output MPDUs
packages to RX part.
2
Spartan-3 Starter Kit
(XC3S200,FT256AFQ)
Implemented MAC receiver part on the
FPGA emulation board.
3
Tektronix TLA 714
Logic Analyzer
As LLC layer and we measured the
result from receiver part output.
4
Tektronix TDS 210
Digital real-time
oscilloscope
Debug only.
5 Notebook
Modified design and generated JTAG
programming file. Then we can program
on FPGA part by JTAG download cable
from notebook print port.
6 JTAG download cable
Program xxx.bin file on FPGA part.


40



Fig. 21 Spartan-3 Starter Kit and features


Fig. 22 Hardware validation environment
Spartan-3E Sample Pack
(PHY layer input)
Spartan-3 Starter Kit
(MAC receiver part)

Tektronix TLA 714 Logic Analyzer
(As LLC layer)
41
3-3 Specifications of MAC Receiver each Module
3-3-1 Receiver Module
The receiver part module is in charge for coordination others modules. It
receives MPDUs from PLCP and decodes packages. The specification is
shown in Fig. 23 and shows that we want to realize in thesis. Table 8 list
MAC receiver part interface signals.
The following notations are used to describe the signal type:
I Input signal
O Output signal
I/O Bi-directional Input / Output signal

Table 8 Receiver part interface signals
Name Type Description
GenPRFrame O Notifies transmitter send ProbeRequest frame.
GenACKFrame O Notifies transmitter send acknowledge (ACK)
frame.
GenCTSFrame O Notifies transmitter send Clear To Send (CTS)
frame.
ReceiveACK O Notifies transmitter that receiver got ACK
frame.
ReceiveRTS O Notifies transmitter that receiver got RTS
frame.
DataReady O Notifies LLC layer that some valid data are
ready to be transmitter.
OutToLLC O Data signals to LLC layer.

RX_Start I Physical layer notifies receiver start to receive
data.
PHYData I Data signals from physical layer.

42
Logic Link
Control
(LLC)
Transmitter part
32
4
PHY
Layer
DataReady
OUTToLLC
PHYData
Rx_start
G
e
n
C
T
S
F
r
a
m
e
G
e
n
A
C
K
r
a
m
e
G
e
n
P
R
F
r
a
m
e
R
e
c
e
i
v
e
R
T
S
R
e
c
e
i
v
e
A
C
K
MAC Receiver

Fig. 23 Receiver part specification

The physical layer splits to two components in 802.11, the PLCP
(Physical Layer Convergence Procedure) and PMD (Physical Medium
Dependent). We assume the data processing was done by PLCP layer in this
thesis so we dont need to parse frame from PHY layer.
The PLCP is the bridge between MAC and radio transmission, it
translates MPDUs to PMD frames. The PMD is responsible for transmitting
any bits it receives from the PLCP to the wireless medium by using antenna.
There are some modulation modes based on data rates in 802.11(a, b, g). The
major efforts are almost in the PLCP and PMD layer so we did not consider
more any physical layer problem in this thesis.

3-3-2 CRC32 Module
The CRC32 module is used for judgment the frame is valid or not. The
data input composes of three parts, MAC header + Frame body + FCS. FCS
43
value is calculated based on CRC-32 algorithm. CRC-32 is cyclic redundancy
code and 32 represent the length of checksum in bits. It uses following
standard generator polynomial:

G(x) = x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x + 1

Calculating FCS, the frame is represented (original frame, before adding
the FCS) as a polynomial, M(x), then multiplies M(x) by X
32
, and divides the
result by a standard generator polynomial G(x) (all of procedure is completed
by using Modulo-2 operation). The resulting remainder of the above
operation is FCS. The FCS is appended to the original frame to form coded
frame which will be transmitted. The whole of the above operation can be
mathematically represented as

CRC = Remainder of (M(x) * X
32
/G(x))

Fig 24 shows example of CRC generation. We set M(x) =03(h) and start
to calculate the CRC value. Then get the full frame value =30D4326D9(h).
The Table 9 shows CRC32 module interface signals and Fig. 25 shows
CRC32 Validation Function Specification that we define.
44

Fig. 24 Example of CRC generation

Receiver
main part
CRC32
Molule
DataIn
RESET
CLK
8
12
DataCount
CRCResult
CRCFinish

Fig. 25 CRC32 validation function specification
45
The single-bit data input (serial) calculation of CRC-32 is implemented
with a linear feedback shift register (LFSR). The CRC-32 LFSR is illustrated
in Fig. 26 (register bits "3" through "25"are left out of the figure to simplify
the drawing). Presetting the flip-flops to 0xFFFFFFFF is equivalent to
complementing the first 32-bits of the data stream. For the first 32 cycles, the
right-most XOR gate in the figure is an inverter. The XOR of any data with a
binary "1" result in the complement of the original data. We used the
reference module as a component and implemented to our CRC32 module.

Table 9 CRC32 module interface signals
Name Type Description
DataIn I 8bit data from host to calculate.
DataCount I Data size for CRC32, maximal calculated data size
= 212 = 4096 bytes.
CRCFinish O Indicated CRC32 finished all data process.
CRCResult O Indicated CRC32 checked result by this module.
CLK I System common clock.
RESET I System common reset.


Fig. 26 Linear feedback shift register implementation of CRC-32
46
Fig. 27 shows the flow chart of CRC32 module that we modified from
the reference code. We illustrate brief CRC32 flow chart as below. When we
receive MPDUs from PLCP we will calculated MAC header + Frame body to
generate new FCS. Then we compared new FCS to old FCS that received
from PLCP. When two value are the same it means no error during received.
The CRCResult signal will output high and inform receiver main module.
The MPDU is correct. When two value are different it means there are some
errors during received. The CRCResult signal will output low and inform
receiver main module. The MPDU is wrong and discard it [10].


Fig. 27 Flow chart of CRC32 module
New FCS Old FCS
START
Get new FCS and output
CRCFinish=1
Compare new
FCS and old
FCS value
CRCResult=1
END
Receive data and start to
generate new CRC value
CRCResult=0
New FCS = Old FCS
47
3-3-3 Scan and Synchronization Module
STAs must scan firstly, join BSS and start to synchronization. Scan and
synchronization is very important in receiver part. STAs shall do
synchronization with a BSS before any actions. First we must scan all
network environment to check any AP existed or not (If-BSS), and then
update TSF by user select. Fig. 28 shows the block diagram of this function.
We only used active scanning in this thesis. Table 10 list signals of the scan
and synchronization module that we define specifications for our MAC
design.

Receiver
main part
8
ScanFinish
RESET
CLK
PRcount
SyncSuccess
Scan & Sync
Module
ChannelVal
4

Fig. 28 Active scanning function block diagram

Table 10 Scan and synchronization module interface signals
Name Type Description
Scan_Finish O Indicates host that all channels has been scanned
48
completely.
GenPRFrame O Notifies TX part to transmit Probe Request
frame.
PRCount I Probes Response count from host.
ChannelVal O Sets Channel value to PHY
Syn_Success O Indicates synchronization success, TSF is
updated by user select.
CLK I System common clock.
RESET I System common reset.

Scan and Synchronization flow chart is shown in Fig. 29. The module
sets the ChannelVal to inform which channel is going to scan. Either
ProbeDelay expired or an incoming frame detected, start the DCF access
mechanism and TSF function firstly. Second send a ProbeRequest frame and
then starts the probe timer. Wait until MinChannelTime, if the medium never
busy, change to next channel, and otherwise wait until MaxChannelTime. In
the same time process any ProbeResponse frames.
49

START
Does get valid
channel value ?
No
Yes
END
Does ProbeDelay
Expire?
Does PHY start
signal sign?
No
No
Yes Yes
1. Start to perform DCF basic
access procedure and TSF
function.
2. Send a probe signal with
broadcast destination, SSID and
broadcast BSSID.
3. Clear and ProbeTimer starts
to count.
Is PHYCCA
indication?
Save Probe response to TX part
Is ProbeTime
<MaxChannelTime
Is PHYCCA
sign?
Yes
ProbeTimer +1
Yes
No
Yes
No
No
Is ProbeTime
<MinChannel
ProbeTimer +1
Yes
No
Fig. 29 Scan and Synchronization flow chart

50
3-3-4 Defragmentation Module
The Defragmentation module processes the frame which is fragmented
in the transmitter end. After main module check More Fragments bit in MAC
header, if More Fragments bit was set to 1, this module saves incoming frame
body and sequence control, then reassembly them after all fragments of
MSDU received successfully. Fig. 30 shows defragmentation function block
diagram. Table 11 list signals of the module.

Transmitter part
Logic Link
Control
(LLC)
4
CLK
MAC_HDR_MultiFrame
FrameBody
RESET Receiver
main part
GenACKFrame
MAC_HDR_SeqCtrl
Defragmentation
Module
DataOutValid
ToLLC
4
4

Fig. 30 Defragmentation block diagram

Table 11 Defragmentation interface signals
Name Type Description
ToLLC O After data defragmentation complete,
send data out to LLC through these
signals.
MAC_HDR_MultiFrame O Multi-frame indicator.
51
Mac_HDR_SeqCtrl I MAC header information contains
sequence control field.
DataOutValid O Indicate defragmentation done, data
are valid.
FrameBody Frame input from main module.
GenACKFrame O Notifies transmitter send ACK frame.
CLK I System common clock.
RESET I System common reset.

Fig. 31 shows the Defragmentation module flow chart. If the More
Fragments bit is clear in the MAC_HDR_Multiframe, then reassembly the
data in the buffer and sent to LLC according to previous data information. If
the More Fragments bit is set, then sort the data in buffer to check. Is it
duplicate frame or not? Then discard duplicate frame or save new frame data
to buffer.

3-3-5 Functional Verify Procedure of Receiver Module
In order to verify our designs, we will verify all modules functions by
the flow chart which is shown in Fig. 32. We combined all modules as a
MAC receiver part. First we perform the synchronization module to find the
AP, then assume one large MSDU was segmented to three small frames
transmitted in transmitter, so defragmentation module assemble these frames
in receiver, then sent to upper layer, data link layer [11] [12].

52

Fig. 31 Defragmentation flow chart
START
Is More
Fragment=1?
Discard multiply
data and dont
save this data on
buffer
Receive correct
frame
Is multiply data
in buffer?
Move data to buffer
END
Is duplicate
frame?
Save frame and
sequence information
Discard current
frame
Generate ACK frame
to TX part
Yes
No
No
No
Yes
Yes

1. Assembly all data
in order on
buffer.
2. Generate ACK
frame to TX part.
3. Send data on
buffer to LLC in
order.

53

Fig. 32 Full function flow chart
START
Perform Scan and
synchronization
Does find
valid AP?
Does receive
frame?
Does CRC32
check received
frame correct?
Does DA =
Me ?
Parsed Frame and
start DCF function
END
Check and notify
CTS to TX part
1. Save Data
frame.
2. Check and
notify ACK
from TX part.
Does DA =
Me?
Is More
Fragment=1?
1. Defragment
frames.
2. Send data to
LLC in
order.
Yes
No
No
No
No
Yes
Yes
Yes
No
No
Yes
Yes
54

























55
CHAPTER 4

SIMULATION AND VERIFY RESULTS

4-1 Simulation and Results
We are using ModelSim software to simulate for each module separately,
and then do a full function simulation based on our design.

4-1-1 CRC32 function
Because the CRC32 generate module we refer to exist code on Xilinx
support Web site. First we must validate CRC32 generation function. Is the
module workable? We input one data (03h) as Fig. 24. The CRC result is
0D4326D9h. Fig. 33 shows simulation result and simulation result is
0D4326D9h as well.
Output 0D4326D9h is correct

CRCFinish
Fig. 33 CRC32 generation function validation
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Than we verify frame integrity after received. We assume a RTS frame
is received from RX module. We shown in Table 12 and its CRC32 value is
as below list:

11111001010000100011011111110011 (F94237F3)

After CRCfinish signal go to high we check CRCResult signal behavior.
If CRCResult signal goes to high the result is corrected. Please check Fig. 34.
We assume get a correct data frame and the CRCResult signal goes to high.
Please check Fig. 35. We assume get a corrupt RTS frame and the CRCResult
signal still keeps low. It means the CRC32 function is workable and the result
is correct.

Table 12 RTS frame data
Frame
Control
Duration RA TA FCS
2D00 E610 AABBCCDDEEFF 665544332211 F94237F3

CRCFinish

CRCresult=1
Fig. 34 CRC32 got a correct RTS frame
57
1 bit error (1010 to 1011) CRCFinish

CRCResult=0
Fig. 35 CRC32 got a corrupt RTS frame

Have a AP and inform TX part to generate PRframe Scan finish

Channel 11 Channel 22 Channel 33 Scan success
Fig. 36 Active scanning success

4-1-2 Scan and synchronization function
We validated scan and synchronization function in the same way as
58
CRC32 function. We assume the MinChannelTime is 100us,
MaxChannelTime is 150us, and there are three channels (0x11,0x22,0x33)
need to be scanned. In The Fig. 36 shows the active scanning function is
performed successfully [13].
The Fig. 37 shows scan failure symptom. If there is not any
ProbeResponse frame in these three channels before reach the
MinChannelTime the scanfinish signal will output low. It means that scan
AP fail.
No find AP Scan finish

Scan fail
Fig. 37 Active scanning fail

4-1-3 Defragmentation function
Fragmentation is a MAC-level proposition that essentially tries to
minimize the risk of suffering a frame error due to a difficult terrain presented
by the PHY. When MSDU is grater than fragment threshold, transmitter will
fragment MSDU into small frames, receiver should defragment (assembly)
these frames by their sequence in MAC header. We simulate the four cases to
59
validate defragmentation function [14].
Case 1: Only one data frame and MAC_HDR_Multiframe= 0 (More
Fragments = 0) received.
So defragmentation module can pass frame body to LLC directly.
Defragmentation module informs TX part to generate ACK frame. Fig. 38
shows simulation result.

Data 1, Seq 1(MAC_HDR_Multiframe= 0)

Output to LLC
Fig. 38 Defragmentation (Single frame)

Case 2: There are three data frames received with normal sequence and
no duplicate frame detected.
Table 13 list three data with its sequence number. We input these data in
order to defragmentation module which we design. Fig. 39 shows the
simulation result as we expect. There are three data that are received and
output to LLC in order.
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Data 2, Seq 2

Data 1, Seq 1 Data 3, Seq 3 Output to LLC in sequence
Fig. 39 Defragmentation (Multiply frames with normal sequence)

Table 13 Three data with sequence number
Data1 Date2 Data3
Data AAAAAAAA BBBBBBBB CCCCCCCC
Sequence number 01 02 03

Case 3: There are three data frames received deranged sequence and no
duplicate frame detected.
The frame one sequence number is one, frame two sequence number
is three, frame three sequence number is two. There are three data that are
received but are not in sequence number. Defragmentation module will
rearrange sequence and output data in sequence to LLC output. Fig. 40 shows
the simulation result as we expect and data output to LLC are correct.
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Data 2, Seq 3 (not in sequence) Data 3, Seq 2 (not in sequence)

Data 1, Seq 1 Output to LLC in sequence
Fig. 40 Defragmentation (Multiply frames with deranged sequence)

Case 4: There are three data frames received, deranged sequence and one
duplicate frame detected.
The data frame one sequence number is one. The data frame two has
the same sequence number and data as data frame one. Defragmentation
module will discard duplicate frame two and output correct data of buffer in
sequence to LLC. Fig. 41 shows the simulation result. Because data frame
two is discarded defragmentation module only send two data to LLC.
Through four case simulation results we can make sure our design that
meets our requirement.
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4-1-4 Full function verification
We set one situation as Fig. 32 to verify the full function of our design.

Data 1, Seq 1 (duplicate frame) Data 2, Seq 2

Data 1, Seq 1 Output to LLC in sequence and discard frame two
Fig. 41 Defragmentation (Multiply frames with one duplicate frame)

We assume there are four data frames that were received from PHY
layer. We list on Table 14. First, the module scans the AP in the three
channels and then starts to receive the data frames. Finally reassembly the
frame body and sent out to LLC. Fig. 42 shows the total simulation result and
Fig. 43 shows frame body data to LLC in order. The result is correct.

Table 14 Four data frames from PLCP layer
No
Frame
Control
Duration Address1 Address2 Address3
Sequence
Control
Frame Body FCS
1 2081H C400H AABBCCDDEEFFH 001122334455H 001122334455H 0001H 35724163H 9964104AH
2 2081H C400H AABBCCDDEEFFH 001122334455H 001122334455H 0002H 254468DBH 74EFF292H
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3 2081H C400H AABBCCDDEEFFH 001122334455H 001122334455H 0003H 33224567H F6100549H
4 20A1H C400H AABBCCDDEEFFH 001122334455H 001122334455H 0004H ABAC3421H 6CD0D5A5H

Data from PLCP CRC check fine

Gen ACK to TX part Data to LLC
Fig. 42 Full function simulated result


Data to LLC compared to Table 4.4 are correct
Fig. 43 Full function simulated result (To LLC data)
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4-2 Hardware full function verification and Results
We simulated all modules and ensured function of each module correct.
We can start to implement those modules on FPGA [15].
First we validated CRC32 module, scan and synchronization module and
fragmentation module by hardware. We used logic analyzer to probe and get
test results. We can ensure each module function before we integrated them in
full module. If have any issue we can narrow down issue quickly.
For CRC32 module, we test as Fig. 34 example again by hardware. Fig.
44 shows test result. Completed to Fig. 34 and result is similar. The function
of CRC32 module is workable of hardware.


Fig. 44 CRC32 got a correct RTS frame (Hardware)

For scan and synchronization module, we test as Fig. 36 example again
by hardware. Fig. 45 shows test result. Completed to Fig. 36 and result is
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similar. The function of scan and synchronization module is workable of
hardware part.

Fig. 45 Active Scanning success (Hardware)

For defragmentation module, we test as Fig. 39 example again by
hardware. Fig. 46 shows test result. Completed to Fig. 39 and result is similar.
We can ensure that function of scan and synchronization module is workable
of hardware part.
At last, we used hardware to validation as 4-1-4 section again. Even if
we used two emulation boards to design hardware we still need to create
schematic for our design. We attach our design, MAC receiver schematic of
appendix A-1. We only keep necessary circuit on our design schematic and
base on it to connect circuit. Form Spartan-3E Sample Pack board (as PHY to
output) to Spartan-3 Starter Kit (our design, MAC receiver) we use cable to
connect in reality.
66

Fig. 46 Defragmentation (Multiply frames with normal sequence,
Hardware)

Then verified sequence is doing synchronization first, verifying received
four data frames with CRC32, then responding with sending ACK to
transmitter, finally reassembling the data frames then send to LLC layer. We
can compare Fig. 42 to Fig. 47 and Fig 43 to Fig. 48. We got the same result.
Data to LLC are 35724163H, 254468DBH, 33224567H and
ABAC3421H in order as Table 14 list data that we input. The full function
of MAC receiver part is workable of hardware part. We realize MAC receiver
part by FPGA successfully [16].

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Fig. 47 Full function hardware tested result


Fig. 48 Full function hardware tested result (To LLC data)
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4-3 MAC Design Method Comparison
We make a MAC design method comparison table of Table 15. There
are three populate ways to design MAC. These are CPU-Base, FPGA and
vender total solution.

Table 15 MAC design method comparison table
Method
Development
time
Design
flexibility
Design
mobility
Speed/
Power
consume
Cost
CPU-Base
(Intersil 384,
ARM)
Short High Medium
Low /
High
High
FPGA Long High High
High/
Low
Low
Total
solution
(BMC4318,
RTL8186)
Medium Low Low
High/
Low
Medium

For the design flexibility, if you need other features that want to
implement in your design you can use reserved I/O to design. That will be
better than using total solution.
For design mobility, we used VHDL language to design and can
implement to all FPGA vendor. We can select a suitable one based on our
function or cost requirement.
For speed and power consumed FPGA has nice performance than
CPU-Base design [17].
For cost, because more and more people used FPGA to design network
protocol communication products, FPGA cost is cheaper than before. Some
69
chips only need 2US dollars.
Though we use FPGA to design will need more development time. We
can separate our design into several modules and make various people to
validate individual module in the same time. That can decrease development
time. Because of many good features we use FPGA to design MAC receiver.
Most people design FPGA by using Verilog language. We try to design
by using VHDL language. Both are IEEE standards and are supported by all
the major Electronic Design Automation (EDA) vendors. Both can be used
for designing Application-Specific Integrated Circuits (ASICs) and
simulating systems. However, VHDL support for system level modeling and
simulation is far more comprehensive than Verilog. We compare and contrast
individual aspects of the two languages of Table 16 [18] [19].

Table 16 VHDL/Verilog compared & contrasted
Property
Design
language
Compared & Contrasted
VHDL
Multiple design-units (entity/architecture pairs), that reside
in the same system file, may be separately compiled if so
desired. However, it is good design practice to keep each
design unit in its own system file in which case separate
compilation should not be an issue.
Compilation
Verilog
The Verilog language is still rooted in it's native
interpretative mode. Compilation is a means of speeding up
simulation, but has not changed the original nature of the
language. As a result care must be taken with both the
compilation order of code written in a single file and the
compilation order of multiple files. Simulation results can
change by simply changing the order of compilation.
VHDL
A multitude of language or user defined data types can be
used.
Data types
Verilog
Compared to VHDL, Verilog data types a re very simple, easy
to use and very much geared towards modeling hardware
structure as opposed to abstract hardware modeling.
70
VHDL
Procedures and functions may be placed in a package so that
they are avail able to any design-unit that wishes to use them.
Design
reusability
Verilog
There is no concept of packages in Verilog. Functions and
procedures used within a model must be defined in the
module. To make functions and procedures generally
accessible from different module statements the functions and
procedures must be placed in a separate system file and
included using the `include compiler directive.
VHDL
VHDL may seem less intuitive at first for two primary
reasons. First, it is very strongly typed; a feature that makes
it robust and powerful for the advanced user after a longer
learning phase. Second, there are many ways to model the
same circuit, specially those with large hierarchical
structures.
Easiest to
Learn
Verilog
Verilog is probably the easiest to grasp and understand.
VHDL
A library is a store for compiled entities, architectures,
packages and configurations. Useful for managing multiple
design projects.
Libraries
Verilog
There is no concept of a library in Verilog. This is due to it's
origins as an interpretive language.
VHDL
Configuration, generate, generic and package statements all
help manage large design structures. Managing
large designs
Verilog
There are no statements in Verilog that help manage large
designs.
VHDL
VHDL is a concise and verbose language; its roots are based
on Ada.
Readability
Verilog
Verilog is more like C because its constructs are based
approximately 50% on C and 50% on Ada.
VHDL
The generate statement replicates a number of instances of
the same design-unit or some sub part of a design, and
connects it appropriately.
Structural
replication
Verilog
There is no equivalent to the generate statement in Verilog.
VHDL
Because VHDL is a very strongly typed language models
must be coded precisely with defined and matching data
types. This may be considered an advantage or disadvantage.
However, it does mean models are often more verbose, and
the code often longer, than its Verilog equivalent.
Verboseness
Verilog
Unused bits will be automatically optimized away during the
synthesis process. This has the advantage of not needing to
model quite as explicitly as in VHDL, but does mean
unintended modeling errors will not be identified by an
analyzer.
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VHDL requires longer learning and is not so amenable to
quick-and-dirty coding but some properties for compilation, design
reusability, libraries, managing large designs and structural replication are
better than using Verilog to design FPGA. That is why we choose VHDL to
design MAC receiver part of FPGA in the thesis.

























72































73
CHAPTER 5

CONCLUSIONS

We implement IEEE 802.11 MAC receive controller by FPGA method
with VHDL langrage in this thesis and base on IEEE 802.11b/g specification.
For the architecture, it can realize the DCF function of receiver part and
ensure those functions are workable. We can use those modules and
implement in other vendors FPGA. For fulfilled that cost down and
customize requirement or other similar application.
VHDL is managing large designs better than Verilog. VHDL is a very
strongly typed language models must be coded precisely with defined and
matching data types. When we combine many peoples modules of one
design for FPAG. We can reduce compatible issue and development time.
Compared software simulation results to hardware test results and we
can find some timing difference. Designer needs to notice this issue. The
difference is caused by synthesizer when implemented to FPGA. Logic gates
will have delay time. Difference pin assign to FPGA will impact synthesized
results as well. That is why we dont show synthesized report because we
used venders development kit. We cant get the optimization gate counts.
Even though that we still can reached our goal. Realized IEEE 802.11b/g
MAC received controller. Because we used 50Mhz clock for design controller
of Spartan-3 Starter Kit that is faster than requirement of IEEE 802.11b/g
specific.
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The PCF MAC function is not realized in this thesis. In the future design,
we can implement PCF MAC function. Let our design more completely.
IEEE 802.11n can be our next research topic for future work as well.

























75
REFERENCES

[1] ,IEEE 802.11 : ,
,,
[2] , FPGA IEEE 802.11b/g ,
,,
[3] B. P. Crow, IEEE 802.11 wireless local area networks, IEEE
Communications Magazine, pp. 115-126, Sept. 1997.
[4] M. Gast, 802.11 Wireless Networks: The Definitive Guide, Second
Edition, OReilly, 2005.
[5] IEEE 802.11, IEEE wireless LAN medium access control (MAC) and
physical layer (PHY) specifications, Aug. 1999.
[6] T. J. Tsai & J. W. Chen, IEEE 802.11 MAC protocol over wireless mesh
networks: problems and perspectives, in Proc. Advanced Information
Networking and Applications, 19th International Conference, Volume 2, pp.
60-63, Mar. 2005.
[7] IEEE 802.11b, Wireless LAN medium access control (MAC) and
physical layer (PHY) specifications: High-speed Physical Layer Extension in
the 2.4GHz Band, IEEE Std 802.11b-1999.
[8] , FPGA IEEE 802.11b ,
,,
[9] Y. Kim, H. Jung, H. H. Lee & K. R. Cho, MAC implementation for IEEE
802.11 wireless LAN, Router Technology, Department, Electronics &
Telecommunications Research Institute, 2001.
76
[10] XILINX, Configurable LocalLink CRC Reference Design, Nov. 2004
[11] ,VHDL ,,
,,
[12] ,FPGA/CPLD-Xilinx ISE ,,
,,
[13] A. Ganz, A. Savvides & Z. Ganz, Media access control development
platform for wireless LANs, in Proc. International Conference on Electronics,
Circuits and Systems, Cyprus, 1999.
[14] T. H. Meng, Design and implementation of an all-CMOS 802.11a
wireless LAN chipset, Communication magazine, IEEE, Vol.41, No.8, Aug.
2003.
[15] H. Velayos & G. Karlsson, Techniques to reduce IEEE 802.11b handoff
time, in Proc. IEEE International Conference on Communications (ICC), June
2004.
[16] A. Yamada, A. Fujiwara & Y. Matsumoto, 66, Enhancement of mesh
network oriented IEEE802.11 MAC protocol, Wireless Laboratories, NTT
DoCoMo Inc, 2004.
[17] : What is difference between VHDL and Verilog ?, 20075
20http://malaysia.answers.yahoo.com/question/index
[18] : VHDL & Verilog Compared & Contrasted, 2007520
http://www.angelfire.com/in/rajesh52/verilogvhdl.html
[19] , ARM,
,,

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APPENDIX A
A-1 Medium Access Control receiver schematic























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