You are on page 1of 14

3.

6 DC BIASING CIRCUITS
dc analysis: to determine the values of base current, I
B
, collector current, I
C
, and voltage
between collector and emitter, V
CE
these values establish an operating point (also known as uiescent point, abbreviated !"
point# of the circuit
the !"point must be in the active region of the characteristics graph
the !"point (I
B!
, I
C!
, V
CE!
# is very important to ensure that the transistor operates in the
active region and the dc limits of operation, as given in the data sheet, are not being
e$ceeded
other related values: base voltage, V
B
collector voltage, V
C
and emitter voltage, V
E
%
3.6.1 Fixed-Bias Circuit
for the dc analysis, the capacitors are replaced with an open circuit euivalent
V
CC
&
B
&
C
v
i
v
o
I
B
I
C
'

V
BE
C
E
B
'
V
CE

C
B
C
C

V
CC
&
B
&
C
I
B
I
C
'

V
BE
C
E
B
'
V
CE

(a# (b#
Figure 3.11 Fixed-bias circuit (a C!"#$ete circuit% (b dc e&ui'a$e(t circuit
(")*
for the dc analysis, the circuit can be divided into base"emitter section (input# and
collector"emitter section (output#%
Base-e"itter Secti!(
+sing ,V-,
V
CC
. I
B
&
B
' V
BE
/olving for I
B
,
I
B
.
B
BE CC
&
V V
((%)#
C!$$ect!r-e"itter Secti!(
the collector current, I
C
is directly related to I
B
and is given as
I
C
. I
B
((%0#
using ,V-,
V
CC
. I
C
&
C
' V
CE
solving for V
CE
,
V
CE
. V
CC
I
C
&
C
((%(#
the base voltage, collector voltage and emitter voltage are measured with reference to
ground where1
V
B
. V
BE
1 V
C
. V
CE
, V
E
. *
)xa"#$e 3.1 &eferring to 2igure E(%), determine I
B!
, I
C!
, V
CE!
, V
B
, V
C
and V
B
%
("))
30* k
)4 V
. )(*
)%4 k
Figure )3.1
S!$uti!(*
2rom euation ((%)#, I
B!
.
56 *4 % (3
k 30*
7 % * )4
=

2rom euation ((%0#, I


C!
. ()(*#((3%*4 5# . 3%3( m6
2rom euation ((%(#, V
CE!
. )4 (3%3( m#()%4 k# . 8%(9 V
V
B
. V
BE
. *%7 V1 V
C
. V
CE
. 8%(9 V, V
E
. *
Tra(sist!r Saturati!( +e'e$
In the saturation region (refer to 2igure (%8#, the value of collector current for a particular
configuration is at ma$imum and the value of collector to emitter voltage, V
CE
is nearly * V% :his
ma$imum collector current is called saturation current, I
Csaturation
and must be lower than the
ma$imum collector current specified in the data sheet% :he resistance between collector to
emitter, &
CE
is very low and can be assumed to be ;ero ohm%
+!ad $i(e a(a$,sis
<iven the output characteristics of B=:, as shown in 2igure (%)0, we can also determine I
C!
and
V
CE!
using load line analysis% :he steps are as follows%
)% Calculate base current using euation ((%)#%
(")0
0% >etermine ma$imum collector current, I
Csaturation
and ma$imum collector to emitter voltage
V
CEma$
using euation ((%(#%
I
Csat
.
C
CC
&
V
when V
CE
. * """"" point 6
V
CEma$
. V
CC
when I
C
. * """"" point B
-abel these points on the characteristics graph%
(% >raw the load line by connecting the point 6 and point B%
3% :he intersection of the load line and I
B!
will give the values of I
C!
and V
CE!
%
Figure 3.1-
)xa"#$e 3.- +sing load line analysis, determine I
B!
, I
C!
and V
CE!
for the circuit in 2igure E(%)%
+se the output characteristics in 2igure (%)0%
S!$uti!(*
)% Calculate I
B!
% I
B!
.
56 *4 % (3
k 30*
7 % * )4
=

(")(
0% >etermine I
Csaturation
and V
CEma$
%
I
Csat
.
k )%4
)4
. )* m6
V
CEma$
. V
CC
. )4 V
(% -abel the two points and draw the load line% :he load line and the !"point are shown in
2igure E(%0%
3% 2rom graph, the !"point are
I
C!
. 3%9 m61 V
CE!
. 8%4 V
Figure )3.-
3.6.- )"itter-Bias Circuit
for the dc analysis, the capacitors are replaced with an open circuit euivalent
(")3
V
CC
&
B
&
C
v
i
v
o
I
B
I
C
'

V
BE
C
E
B
'
V
CE

&
E
I
E
C
B
C
C
C
E

V
CC
&
B
&
C
I
B
I
C
'

V
BE
C
E
B
'
V
CE

&
E
I
E
(a#
Figure 3.13 )"itter-bias circuit (a C!"#$ete circuit% (b dc e&ui'a$e(t circuit
Base-e"itter Secti!(
using ,V-,
V
CC
. I
B
&
B
' V
BE
' I
E
&
E
substituting I
E
. (? ' )# I
B
,
V
CC
. I
B
&
B
' V
BE
' (? ' )# I
B
&
E
solving for I
B
,
I
B
.
E B
BE CC
)#& ( &
V V
+ +

((%3#
C!$$ect!r-e"itter Secti!(
using ,V-,
V
CC
. I
C
&
C
' V
CE
' I
E
&
E
solving for V
CE
,
V
CE
. V
CC
I
C
&
C
I
E
&
E
((%4#
using the appro$imation, I
C
I
E
,
V
CE
. V
CC
I
C
(&
C
' &
E
# ((%9#
(")4
the emitter voltage
V
E
. I
E
&
E
((%7#
using ,V-,
V
B
. V
BE
' V
E
((%8#
V
C
. V
CE
' V
E
((%@#
the collector voltage can also be calculated using the following euation
V
C
. V
CC
I
C
&
C
((%)*#
)xa"#$e 3.3 &eferring to 2igure E(%(, determine I
B!
, I
C!
, I
E
, V
CE!
, V
E
, V
B
and V
C
%
30* k
0* V
. )0*
)%0 k
*%8 k
Figure )3.3
S!$uti!(*
2rom euation ((%3#, I
B!
.
56 39 % ((
k# ()0)#(*%8 k 38*
7 % * 0*
=
+

2rom euation ((%0#, I


C!
. ()0*#(((%39 5# . 3%*0 m6
I
E
3%*0 m6
(")9
2rom euation ((%9#, V
CE!
. 0* (3%*0 m#(0 k# . ))%@9 V
2rom euation ((%7#, V
E
. (3%*0 m#(*%8 k# . (%00 V
2rom euation ((%8#, V
B
. *%7

' (%00 . (%@0 V
2rom euation ((%@# V
C
. ))%@9

' (%00 . )4%)8
+!ad $i(e a(a$,sis
Ae can also determine the !"point (I
C!
and V
CE!
# for emitter"bias using load line analysis% :he
steps are as follows%
)% Calculate base current using euation ((%3#%
0% >etermine, I
Csaturation
and V
CEma$
%
I
Csat
.
E C
CC
& &
V
+
when V
CE
. *
V
CEma$
. V
CC
when I
C
. *
-abel these points on the characteristics graph%
(% >raw the load line by connecting the two points%
3% :he intersection of the load line and I
B!
will give the values of I
C!
and V
CE!
%
)xa"#$e 3.. +sing load line analysis, determine I
B!
, I
C!
and V
CE!
for the circuit in 2igure E(%(%
:he output characteristic is given in 2igure (%)0%
S!$uti!(*
)% Calculate I
B!
% I
B!
.
56 39 % ((
k# ()0)#(*%8 k 38*
7 % * 0*
=
+

0% Calculate I
Csaturation
and V
CEma$
%
I
Csat
.
k *%8 k )%0
0*
+
. )* m6
V
CEma$
. V
CC
" V
CE
. 0* B (I
C
&
E
#
(% :he load line and the !"point are as shown in 2igure E(%3%
3% 2rom graph, the !"point1
I
C!
. 3%3 m61 V
CE!
. )) V
(")7
Figure )3..
3.6.3 /!$tage-di'ider Bias Circuit
for the dc analysis, the capacitors are replaced with an open circuit euivalent

V
CC
&
)
&
C
v
i
v
o
I
B
I
C
'

V
BE
C
E
B
'
V
CE

&
E
I
E
C
B
C
C
C
E
&
0

V
CC
&
)
&
C
I
B
I
C
'

V
BE
C
E
B
'
V
CE

&
E
I
E
&
0
(a# (b#
Figure 3.1. /!$tage-di'ider bias circuit (a C!"#$ete circuit% (b dc e&ui'a$e(t circuit
two methods of dc analysis: e$act analysis and appro$imate analysis
(")8
)xact A(a$,sis
determine :heveninCs euivalent circuit looking from base"emitter section

V
CC
&
)
I
B
'

V
BE
&
E
I
E
&
0

&
:D
I
B
'

V
BE
&
E
I
E
V
:D
(a# (b#
Figure 3.10 (a Base-e"itter secti!(% (b T1e'e(i(2s e&ui'a$e(t circuit
:hevenin voltage, V
:D
.
# V (
& &
&
CC
0 )
0
+
1
:hevenin euivalent resistance, &
:D
.
0 )
0 )
& &
& &
+
applying ,V- to the :heveninCs euivalent circuit,
V
:D
. I
B
&
:D
' V
BE
' I
E
&
E
/ubstituting I
E
. (? ' )# I
B
,
V
:D
. I
B
&
:D
' V
BE
' (? ' )# I
B
&
E
solving for I
B
,
I
B
.
E :D
BE :D
)#& ( &
V V
+ +

((%))#
C!$$ect!r-e"itter Secti!(
(")@
similar to collector"emitter section of emitter"bias circuit
therefore the euations obtained for emitter"bias circuit can be used for voltage"divider
bias circuit%
V
CE
. V
CC
I
C
&
C
I
E
&
E

or V
CE
. V
CC
I
C
(&
C
' &
E
#
V
E
. I
E
&
E

V
B
. V
BE
' V
E
V
C
. V
CE
' V
E
the base voltage can also be calculated using the following euation
V
B
. V
:D
I
B
&
:D
((%)0#
)xa"#$e 3.0 &eferring to 2igure E(%4, determine I
B!
, I
C!
, I
E
, V
CE!
, V
E
, V
C
and V
B
%
v
o
03 V
*%8 k
0%0 k
) 2
8%8 k
. ))*
43 k
v
i
00 2
)* 2
Figure )3.0
S!$uti!(*
)% Calculate V
:D
and &
:D
%
V
:D
.
# 03 (
k 43 k %8 8
k 8 % 8
+
. (%(9 V
&
:D
.
k 3 4 k 8 % 8
# k 43 #( k 8 % 8 (
+
. 7%47 k
0% >raw :heveninCs euivalent circuit%
("0*
*%8 k
7%47 k
'

V
BE
(%(9 V
Figure )3.0(a
(% Calculate I
B!
%
I
B!
.
k# ()))#(*%8 k 47 % 7
7 % * (9 % (
+

. 07%9* 6
2rom euation ((%0#, I
C!
. ())*#(07%9* 5# . (%*3 m6
I
E
I
C!
. (%*3 m6
2rom euation ((%9#, V
CE!
. 03 ((%*3 m#(( k# . )3%88 V
2rom euation ((%7#, V
E
. ((%*3 m#(*%8 k# . 0%3( V
2rom euation ((%@#, V
C
. )3%88

' 0%3( . )7%() V
2rom euation ((%)0# V
B
. (%(9

(07%9* 5#(7%47 k# . (%)4 V
A##r!xi"ate A(a$,sis
&eferring to base"emitter section of voltage divider bias in 2igure (%)4(a#, the appro$imate
analysis is carried out by assuming the base current, I
B
*% :he assumption is
true if the following condition is satisfied%
&
E
)*&
0
:he base voltage is eual to the :hevenin voltage and can be determine from euation ((%)0#%
V
B
. V
:D
I
B
&
:D
. V
:D
=
# (V
& &
&
CC
0 )
0
+
:he appro$imate analysis can be carried out with the following steps%
)% :est whether the condition &
E
)*&
0
is satisfied%
0% Calculate base voltage%
("0)
V
B
. V
:D

(% Calculate emitter voltage and emitter current%
V
E
. V
B
V
BE
1 I
E
.
E
E
&
V
3% >etermine the !"point%
I
C!
I
E
1 V
CE
. V
CC
I
C
(&
C
' &
E
#
)xa"#$e 3.6 >etermine I
C!
and V
CE!
for the circuit in 2igure E(%9 using appro$imate analysis%
S!$uti!(*
)% :est whether the condition &
E
)*&
0
is satisfied%
&
E
. ())*#(*%8 k# . 88 k
)*&
0
. )*(8%8 k# . 88 k
:herefore the condition &
E
)*&
0
is satisfied%
0% Calculate base voltage%
V
B
. V
:D
=
# (V
& &
&
CC
0 )
0
+
.
# 03 (
k 43 k %8 8
k 8 % 8
+
. (%(9 V
(% Calculate emitter voltage and emitter current%
V
E
. (%(9 *%7 . 0%99 V1 I
E
.
k *%8
99 % 0
3 (%(( m6
3% >etermine the !"point%
I
C!
I
E
. (%(( m6 (compare to I
C!
. (%*3 m6 using e$act analysis#
V
CE!
. 03 ((%(( m#(( k# . )9%97 V
(compare to V
CE!
. )7%() V using e$act analysis#
+!ad $i(e a(a$,sis
("00
:he output section of voltage divider bias circuit and the output section of emitter bias circuit are
the same% :herefore the load line analysis for voltage"divider bias circuit is the same as the load
line analysis for emitter"bias circuit%
("0(

You might also like