Challenges in Development, Manufacturing and Use of Underfill in Flip Chip Package

Jason Strader, Xijin Chen, Gautham Vevarakonda and The Duong Arizona State University Ira A. Fulton Schools of Engineering P.O. Box 879309 Tempe, AZ 85287-9309 Phone: 480-965-1726 Email: engineering@asu.edu encapsulate the bottom side of a silicon chip. Encapsulate in this context means covering the fragile interconnects between the chips bottom side and the PCBs top side. The introduction of underfill has given the solder interconnection technology an unprecedented mechanical integrity and a significant increase in solder fatigue resistance. The major trend in electronic products today is to make them smaller, lighter, smarter, thinner, shorter and faster whereas maintaining the functionality, reliability and robustness of the device at low costs.

ABSTRACT Flip chip technology is a packaging approach to meet high input/output count due to its area of interconnection onto substrate, which is becoming a mainstream technology to package for cheaper, smaller, lighter and higher reliability electronic devices. Underfill, which is used to enhance the solder joint fatigue reliability of a flip chip device, is critical to the reliability of the area array technologies. This paper illustrates the challenge in development, manufacturing and use of underfill in flip chip packages, focusing on the challenges in development, materials and technologies used in current underfill processes and future trends for underfill technologies. A stage gate system is introduced to illustrate the challenge of development of underfill materials and several manufacturing challenges are mentioned according to different underfill materials. In this paper, material properties and current underfill technologies, such as convectional underfill, no-flow underfill and molded underfill are noticed to give an overview of underfill technology. Based on the current trend of underfill materials and requirements from industry, some future technologies for underfill materials are introduced. KEY WORDS: Underfill, Flip Chip, Packaging, Material, Epoxy, Integrated Circuit (IC), Coefficient of Thermal Expansion (CTE), inout-output (I/O) INTRODUCTION The use of flip-chip technologies to package electronics first emerged in the late 1960s. Flip-chip packaging offers a number of crucial advantages, including a higher number of input-outputs (I/Os), a smaller integrated circuit (IC) footprint, an improved electrical performance, an increased reliability, and a low cost. Consequently, flip-chip packaging has been instrumental in facilitating the trend toward small, lightweight, and high-performance electronic devices. Advances in the techniques and materials employed in the underfill process have played a key role in ensuring the widespread application of flip-chip packaging. Since its inception at IBM in the 1970s, under-fill technology has been a very important part of electronics manufacturing. The usage of underfills was widely adopted after industry shifted from using ceramic substrates to organic substrates. The traditional underfill packaging procedure is shown in Figure 1. The function of an underfill is to

Fig.1 Cross section of tradition flip-chip underfill packaging The invention on the solder joint was one of the most innovative developments to enable the use of low-cost organic substrates in flip-chip packages. This paper reviews emerging challenges of the underfill processes including new requirements of thermal mechanical properties for underfill. The paper also briefly reviews the use and application of various underfill technologies including materials for conventional underfill, no flow underfill and molded underfill. The development and manufacturing of underfill is also discussed followed by future technologies. BACKGROUND AND CURRENT UNDERFILL PROCESSES Underfill material property and selection Reliability is the major concern in flip chip packaging, which leads to the need for the right selection of underfill material based on its properties such as Coefficient of thermal expansion (CTE), viscosity, flow characteristic, modulus and adhesion. The CTE of an underfill material should match with that of solder bump. The two types of normal solder bumps are Pb5Sn (29 ppm) and Eutectic (24.3 ppm). The CTE of underfill can be adjusted by varying the amount of silica filler (typically between 60-65%) and the polymer chemistry. As

glass transition temperature of polymer is exceeded, the CTE increases. Therefore, the is chosen to be greater or equal to to maintain the underfill CTE matching that of the chip throughout reliability testing between to . As the dispensing system can handle a limit degree of viscosity variation, the viscosity of underfill has to be such that the material has room temperature pot life extending more than one shift at the IC assembly line as well as a reasonable shelf life. Filler settling occurs when the viscosity of the underfill becomes too low to hold the filler as a suspension. This occurs when the temperature of the underfill is raised beyond the recommended flow temperature or if the base chemistry is not able to keep the filler buoyant. The flow characteristic of an underfill is represented by the time it takes in the capillary underfill process:

Table 1: Performance indicators taking into consideration your package type and process conditions [1] Current underfill processes Underfill process is primarily governed by the capillary flow of the material under the die. Underfilling is considered a slow process in the flip-chip assembly line. In order to increase the speed of the underfilling process, packages are typically heated from the substrate side thereby reducing the viscosity of the material. A typical Underfill Process consists of the following steps. 1. Pre-baking of package for moisture removal 2. Dispensing at elevated temperature 3. Underfill flow under die 4. Curing at elevated temperature of underfill, coupling the die and the substrate [5]

Where is the time taken to reach a distance under the die, is the surface tension of the liquid-vapor interface while is the viscosity, h is the bump height, and is the contact angle between the underfill and the surface. From the equation, the process window of the underfill flow is proportional to the square of the distance. Since the viscosity of underfil is a function of temperature, the process window also depends on the temperrature at which the flow is done. Additionally, the size and distribution of filler have an impact on the speed of the underfill flow. Pratically, the largest size of the filler particle should be smaller than one third of the solder bump size to ensure smooth flow. The underfill flow is also affetced by the surfaces it comes in contact with: the substrate surface and the underside of the die. Flux residue after the reflow of the solder bumps may interfere with the underfill flow, which leads to the presence of voids and delamination after cure. After the underfill flow process, the underfill is cured. The curing profile of the underfill material must be optimized with the option of the oven for a shorter curing time. After the curing process, the modulus of underfill must satisfy two requirements; it should be low enough to relieve the stress between the die and the subtrate during reliability testing; it should be high enough to maintain the coplanarity of the package and relieve the stress from the solder bumps. Based on these requirements, the modulus (E) of underfill material is also important. While below the glass transition temperature, should be between 7 GPa and 10 GPa. When the underfill exceeds its glass temperature, should be close to 7GPa. Another important property of underfill material is the adhesion of underfill to the die, solder bumps and substrate to prevent delamination of the flip chip packgage. Table 1 lists some performance indicators of undefill material. The values in the table are only indicators, the actual optimized values should be chosen based on the type of package and process conditions.

Fig 2: Typical Underfill process Various underfill processes and the material properties required for each process are discussed in the subsequent sections. Conventional underfill Figure 2 shows the process steps of flip-chip with conventional underfill. It can be seen from the figure that separate flux dispensing and cleaning steps are required before and after assembling of the chip. In this process, after the chip is assembled onto the substrate, the underfill is dispensed into the gap between chip and substrate by capillary force. The capillary flow is usually slow and can be incomplete. The incomplete underfilling process results in formation of voids under the die resulting in lower reliability of the package. The curing of underfill takes a long time consuming additional manufacturing time. Another disadvantage with this process is that as the gap distance decreases flux cleaning becomes difficult.

cleaning steps. Also, it avoids the capillary flow of underfill combining the solder bump reflow and underfill curing into a single step. This improves the production efficiency of the underfill process.

Fig 3: Conventional Underfill process The critical properties of underfill materials that impact capillary flow are: 1. Viscosity of material 2. Surface tension of the material at dispense temperature 3. Contact angle of the underfill material to both solder resist and die passivation material 4. Cure kinetics The problems mentioned above are intensified further with the increase in dimensions of chip and I/O counts, and decrease in gap distance and pitch sizes. In order to mitigate these problems various methods have been suggested which include pressurized underfill encapsulation, vacuum assisted underfill process and raised die underfill process. In the first process, the underfill is injected in the mold cavity at higher pressure and temperature which shortens the filling time by two to three times. In the second process, the flow of underfill is assisted with vacuum applied by a shroud device placed closed to the gap between the chip and the board. Gravity is utilized to assist the underfill flow in the last process. One end of the flip-chip is position so that it is elevated on an inclined plane. The underfill is dispensed at the elevated end and a barrier is used at the other end to prevent overflow. These approaches however are not widely adopted by the industry. To overcome the disadvantages of conventional underfill processes new techniques like no-flow underfill, molded underfill and wafer level underfill have been suggested.[2][5] No-flow underfill Figure 3 illustrates the process steps involved. In this process, instead of dispensing the underfill after chip assembly, the dispensing is done onto the substrate before placement of the chip. The chip is then placed onto the substrate and the whole assembly goes through solder reflow, where the interconnections are established. The advantage of this process is that it eliminates separate flux dispensing and

Fig 4: No-flow Underfill process In order to successfully implement this process, the underfill material should possess two critical properties latent curing ability and built-in fluxing capability. The underfill should have enough reaction latency to maintain low viscosity. Also, since in this process the underfill is dispensed before the chip placement, it is important that the material has self-fluxing capability to facilitate solder wetting. Even though the noflow underfill process provides many advantages over the conventional process, it is limited due to its ineffectiveness in eliminating void formation. Voids can be formed due to moisture in the board, out-gassing of underfill, etc. Voids are highly undesirable as they lead to high stress concentrations near solder bumps, underfill delamination and solder extrusion. The important process parameters that affect underfill voids in a no-flow process are the solder mass design, the underfill dispensing pattern, the reflow profile and the placement force and speed. In cases using a small circuit board, as the temperature distribution is more homogeneous, it is relatively easy to avoid voids using the right combination of material and process parameters. However, for complex assemblies, the optimization of reflow process is difficult. The reliability of no-flow underfill packages can be enhanced by preventing underfill cracking in the thermal cycle. Also, low modulus materials decrease stress in the underfill. However, this diminishes the role of the underfill as a stress re-distribution layer and hence cannot prevent solder joint failure. With no-flow underfill, the key is underfill material has two critical properties; latent curing ability and built-in fluxing capability. [2] Why latent curing ability: so that the underfill can maintain its low viscosity until the solder joints are formed. If not, gelled

underfill would prevent the melting solder from collapsing onto the contact pads, which will resulted in low yield of the solder joint. Why built-in fluxing capability: fluxing is used to reduce and eliminate the metal oxide on the solder and to prevent it from being reoxidized under high temperature. Noflow under fill is dispensed before the chip placement (no flux dispensing as the conventional method); hence self-fluxing capability is required to enhance the solder wetting. Typically an epoxy-based encapsulant is chosen for the no-flow underfill material. Some advantages of epoxy resins are low-cost, adjustable curing temperature and curing rate (by selecting proper catalyst) and good adhesion to most substrates. Figure 4 shows that the typical reflow profile of Sn/Pb solder bumps consists of 4 temperature zones: preheating, soaking, reflow and cooling. The successful no-flow underfill should behave correctly at each temperature zone. In the preheating zone, the no-flow underfill material should drastically drop its viscosity and then maintain the low viscosity so that the underfill material can wet all contact surfaces and the chip can easily compress down by its own weight via gravity to contact the solder bumps and copper pads. In the soaking zone, the material should provide fluxing capability to remove the metal oxide at the surface of solder bumps and copper pads. In the reflow zone, the material should remain flowable until the completion of solder reflow. The underfill should be cured at a temperature below the melting point of solder bumps. In the cooling zone, the cured material should have reasonable CTE, modulus, toughness, and adhesion strength so that the cured material and any other components of the assembly will not crack and delaminate. [4]

whole chip. This process reduces process time, improves mechanical stability and provides higher reliability because it utilizes an epoxy molding compound (EMC). When compared to a conventional underfill, molded underfill has much higher silica content which offers a low CTE closer to that of the solder joint. Another advantage with molded underfill is an increased production rate which is close to four times that of the conventional process. In process, molded underfill resembles the pressurized conventional underfill process except that the liquid encapsulates are replaced by the molding compounds.

Fig 6: Design of flip chip BGA with molded underfill. One of the challenges of such a design is that air might get trapped under the chip due to higher resistance to mold flow resulting in voids. However, this can be easily overcome by using mold vents and using geometrical optimization to create similar flow resistance over and under the chip. Even though it requires a special design on the substrate, this process is robust and is commonly adopted. Molding temperature, clamp force and injection pressure are the most important parameters in this process. Higher temperature is always preferred to achieve low viscosity and better flow properties. However, the molding temperature should not exceed the melting point of solder material because as the temperature nears the melting temperature, the solder might melt and there is a risk of the die being swept away from the site. Another disadvantage is that, at high injection pressure, bump and die cracking are most likely to occur. Even with these disadvantages, with some effort in material selection, mold design and process optimization, this process provides higher reliability and cost reduction. [2][5] DEVELOPMENT AND MANUFACTURING Challenges in development of any material including underfills are typically addressed through a stage gate system. A stage gate system contains milestones or stages during the design and development process to ensure the project is progressing smoothly and that the product is meeting design criteria. A series of meetings are held and in order to progress to the next stage a gate must be passed at these meetings. Each gate has a set of required criteria that must be met before moving on to the next stage. Once all stages have been completed, the product is considered to be complete and ready for product release and sale. Examples of the possible stages are shown in figure 6. Sampling to customers for evaluation of ease of use, properties and reliability during the development process may be required to ensure a robust product is being developed. [6][7]

Figure 5: Typical heating profile of eutectic Sn/Pb solder bump [2] To enhance the reliability via low CTE and high modulus, silica fillers are included into underfill. However, the filler may interfere with the solder joint formation and lower the yield of the solder joint. Therefore, commercial no-flow underfills contain no filler, which makes its CTE much higher than conventional underfill. [2], [5] Molded underfill This process is a result of combination of over molding and the underfill. Molded underfill is applied via a transfer molding process during which the molding compound fills the gap between the chip and substrate and also encapsulates the

Figure 7: Example of stage gate process flow Stage zero A Business opportunity evaluation (BOE) is completed. A BOE is populated by the marketing team with some inputs from the technical department. The composition of a BOE typically includes the size of market, if there is adequate space for a new underfill product, percent market share expected, time of return on investment, etc. The team must rely on reports from outside services and exhaustive searches of competitive companies and customers for this information. The BOE is presented to management and if approved, the project can move on to stage one. [6] [7] Stage one Stage one can be particularly challenging since all of the properties of the underfill will need to be defined and recorded in a product design sheet (PDS) or product spec sheet (PSS). The properties must make the material competitive in performance, price and ease of use. To obtain and define what these properties need to be, customer interviews and competitive product reviews are conducted. Unfortunately, customers may be giving you their wish list for properties instead of acceptable properties that ma y make the project more difficult. Many times the competitors latest and greatest materials are not publically listed in brochures and customers who use them typically do not divulge information about them as it may cause them to lose a competitive edge if a supplier who is developing a new material shares the properties with another customer (a competitor to them). Therefore the materials defined properties may be one step behind the market if thorough research and information gathering is not conducted. A gate meeting is held once the PDS is competed. The PDS may be accepted as is or modifications may be made to some of the properties. Once the PDS is approved, the project can move on to stage two. In rare occasions it may be determined that the project is outside the scope of capabilities and will be scrapped or at least go back to the defining phase and the PDS will need to be rewritten.[6][7] Stage two Stage two may be broken into two parts; stage two A, feasibility and stage two B, robustness.

Two A: formulation feasibility During this part of stage two the challenge is now to meet the parameters listed on the product design sheet. This is where materials and material properties become extremely important. To ensure the PDS properties are realistic further research of competitive materials is conducted. This typically includes obtaining and evaluating them. Obtaining the newest and best competitive material is quite difficult. Potential formulations from previous work, patents and other literature are investigated. If the product under development appears to be novel, patent searches need to be made to ensure not to infringe on competitive patents. If no exiting patents or public information exist regarding the novel material, a patent application may be submitted. Next, various formulations will be made and tested based these PDS properties. In the case of underfill, these properties are particularly challenging. Some challenges that must be overcome, the potential issue if they are not overcome and potential failure if not overcome are listed in table 2 below. Note that this table is not all encompassing.

Table 2: List of challenges, issues and potential failure Other obstacles include raw material cost and availability for state of the art materials and competitive patents preventing utilization of certain technologies and materials. Methods to overcome the challenges listed in table 2 include proper surfactants, coupling agents, choice of filler, selection of base resin, catalyst type and amount and techniques used to combine/mix these components. [6], [7], [8], [9], [10], [11], [12] Two B: formulation robustness A design of experiments (DOE) is typically used to ensure a robust formulation. This consists of making several batches varying all of the raw material components either in amount and/or in lot number used. It can be quite challenging to obtain various lot numbers of the raw materials that span the entire range of the quality specifications for that material however this is necessary to ensure that the underfill is robust and can be manufactured with different lots of raw materials and still maintain the intended properties. If all properties meet the PDS after the DOE is completed some scale up batches are completed to ensure the formulation can be made on a larger scale. If scale up is successful a gate meeting is held. If all gate criteria are met the project moves on to stage three, if criteria are not met, they are either accepted as

changes to the PDS or the material formulation needs to be altered and the gate will be re-held once the formulation meets the requirements. [6], [7] Stage three Production trials will be made using the final formulation from stage two B. Tweaks to the formulation may be made to ensure properties are met. A process DOE is typically used to vary process steps to ensure a robust manufacturing procedure. Due to the increasesd size of manufacturing equipment and variations in equipment tolerances, issues not found in the laboratory may be fleshed out. These may include filler settling, changes in final properties due to inhomogeneity, long production times and issues handling and packaging the underfill. Other challenges may include unreasonable or difficult raw material storage or an unforeseen need for new expensive manufacturing equipment. Once a predetermined amount of batches have been completed that meet requirements and the DOE is completed a gate meeting will be held. Any manufacturing issues will be addressed and if acceptable the gate will pass. If any criteria are not met the gate will fail and the project may be pushed back to stage two or stage three will be repeated until all issues have been resolved. During this stage, reliability is usually started to ensure that the material will maintain its intended properties under accelerated testing conditions. The challenge here lies in running the correct accelerated tests that will be accepted by customers. These tests, although accelerated, may still require a few months to complete making it essential to choose the correct tests so that testing will not need to be restarted. Sales and marketing materials are also drawn up and released to the public and customers. Of course, making ones product attractive to customers is always a challenge. [6], [7], [8], [9], [10],[11],[12] Stage four: testing and validation After the product has been manufactured for a set period of time or after a set number of batches (typically thirty) have been produced, all quality control data from production made batches is reviewed to ensure the product has been repeatedly meeting specifications. Control limits or specification limits that would have been set during scale up in stage three may be modified if required. If the material is not meeting critical design properties, formulation or processing adjustments may be made or the properties that are not meeting specification may be accepted. Some issues that may be found that will need to be overcome include; increase in raw material costs resulting in the product cost increasing and eroding profits, the material no longer meets required parameters resulting in a quality risk or recalls, high scrape rates causing long lead timesandreducedprofits.[6],[7] Manufacturing Challenges As with any material there are several challenges to manufacturing that include; staffing, procurement, logistics, work flow, equipment malfunction, packaging, storage and shipping. Depending on the type of underfill material, these steps can be complicated with need for refrigeration, hermetic

packaging, special filling/dispensing equipment and expensive shipping methods. [6], [7] FUTURE TRENDS With more complex requirements in underfill industry, new ideas and technologies in underfill materials are needed. Most of these new advanced technologies are in progress; their advantages tend to make flip-chip packaging lower cost and higher reliability. Among the new technologies, four underfill techniques illustrated in figure 6 are making great progress with the development of materials and equipment. Future technologies/ materials Molded Underfill Advantages Challenges

Wafer-level underfill LOCTITE ECCOBOND UF 8840 Pre-applied Underfill

Lower material cost and excellent reliability Low cost and high reliability High flexibility and compatibility Fast flow rate and quick cure time

Mentioned in MUF part Mentioned in WUF part High cost for manufacturing

Specialized equipment involved Fig 8: Advantages and Challenges of four future technologies Capillary Underfill (CUF) has been the cornerstone of todays flip chip technology in both BGA and CSP format. But, with the need for reducing package assembly cost, lower material cost and faster through put processes, new generation technology for underfill processing is needed. Compared with CUF, molded underfill (MUF) approach offers a solution to current technical problems with promising advantages, such as lower material cost and excellent reliability. Mold underfill assembly concept uses a single step approach to both underfill and over mold the die during the same mold shot which makes process simpler and faster. Due to more stringent requirements and its CTE, mold materials intend for use as MUF are not commonly used in the market. MUF materials need to be capable to fill in fine gap which tend to be 150 to 180 without trapping voids under the flip chip die. As for CTE, MUF materials are required to lower CTE and minimize CTE mismatch between silicon and substrate. In order to fulfill these two requirements posed on MUF, a finer filler size is chosen along with vacuum assisted molding to help with the molding process.

Figure 9: Package Design Rules with Clearance Requirements for flip chip Sip with MUF. [13]

Although, molding process is quite mature and established, MUF materials have some unique properties which require special controls during high volume manufacturing. Waxing frequency and mold flash control were particularly addressed during production mode. Insufficient waxing could lead to difficulties in the release function of the molded strip and pose risk of damaging the device or package. Also, limitation of MUF may affect its development which lies in its relatively narrow scope to encompass a wide range of die and package sizes. Thus expand the scope of MUF to larger die sizes is needed in future development work. As mentioned earlier, MUF can provide significant cost saving in assembly. Due to inherently more complex nature of CUF materials requiring more expensive ingredients and more complex manufacturing processes, the cost benefits of MUF is apparent. Therefore, the design and cost benefit with MUF were weighed against its technology limitation to establish a best-fit package scope for MUF and to define future work. Another future technology that needs to be mentioned is wafer level underfill, which is still a relative new concept and research is still in the material development stage. Wafer level underfill was proposed as an SMT-compatible flip-chip process to achieve low cost and high reliability. As illustrated in the figure 10, the underfill is applied to a bump wafer using printing or coating methods. Later, the underfill is B-staged and the wafer is cut into single chips. If the wafer is unbumped, it has to be bumped before the dicing is done. The individual chips are then placed onto the substrate.

production flip chip assembly, others underfill technologies such as no-flow underfill, molded underfill and wafer-level underfill have been developed and applied in the industry. There are emerging challenges of underfill technology development, material selection and manufacturing. All these challenges require close cooperation between the material supplier, the chip designer and manufacturing factory. A high level understanding of the materials, the processes utilizing these materials and their inter-relationship is required for a successful package. ACKNOWLEDGEMENTS The authors wish to acknoweldge Professor Amenah Tasooji, Arizona State universiy, for her valuable lectures and coaching. We also recognize Dr. Richard F. Hill, Vice President of Technology, Laird Technologies and Dr. Do Le Minh Khoa, Test Engineering GL, Intel Products Vietnam for their supports during the curse of this project. REFERENCES [1] Ignatius J. Rasiah, Selecting an underfill for flip chip package, Electronics Engineer May 1999. [2] Zhuqing Zang and C.P. Wong, Recent Advances in Flip Chip Underfill: Materials, Process, and Reliability, in IEEE Transactions on Advanced Packaging, Vol. 27, No. 3, August 2004 [3] C. P. Wong, Songhua H. Shi and G. Jefferson, High Performance No-Flow Underfill for Flip-Chip Application: Material Characterization, IEE Trans. Comp., Packag., Manufact. Technology. A, Vol 2 [4] Lejun Wang, C.P. Wong, Recent Advances in Underfill Technology for Flip-Chip, Ball Grid Array, and Chip Scale Package Applications, 2000 Intl Symp on Electronic Material & Packaging [5] M. Datta, Tetsuya Osaka and J. Walter Schultze, MicroElectronic Packaging (Dec 20, 2004) [6] Laird Technologies TTM product and process Development procedure # A13262-00 Rev. L [7] Jason L. Strader of Laird Technologies Thermal business unit product development team [8] Drs. Sandeep Tonapi and Brad Reitz, Flip -Chip Underfill: Design and Material Challenges, Chip Scale Review, Feb. 2004. [9] Dr. Ken Gilleo, The Chemistry and Physics of Underfill, ET-Trends [10] Dr. Ignatious J. Rasiah, Selecting and Underfull for Flip Chip Packaging, Electronics Engineer, May 1999 [11] Tim Chen, Jinlin Wang and Daoqiang Lu, Emerging Challenges of Underfill for Flip Chip Application, 2004 Electronic Components and Technology Conference [12] Shijian Luo and C. P. Wong, Moisture Absorption in Uncured Underfill Materials, IEEE Transactions on Components and Packaging Technologies, Vol. 27, No. 2, June 2004 [13] Lee J.Y., et al, Molded Underfill Development for FlipStack CSP, Amkor Technologies Ltd., ECTC 2009 Conference Paper

Fig 10: Process steps of wafer-level underfill [2] As required in coating or printing process, liquid material is needed for underfill deposition. In this process, two dissimilar materials are applied one to the flux layer and the other to the bulk underfill which ensures the separation of flux from bulk underfill. Although the process and material needed for wafer-level underfill is clearly noticed, there are some challenges impeding the development of this technology which are mentioned below: 1. Requirement of a robust underfill deposition process; 2. Consistency to enable high yield during the assembly 3. Good solder joint formation. SUMMARY This paper gives an overview of challenges in use, maufacturing, development and its future trends of underfill technology. Flip chip offers many advantages over other interconection technologies and is practiced in many applications. Underfill is required for flip chip technology to resolve the reliability issues. While convetional underfill is process-unfreindly and becomes the bottleneck to a high

[14] Pendse R; et al, Innovative Approaches in Flip Chip Packaging for Mobile Applications; Stats ChipPAC Inc., ECTC 2009 Conference Paper. [15] Ken Gilleo, New Generation Underfills Power the 2 nd Filp Chip Revolution, Surface Mount Technology, 2010. APPENDIX