Integrated Circuit

Technology Overview

Hazırlayan : Yrd. Doç. Dr. Burcu ERKMEN

 Typical VLSI Systems
Cell Phones Hearing aids
Digital Cameras

Automotive

Biomedical Computers
Why ICs
„ Integration improves
… Size(Submicron)
… Speed
… Power
… Complexity
Smaller size of IC components yields higher speed and lower power consumption.

„ Integration reduce manufacturing costs

… (almost) no manual assembly
Discrete vs Integrated Circuit Design

Activity / Item Discrete Integrated

Component Accuracy Well known Poor absolute accuracies

Breadboarding Yes No (kit parts)

Fabrication Independent Very dependent

Layout, Verification and

Physical Implementation PC layout
Extraction

Parasitics Not Important Must be included in the design

Simulation Model parameters well known Model parameters vary widely

Generally complete testing is Must be considered before

Testing
possible design
Schematic Capture,
Schematic Capture,
CAD Simulation, extraction, LVS,
Simulation, PC Board Layout
layout and routing
Active devices, capacitors, and
Components All possible
resistor
 History
The First Computer

The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470

Mechanical computing devices

Used decimal number system

Could perform basic arithmetic

operations

Even store and execute

Problem: Too complex and expensive!

ENIAC - The first electronic computer (1946)

17,468 vacuum tubes

7,200 crystal diodes
1,500 relays
70,000 resistors
10,000 capacitors
30 tons
63 m²
150 kW
5,000 simple addition
or subtraction operations

Problem: Reliability issues and excessive power consumption!

 Invention of the Transistor
„ Vacuum tubes invented in 1904 by Fleming
… Large, expensive, power-hungry, unreliable

Invention of the bipolar transistor (BJT) 1947

Shockley, Bardeen, Brattain – Bell Labs
First Integrated Circuit
integrated circuit 1958 Jack Kilby – Texas Instruments
A device having multiple electrical components and their interconnects manufactured
on a single substrate.
Intel 4004 Micro-Processor

1971
2300 transistors
108 KHz operation
PMOS only (10 um process)
Intel Pentium 4 Micro-Processor

2000
42 million transistors
2 GHz operation
0.18 um
Intel Core 2 Quad

2008
820 million transistors
2.83 GHz operation
45 nm
VLSI technological growth based on:

• Feature size

• Gate count of a chip

• Transistor count of a chip

• Operating frequency of a chip

• Power consumption of a chip

• Power density in a chip

• Size of a device used in chip

Moore’s Law
In 1965, Gordon Moore noted that
the number of transistors on a chip
doubled every 18 to 24 months.
Gordon Moore
Intel Co-Founder
Intel Processor Transistor Count Trends
Year Model Transistor Count
1971 4004 2300
1972 8008 3500
1974 8080 6000
1978 8086 29000
1982 80286 134000
1985 80386 275000
1989 80486 1,2 million
1993 Pentium 3,1 million
1995 Pentium Pro 5,5 million
1997 Pentium II 7.5 million
1999 Pentium III 9.5 million
1999 Celeron 18.9 million
2000 Pentium 4 42 million
2002 Itanium II 220 million
2003 Pentium M 77 million
2005 Pentium D 230 million
2006 Dual Core 376 million
2006 Quad Core 1328 million
2007 Core 2 Duo 410 million http://www.intel.com/press
2008 Core 2 Quad 820 million room/kits/quickreffam.htm
Intel Processor Transistor Size Trends
Year Model Transistor Size
1971 4004 10um
1972 8008 10um
1974 8080 6um
1978 8086 3um
1982 80286 1,5um
1985 80386 1,5um
1989 80486 1um
1993 Pentium 0,8um
1995 Pentium Pro 0,6um
1997 Pentium II 0,35um
1999 Pentium III 0,25um
1999 Celeron 0,25um
2000 Pentium 4 0,18um
2002 Itanium 2 0,18um
2003 Pentium M 0,13um
2005 Pentium D 90nm
2006 Dual Core 65nm
2007 Core 2 Duo 65nm http://www.intel.com/press
2008 Core 2 Quad 45nm
room/kits/quickreffam.htm
EXACTLY HOW SMALL (AND POWERFUL) IS 45 NANOMETERS

„ 45nm Size Comparison

… o A nail = 20 million nm

… o A human hair = 90,000nm

… o Ragweed pollen = 20,000nm

… o Bacteria = 2,000nm

… o Intel 45nm transistor = 45nm

… o Rhinovirus = 20nm

… o Silicon atom = 0.24nm

1.000.000.000nm = 1m
Expected CMOS Downsizing from History to Future
History
Expected
Downsizing
Era Limit
In late 1970 1micro-meter
In early 1980 500nm
In early 1990 100nm

Today
™ Intel plans to introduce processors built on 32nm technology in 2009

™ 5nm gate lenght p-channel MOSFET has been reported in the research level
(H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M Narihiro, K. Arai, Y. Ochiai, K. Takeuchi, T. Yamamoto, and T. Mogami, “Sub-
10- nm Planar-Bulk-CMOS Devices using Lateral Junction Control”, IEDM Tech., Dig., pp.989-991, Washington DC, December, 2003)

Future
The ultimate limit of downsizing is the distance of atoms in silicon crystals.
(about 0.3nm )
Intel Processor Operating Frequency Trends
Year Model Clock Speed(s)
1971 4004 108KHz
1972 8008 200KHz
1974 8080 2MHz
1978 8086 10MHz
1982 80286 12MHz
1985 80386 33MHz
1989 80486 50MHz
1993 Pentium 66MHz
1995 Pentium Pro 200MHz
1997 Pentium II 300MHz
1999 Pentium III 600MHz
1999 Celeron 333MHz
2000 Pentium 4 2GHz
2002 Itanium 2 1GHz
2003 Pentium M 1.7GHz
2005 Pentium D 3.2GHz
2006 Quad Core 2.66GHz http://www.intel.com/press
2007 Core 2 Duo 2.33GHz room/kits/quickreffam.htm
2008 Core 2 Quad 2.83GHz
Power Density

Power density too high to keep junctions at low temp

 Top 10 Preliminary Worldwide Semiconductor Vendors by Revenue Estimates
(Millions of U.S. Dollars)

2008 2007 2008 2008 2007 2007-2008

Rank Rank Company Revenue Market Share (%) Revenue Growth (%)

1 1 Intel 34,187 13.1 33,800 1.1

2 2 Samsung Electronics 17,900 6.8 20,464 -12.5

3 3 Toshiba 10,510 4.0 11,820 -11.1

4 4 Texas Instruments 9,792 3.7 11,768 -16.8

5 6 STMicroelectronics 9,652 3.7 9,966 -3.2

6 5 Infineon Technologies (incl. 8,078 3.1 10,194 -20.8

Qimonda)
7 8 Renesas Technology 7,849 3.0 8,001 -1.9

8 11 Qualcomm 6,463 2.5 5,619 15.0

9 7 Hynix Semiconductor 6,400 2.4 9,100 -29.7

10 12 NEC Electronics 5,889 2.2 5,593 5.3

Others 145,180 55.4 147,586 -1.6

Total 261,900 100.0 273,911 -4.4

Source: Gartner (December 2008)

Worldwide IC Foundry Centers

The total number of IC

Country Foundry Center

USA 16

Japan 12
Other Asian Countries
(China, Taiwan, Singapore, Korea) 25

Europe & Israel 6

ITRS - International Technology Roadmap for Semiconductors

YEAR 2002 2005 2008 2011 2014

TECHNOLOGY 130nm 100nm 70nm 50nm 35nm

CHIP SIZE 400mm2 600mm2 750mm2 800mm2 900mm2

NUMBER OF TRANSISTOR (LOGIC) 400M 1 Billion 3 Billion 6 Billion 16 Billion

DRAM CAPACITY 2GBits 10GBits 25GBits 70GBits 200GBits

MAXIMUM CLOCK FREQUENCY 1.6GHz 2GHz 2.5GHz 3GHz 3.5GHz

MINIMUM SUPPLY VOLTAGE 1.5V 1.2V 0.9V 0.6V 0.6V

MAXIMUM POWER DISSIPATION 130W 160W 170W 175W 180W

MAXIMUM NUMBER OF I/O PINS 2500 4000 4500 5500 6000

Predictions of the worldwide semiconductor / IC

industry about its own future prospects..
 ASIC Design Strategies
„ Design is a continuous tradeoff to achieve
performance specs with adequate results in all
the other parameters.
„ Performance Specs - function, timing, speed,
power
„ Size of Die - manufacturing cost
„ Time to Design - engineering cost and schedule
„ Ease of Test Generation & Testability -
engineering cost, manufacturing cost, schedule
Design Abstraction Levels
SYSTEM

MODULE

GATE

CIRCUIT

DEVICE
G
S D
n+ n+
 From Sand to IC

2-inch to 12-inch wafers

When Intel first began making chips,
the company printed circuits on 2-inch wafers.
Now the company uses both 300-millimeter (12-inch)
and 200-millimeter (8-inch) wafers, resulting in larger
chip yields and decreased costs.

The larger wafers can yield more than

twice as many chips, achieving an economy
of scale that Intel says will save 30% in
manufacturing costs for each wafer.
 Scaling & Integration Analogy

12 inch wafer: Earth:

300 mm diameter 13000 km diameter
23 billion components 7 billion people
IC Classification
‰ Circuit technology (BJT, BiCMOS, NMOS, CMOS)

‰ Design style (Standard cell, Gate Array, Full Custom, FPGA)

‰ Design Type (Analog, Digital, or Mixed-Signal)

‰ Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

IC Classification

‰ Circuit technology (BJT, BiCMOS, NMOS, CMOS)

‰ Design style (Standard cell, Gate Array, Full Custom, FPGA)

‰ Design Type (Analog, Digital, or Mixed-Signal)

‰ Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

Classification of IC Technologies

(for RF) (for High

Speed)
IC Technology Market
Signal Bandwidths versus Technology
Signal Bandwiths versus Application
Why CMOS
‰ Power dissipation only during switching
(circuitry dissipates less power when static)

‰ Higher packing density – lower manufacturing cost per device

‰ MOS devices could be scaled down more easily

Bipolar transistors can operate at higher frequencies than CMOS

(usefull for microwave applications )
Bipolar vs. MOS Transistor

CATEGORY BJT CMOS

Power Dissipation Moderate to High Low but can be large

Speed Faster Fast

gm at 100MicroAmper 4mS 0.4mS (W=10L)

Number of Terminals 3 4

Cutoff Frequency(fT) 100 GHz 50 GHz (0.25µm)

Noise (1/f) Good Poor

Smaller for short
Small Signal Output Resistance Slightly larger channel

Switch Implementation Poor Good

Technology Improvement Slower Faster

IC Classification
‰ Circuit technology (BJT, BiCMOS, NMOS, CMOS)

‰ Design style (Standard cell, Gate Array, Full Custom, FPGA)

‰ Design Type (Analog, Digital, or Mixed-Signal)

‰ Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

Classification of ASIC Design Styles
 Full Custom Design
™ Custom design involves the entire design of the IC, down to the smallest detail of
the layout.
™ No restriction on the placement of functional blocks and their interconnections
™ Highly optimized, but labor intensive.
™ Designer must be an expert in VLSI design
™ Design time can be very long (multiple months)
™ Involves the creation of a a completely new chip
™ Fabrication costs are high
Full Custom Design Style
 Full Custom Layout
Full Custom Layout of Square Root Circuit
Standart Cell Design
™ Designer uses a library of standard cells; an automatic place and route
tool does the layout.
™ Each standard cell contains a single gate of AND, OR, NOT etc.
™ Standard cells can be placed in rows and connected with wires
™ Routing done on “channels” between the rows.
™ All cells are the same height but vary in width.
™ All cells have inputs and outputs on top or bottom
of cell.
™ Design time can be much faster than full custom because layout is
automatically generated.
Standart Cell Design Style
Standart Cell Layout
Gate Array Design
™ Pre-fabricated array of gates (could be NAND).
(Gates already created on a wafer; only need to add the interconnections.)
™ Entire chip contains identical gates
¾ normally 3- or 4-input NAND or NOR gates.
¾10,000 – 1,000,000 gates can be fabricated within a single IC depending
on the technology used.
™ A routing tool creates the masks for the routing layers and "customizes" the
pre-created gate array for the user's design
™ Manufacture of interconnections requires only metal deposition
™ Fabrication costs are cheaper than standard cell or full custom because the
gate array wafers are mass produced
™ The density of gate arrays is lower than that of custom IC’s
™ This style is often a suitable approach for low production volumes.
Gate Array Design Style
FPGA Design
™ Pre-fabricated array of programmable logic and interconnections.
™ Programmable interconnects between the combinational logic, flip-flops
and chip Inputs and Outputs
™ Field Programmable devices are arrays of logic components whose
connectivity can be established simply by loading appropriate configuration
data into device’s internal memory.
™ No fabrication step required, avoid fabrication cost and time
™ Very good for prototype design because many FPGAs are
re-usable.
FPGA Design Style
 Design Style Comparisons
Full Standard Cell Gate Array FPGA
Custom
Cell size Variable Fixed height Fixed Fixed

Cell type Variable Variable Fixed Prog.

Cell placement Variable In row Fixed Fixed
Interconnections Variable Variable Variable Prog.

Design cost High Medium Medium Low

Area Compact Compact to Moderate Large

Moderate
Performance High High to Moderate Low
Moderate
Fabricate All Layers All Layers Routing None
IC Classification
‰ Circuit technology (BJT, BiCMOS, NMOS, CMOS)

‰ Design style (Standard cell, Gate Array, Full Custom, FPGA)

‰ Design Type (Analog, Digital, or Mixed-Signal)

‰ Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)
Design Type
Analog, Digital, or Mixed-Signal VLSI
 DIGITAL
™ Regular, hierarchical and modular
™ Designed at the system level
™ Standardized
™ Components must have fixed values
™ Simplified device models
™ Available synthesis EDA tools
™ Designed at the system level
(top-down)
™ Short design time
™ First time successful prototyping
Mixed Mode
ANALOG
™ Irregular /hardly hierarchical
™ Designed at the circuit level
™ Customized
™ Components must have a continuum values
™ Required precision modeling
™ Hard to find synthesis tools
™ Mixed bottom-up top-down
™ Longer design time
™ More spins for prototyping
™ Difficult to test
™ Less power consumption
IC Classification
‰ Circuit technology (BJT, BiCMOS, NMOS, CMOS)

‰ Design style (Standard cell, Gate Array, Full Custom, FPGA)

‰ Design Type (Analog, Digital, or Mixed-Signal)

‰ Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

Classification of Circuit Size

Small-Scale Integration SSI <100 1963

Medium-Scale Integration MSI 100-300 1970

Large-Scale Integration LSI 300 - 30000 1975

Very Large-Scale Integration VLSI 30000 - 1million 1980

Ultra-Large Scale Integration ULSI >1million 1990

Giga Scale Integration GSI >1billion 2010

System-on-a-Chip (SoC)

Three Dimensional Integrated Circuit (3D-IC)

 System-on-a-Chip (SoC)
Integrating all or most of the components of a hybrid system on a single substrate
(silicon or MCM), rather than building a conventional printed circuit board.

¾ More compact system

realization
¾ Higher speed
¾ Better reliability
¾ Less expensive
Three Dimensional Integrated Circuit (3D-IC)
Advatages of 3D-ICs
‰ Improved packing density
‰ Noise immunity
‰ Improved total power due to reduced wire length/lower capacitance
‰ Superior performance
‰ The ability to implement added functionality

http://www.research.ibm.com/journal/rd/504/topol.html
Traditional VLSI Design Flow
Traditional VLSI Design Flow (Cont'd)
 Future of CMOS Technology

™ Future Lithography Techniques (electron-beam lithography, X-ray

lithography, Excimer laser)

™ Novel transistor structures (SOI, double-gate MOSFETs , High-k (dielectric

constant) gate insulatoror technology)

™ Wiring and interconnections (aluminium-based inter-connects are being

replaced by lower-resistance copper ; low-k (dielectric constant) interlayer for
interconnects)

™Control of Power and heat generation (New cooling technologies,

Changeable clock frequency and supply voltage )