Verilog HDL Simulation Labs

Overview
The Verilog simulation labs in this course are designed to maximize your handson introduction to Verilog coding. Therefore, you are asked to create all hardware modules and testbenches from scratch. After finishing these labs, you will gain the level of coding skill, syntax proficiency, and understanding that can only be achieved through meaningful practice and effort. Most of the early lab exercises are standalone tasks that reinforce and illustrate language concepts that are fundamental to all Verilog coding.

Objectives
After completing these labs, you will be able to: Write RTL descriptions for simple circuits Create a structural Verilog description for simple circuits Build hierarchy by using Verilog Create a Verilog testbench to verify the hierarchical structure created in the previous steps Use the simulation software Create basic input stimulus Run a simulation

Labs Outline
Lab Lab Lab Lab Lab Lab 1: 2: 3: 4: 5: 6: Building Hierarchy Simulation/Verification Memory n-bit Binary Counter Comparator Arithmetic Logic Unit (ALU)

Lab 1: Building Hierarchy

In this lab, you will write a complete RTL description for the modules MY_AND2 and MY_OR2 and build the circuit shown below (Figure 1) in a structural Verilog description of the top-level module AND_OR.

INP[0] INP[1]

MY_AND2

SIG1

Top level: AND_OR

U0
MY_OR2

OUT1

INP[2] INP[3]

MY_AND2

SIG2

U2

U1

Figure 1 This lab comprises three primary steps: You will create a software project; write RTL descriptions; and check the syntax of your RTL code.

Lab 2: Simulation/Verification
In this lab, you will write a Verilog testbench for the AND_OR module completed in the previous exercise. As part of the testbench, you will create a simple input stimulus by using both concurrent and sequential statements. Examine the circuit below (Figure 2). In this lab, you will write a complete Verilog testbench description for the module AND_OR.

Figure 2

This lab comprises four primary steps: You will create a new project and import Verilog source files; create a testbench with the Verilog testbench wizard in the simulation software; create initial and always input stimulus statements; and, finally, verify the logic structure and functionality by running a simulation and examining the resulting waveforms.

Lab 3: Memory (ROM)

In this lab, you will write a complete RTL description for a ROM module by using a one-dimensional array and a Verilog reg data type and a case statement.

The memory was modeled as a ROM, which is a constant; therefore, you were required to assign values at the time of declaration. This lab comprises three primary steps: You will create a one dimensional memory array using case statement; create a testbench with the Verilog testbench wizard in the simulation software; finally, verify the logic structure and functionality by running a simulation and examining the resulting waveforms.

Lab 4: n-bit Binary Counter

In this lab, you will write a complete RTL description for the module CNTR by using parameter statements to specify the bit width. This is an n-bit binary, up/down, loadable counter, with active-Low asynchronous reset. You will then build a Verilog HDL testbench to verify the functionality of the RTL code as well as the hardware it models.

Examine the circuit below (Figure 3). In this exercise, you will create a fully functional binary counter that can be dynamically scaled to any length. The use of parameter statements is an important tool for module reuse and source code readability. The circuit is an n-bit binary, up/down loadable counter, with activeLow asynchronous reset.
D_IN CNTR CE LOAD UpDn CLK RST Q_OUT

Figure 3

This lab comprises three primary steps: You will create a software project; declare the parameter statements; and, finally, create a testbench to verify the design. Create the input stimulus: 1. Set the CLOCK input to toggle at a rate of 100 MHz 2. Assert the RESET input at time 15 ns, hold for 25 ns, then de-assert 3. Set the CE input initially High, de-assert (set Low) at time 300, hold for 100 ns, reassert 4. Set the LOAD input initially Low, toggle High at time 500 ns, for one full clock cycle 5. Set UPDN to initially High, then Low at time 750 ns 7. Set the D_IN input value to 8h0F or 8b00001111

Lab 5: Comparator
In this lab, you will write description for the module COMP (Synchronous Comparator) using an if/else statement. Examine the circuit below (Figure 4):

Figure 4 This lab comprises four primary steps: You will create a software project; create an RTL version of COMP; and, finally, create a testbench to verify that the behavioral model functions correctly. If the expected result and the data are equal, the result is TRUE; otherwise, the result is FALSE. Declarations of input and output are shown in the following table: Port Label enable expected data result clk Length 1bit 4 bit 4 bit 1 bit 1 bit Description Input; enable the comparator Input; expected output Input; actual output; Output; result of comparison Clock input

Lab 6: Arithmetic Logic Unit (ALU)

In this lab, you will write a complete RTL description for the module ALU. The op-codes and functionality of the synchronous ALU is described below.

Inputs A_IN (4 bit ) B_IN (4 bit ) OPCODE (4 bit ) CLK ENABLE

Outputs OUTPUT (4 bit)

Use a case statement to describe the functionality for the ALU as shown in the following table, which shows the SELECTION OPCODE and the operation/function for each. Do not forget the ENABLE input.
OPCODE S2 S1 S0

S3

0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0

0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1

Operation Y=A Y=A+1 Y=A+B Y=A+B+1 Y = A + (~B ) Y = A + (~ B ) + 1 Y=A1 Y = A and B Y = A or B Y = A xor B Y=~A Y=0

Function Transfer Increment Addition Addition and Increment Add + 1s comp Subtraction Decrement AND OR XOR Compliment Transfer 0s

Table: SELECTION OPCODE