VLSI TECHNOLOGY

Jitendra S Sengar Asst. Professor VLSI Division, ECE

COURSE SYLLABUS

Unit 1 Crystal growth & wafer preparation. Processing considerations: Chemical cleaning, getting the thermal Stress factors etc. Epitaxy [T1] Vapors phase Epitaxy Basic Transport processes & reaction kinetics, doping & auto doping, equipments, & safety considerations, buried layers, epitaxial defects, molecular beam epitaxy, equipment used, film characteristics, SOI structure.
Unit 2 Oxidation [T1] Growth mechanism & kinetics, Silicon oxidation model, interface considerations, orientation dependence of oxidation rates thin oxides. Oxidation technique & systems dry & wet oxidation. Masking properties of SiO2. Diffusion [T1] Diffusion from a chemical source in vapor form at high temperature, diffusion from doped oxide source, diffusion from an ion implanted layer. (

COURSE SYLLABUS

Unit 3 Lithography [T1] Optical Lithography: optical resists, contact & proximity printing, projection printing, electron lithography: resists, mask generation. Electron optics: roster scans & vector scans, variable beam shape. X-ray lithography: resists & printing, X ray sources & masks. Ion lithography.
Unit 4 Etching [T1] Reactive plasma etching, AC & DC plasma excitation, plasma properties, chemistry & surface interactions, feature size control & apostrophic etching, ion enhanced & induced etching, properties of etch processing. Reactive Ion Beam etching, Specific etches processes,Trench etching.

TEXT AND REFERENCE BOOKS

Text Books

[T1] S.M. Sze, Modern Semiconductor Device Physics, John Wiley & Sons, 2000.

Reference Books

[R1]B.G. Streetman, Solid State Electronics Devices, Prentice Hall, 2002. [R2]Chen,VLSI Technology Wiley, March 2003.

Tools Used

Silvaco

OBJECTIVE OF THE COURSE

Understand the impact of the physical and chemical processes of integrated circuit fabrication technology on the design of integrated circuits. Understand physics of the Crystal growth, wafer fabrication and basic properties of silicon wafers

Learning contamination reduction and corresponding measurements methods including clean factory, wafer cleaning and Gettering. Learning lithography techniques and concepts of wafer exposure system (projection, contact and proximity) types of resists (g-line, I-line, and deep ultraviolate resist). Its measurement methods including mask features, defects, resist pattern and etched features) Understand Concepts of thermal oxidation and Si/SiO2 interface and its quality measurements (including physical, optical and electrical). Modelling and simulation of thermal oxidation.

Learn concepts of dopant solid solubility, diffusion macroscopic point, different solutions to diffusion equation. Design and evaluation of diffused layers and its measurement methods. Learn concepts of ion implantation, role of the crystals structures, high-energy implants, ultralow energy implants and ion beam heating methods. Learn concepts of thin film deposition including chemical Vapor Deposition (including APCVD, LPCVD, PECVD and HDPCVD) and Physical vapor deposition (including, evaporation and sputtering). Learning concepts of Wet etching, and Plasma etching mechanism and systems.

Learning back-end technology including contacts, interconnects vias, dielectrics, silicided gates, source/drain regions, contact formations, global interconnects, IMD deposition and planarization. Morphological, electrical, chemical and structure, mechanical measurements.

A Brief History
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large,

expensive, power-hungry, unreliable 1947: first point contact transistor (3 terminal devices)

Shockley, Bardeen and Brattain at Bell Labs

A Brief History, contd..

1958: First integrated circuit

Flip-flop using two transistors Built by Jack Kilby (Nobel Laureate) at Texas Instruments Robert Noyce (Fairchild) is also considered as a co-inventor

Kilbys IC
smithsonianchips.si.edu/ augarten/

A Brief History, contd.

First Planer IC built in 1961

2003 Intel Pentium 4 processor (55 million transistors) 512 Mbit DRAM (> 0.5 billion transistors) 53% compound annual growth rate over 45 years No other technology has grown so fast so long Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society

MOS Integrated Circuits

1970s processes usually had only nMOS transistors
Inexpensive, but consume power while idle

1980s-present: CMOS processes for low idle power

Intel 1101 256-bit SRAM

Intel 4004 4-bit Proc

Moores Law
1965: Gordon Moore plotted transistor on each chip

Fit straight line on semilog scale Transistor counts have doubled every 26 months

Integration Levels
SSI: 10 gates

MSI: 1000 gates LSI: 10,000 gates

VLSI: > 10k gates

http://www.intel.com/technology/silicon/mooreslaw/

Corollaries
Many other factors grow exponentially

Ex: clock frequency, processor performance

10,000 1,000 4004 8008 8080 100 8086 80286 Intel386 10 Intel486 Pentium Pentium Pro/II/III 1 Pentium 4

Clock Speed (MHz)

1970

1975

1980

1985

1990

1995

2000

2005

Year

WHY VLSI DESIGN?

Money, technology, civilization

VLSI:VERY LARGE SCALE INTEGRATION

Integration: Integrated Circuits

multiple devices on one substrate

How large is Very Large?

SSI (small scale integration)

7400 series, 10-100 transistors 74000 series 100-1000

MSI (medium scale)

LSI 1,000-10,000 transistors VLSI > 10,000 transistors ULSI

Need of VLSI
Integration Improves the Design Lower parasitics, higher clocking speed Lower power Physically small Integration Reduces Manufacturing Costs (almost) no manual assembly About $1-5billion/fab Typical Fab 1 city block, a few hundred people Packaging is largest cost Testing is second largest cost For low volume ICs, Design Cost may swamp all manufacturing cost

Levels of Design
Specifications IO, Goals and Objectives, Function, Costs
Architectural Description VLHD, Verilog, Behavioral, Large Blocks

Logic Design Gates plus Registers

Circuit Design Transistors sized for power and speed Discrete Logic, Technology Mapping

Layout Size, Interconnect, Parasitics

SYSTEM

MODULE

GATE

CIRCUIT

G S n+ D

DEVICE

n+

WHAT IS CMOS VLSI?

MOS

= Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation) we use polycrystalline silicon which is deposited on the surface of the chip as a gate. We call this poly or just red stuff to distinguish it from the body of the chip, the substrate, which is a single crystal of silicon. do use metal (aluminum) for interconnection wires on the surface of the chip.

Now

We

CMOS:COMPLEMENTARY MOS
Means

we are using both N-channel and Pchannel type enhancement mode Field Effect Transistors (FETs). Field Effect- NO current from the controlling electrode into the output
FET is a voltage controlled current device BJT is a current controlled current device

N/P

Channel - doping of the substrate for increased carriers (electrons or holes)

Complementary Metal Oxide Semiconductor

VDD PMOS

X
NMOS

VSS

FOUR VIEWS

Logic

Transistor

Layout

Physical

VLSI DESIGN
The

real issue inVLSI is about designing systems on chips. The designs are complex, and we need to use structured design techniques and sophisticated design tools to manage the complexity of the design. We also accept the fact that any technology we learn the details of will be out of date soon. We are trying to develop and use techniques that will transcend the technology, but still respect it.

HELP FROM COMPUTER AIDED DESIGN TOOLS

Tools

Experts

Editors Simulators Libraries Module Synthesis Place/Route Chip Assemblers Silicon Compilers

Logic design Electronic/circuit design Device physics Artwork Applications - system design Architectures

DESIGN STYLES

Full custom Standard cell Gate-array Macro-cell FPGA Combinations

FULL CUSTOM Hand drawn geometry All layers customized Digital and analog Simulation at transistor level (analog) High density High performance Long design time

FULL CUSTOM

Vdd

IN

Out

Gnd

STANDARD CELLS

Standard cells organized in rows (and, or, flipflops,etc.) Cells made as full custom by vendor (not user). All layers customized Digital with possibility of special analog cells. Simulation at gate level (digital) Medium density Medium-high performance Reasonable design time

STANDARD CELLS

Routing

Cell

IO cell

GATE-ARRAY

Predefined transistors connected via metal Two types: Channel based Channel less (sea of gates) Only metallization layers customized Fixed array sizes (normally 5-10 different) Digital cells in library (and, or, flip-flops,etc.) Simulation at gate level (digital) Medium density Medium performance Reasonable design time

GATE-ARRAY
Sea of gates Channel based Vdd NAND gate using gate isolation

Vdd A B PMOS Oxide isolation Out B

A
Out

NMOS Gate isolation

Gnd

Can in principle be used by adjacent cell Gnd

Gate-array

Sea of gates
RAM

MACRO CELL

Predefined macro blocks (Processors, RAM,etc) Macro blocks made as full custom by vendor All layers customized Digital and some analog (ADC) Simulation at behavioral or gate level (digital) High density DSP processor High performance LCD RAM Short design time cont. Use standard on-chip busses ADC ROM System on a chip

FPGA = FIELD PROGRAMMABLE GATE ARRAY

Programmable logic blocks Programmable connections between logic blocks No layers customized (standard devices) Digital only Low - medium performance (<50 - 100MHz) Low - medium density (up to ~100k gates) Programmable by: SRAM, EEROM, Anti_fuse, etc Cheap design tools on PCs Low development cost High device cost

HIGH PERFORMANCE DEVICES

Mixture of full custom, standard cells and macros Full custom for special blocks: Adder (data path), etc. Macros for standard blocks: RAM, ROM, etc. Standard cells for non critical digital blocks

Transistor Types
Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration First patent in the 20s in USA and Germany Not widely used until the 60s or 70s

MOS TRANSISTORS

Four terminal device: gate, source, drain, body Gate oxide body stack looks like a capacitor

Gate and body are conductors (body is also called the substrate) SiO2 (oxide) is a good insulator (separates the gate from the body Called metaloxidesemiconductor (MOS) capacitor, even though gate is mostly made of poly-crystalline silicon (polysilicon)
Source Gate Drain Polysilicon SiO 2
Polysilicon SiO 2 Source Gate Drain

n+ p

n+ bulk Si

p+ n

p+ bulk Si

NMOS

PMOS

NMOS OPERATION

Body is commonly tied to ground (0 V) Drain is at a higher voltage than Source When the gate is at a low voltage:

P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF
Source Gate Drain Polysilicon SiO2 0 n+ p n+ S bulk Si D

NMOS OPERATION CONT.

When the gate is at a high voltage: Positive charge on gate of MOS capacitor

Negative charge is attracted to body under the gate Inverts a channel under gate to n-type (N-channel, hence called the NMOS) if the gate voltage is above a threshold voltage (VT) Now current can flow through n-type silicon from source through channel to drain, transistor is ON
Source Gate Drain Polysilicon SiO2 1 n+ p n+ S bulk Si D

PMOS TRANSISTOR

Similar, but doping and voltages reversed

Body tied to high voltage (VDD) Drain is at a lower voltage than the Source Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior
Source Polysilicon SiO 2

Gate

Drain

p+ n

p+ bulk Si

POWER SUPPLY VOLTAGE

GND = 0 V In 1980s, VDD = 5V VDD has decreased in modern processes

High VDD would damage modern tiny transistors Lower VDD saves power

VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, Effective power supply voltage can be lower due to IR drop across the power grid.

HELPING FIELDS FOR IC FABRICATION

Material Engineering Chemistry Device Physics Advanced Technology.

MATERIALS USED IN VLSI FABRICATION Main Categories of Materials Materials can be classified into three main groups regarding their electrical conduction properties: 1. Insulators 2. Conductors 3. Semiconductors

CONDUCTORS

1. 2. 3. 4. 5.

Conductors are used in IC design for electrical connectivity. The following are good conducting elements: Silver Gold Copper Aluminum Platinum

INSULATORS
Insulatorsare usedtoisolate conductingand/or semi-conductingmaterialsfromeachother. MOS devicesand Capacitorsrelyon an insulatorfortheirphysicaloperation. The choiceof the insulators(and the conductors) in IC design dependsheavilyon howthe materials interactwitheachother, especiallywiththe semiconductors.

SEMICONDUCTORS

The basic semiconductor material usedin devicefabricationisSilicon The success of thismaterial isdue to: Phisicalcharacteristics Abundance in nature and very low cost Relatively easy process Reliable high volume fabrication Othersemiconductors(e.g. GaAs) are usedforspecial applications