Professional Documents
Culture Documents
Introduction to the Partial Element Equivalent Circuit (PEEC) Technique (MO-AM-5) G. Antonini, A. E. Ruehli+, F. Ferranti
degli Studi dellAquila, ITALY + Emeritus IBM, IBM T. J. Watson Research Center, USA
Ghent Universit` a
University, BELGIUM
Slide 1
Overview
Introduction to Partial Element Equivalent Circuit (PEEC) Method PEEC Fundamentals Assembling Equations by enforcing KVL and KCL Multi-function partial elements evaluation Complexity reduction, non-orthogonal formulation PEEC Model Examples Conclusions How can I get started with PEEC - References
2010 IEEE EMC Symposium Slide 2
Differential Equation
Integral Equation
PEEC
CIRCUIT EQUATIONS
Slide 3
PEEC fundamentals
Each current owing in volumes, located at a point r within v , and each charge on surfaces, located at a point r S on S produce, an induced effect at a point r at time t.
Inside the conductor, at a point r , at time t, the following equation holds A(r , t) J (r , t) i = E (r , t) (r , t) E (r , t) = t where E i (r , t) is the electric eld eventually incident in r at time t.
2010 IEEE EMC Symposium Slide 4
PEEC fundamentals
J (r , t) A(r , t) E (r , t) = + + (r , t) t
i
A(r , t) =
J (r , t ) dv |rr |
(r , t) =
1 4
(r , t ) dS |rr |
| r r | t =t r r c0 J (r , t) + E (r , t) = 4
i v
1 J (r , t ) 1 dv + t |rr | 4
(r , t ) dS |rr |
PEEC fundamentals
The previous equations can be rewritten in the Laplace domain, in a more compact form, as: E (r , s) = (r , s) =
i
J (r , s) s J (r , s) es + dv + (r , s) 4 v |r r | (r , s) es 1 rS dS 4 S |r r | rv rS
J (r , s) = 0 J (r , s) = s (r , s) n
where = |r r |/c0 , s is the Laplace variable and c0 is the speed of light in the free space.
Slide 6
PEEC fundamentals
Conductor and dielectric volumes and surfaces are discretized in elementary volumes (hexahedra) and patches (quadrilaterals) respectively.
Jy
Jx
1
Q1
Currents are assumed owing in volume cells running into x, y, z directions Charges are assumed on the surface of conductors
2010 IEEE EMC Symposium Slide 8
PEEC fundamentals
The unknown quantities J (r , s) and (r , s) are approximated by a weighted sum of nite set of basis functions b R3 and p R: J (r , s) = (r , s) = where In (s) and Qm (s) are the basis function weights which must be determined at each angular frequency s Nv and Ns represent the number of volume and surface basis functions and the corresponding elementary volume and surface subregions
2010 IEEE EMC Symposium Slide 9
Nv
bn (r ) In (s)
n=1 Ns
pm (r ) Qm (s)
m=1
PEEC fundamentals
Nv n=1
E (r , s) =
bn (r ) In (s) s + 4
Ns m=1
Nv n=1
es bn (r n ) In (s) dVn + |r r n | Vn
+ (r , s) (r , s) = 1 4 es pm (r m ) Qm (s) dSm |r r m | Sm
The so-called Galerkins testing or weighting process is used to generate a system of equations for the unknowns weights In (s) , n = 1 Nv and Qm (s) , m = 1 Ns by enforcing the residuals of equations to be orthogonal to a set of weighting functions, chosen to be coincident with the basis functions.
Slide 10
PEEC fundamentals
Each term of the EFIE is weighted and integrated over elementary volume cells Vi : f (r ) , bi (r )
Vi
Vi
f (r ) bi (r ) dVi
for i = 1 Nv
E i (r , s) + s 4
Nv n=1
Nv n=1 bn (r ) In (s)
+ dVn + (r , s) , bi (r )
Vi
es bn (r n ) In (s) |r r n | Vn
=0
Slide 11
PEEC fundamentals
Choice of the basis and weighting functions for conductor volumes and conductor surfaces n u 0
Sn
bn (r ) =
if r Vn otherwise
if r Am otherwise
Slide 12
VRk
lk = ILk = Rk ILk Sk
M + Qm (Pk,m Pk,m ) m=1
VLk = s
n=1
Lpkn ILn
VCk =
l and Sk are the length and the cross section of cell k and the coecient 1 Lpkn (s) = 4 Sk Sn
Vk
es k u n u dVn dVk |r k r n | Vn
which allows to relate the potential of each surface cell to the displacement current due to charges located on the surface of cells. Kirchhos current law (KCL) is enforced to each node m. In the Laplace domain, it reads:
Nv
sQm
k=1
where am,k = 1, +1, 0 depending on the connection and direction of branch k with respect to node m and Ism (s) represents the current source located at node m.
2010 IEEE EMC Symposium Slide 14
Example
Single zero thickness conductor with three nodes. Discretization process: 3 nodes, 3 potentials to innity k , k = 1, 2, 3 2 branches, 2 currents ILn , n = 1, 2
Slide 15
Example
Equivalent circuit for magnetic eld coupling KVL is enforced to each mesh.
1 2 (R1 + sLp11 IL1 + sLp12 IL2 + V01 ) = 0 2 3 (R2 + sLp22 IL2 + sLp21 IL1 + V02 ) = 0 In a matrix form, KVL reads: A (s) RI L (s) sLp (s) I L (s) V 0 (s) = 0 where A is the connectivity matrix.
2010 IEEE EMC Symposium Slide 16
1 P
11
I1
1 P
22
I2
1 P
33
I3
Slide 18
2 Ic 2
R2
+ -
IL 2
Lp22
3 Ic 3
1 P
11
I1
1 P
22
I2
1 P
I3
33
Partial element equivalent circuit Lumped linear and non linear elements can be connected to the equivalent circuit through nodes.
Slide 19
Ak
Am
Dense matrices!!
2010 IEEE EMC Symposium Slide 20
Example: Evaluation of Partial Inductances Near and Far Coecients; High Accuracy Required!
Lp km Lp km = 4Sk Sm
vk vm
uk um dvk dvm | rk rm |
lk lm uk um = 4rkm
2010 IEEE EMC Symposium
Slide 21
vk
vm
Partial Lp Circuit Equation dik (t) dim (t ) + Lpkm vbk (t) = Lpkk dt dt
2010 IEEE EMC Symposium
Ak
Am
2 Cell Examples
qk Ak rkm Am
qm
P Circuit Element Equation vk (t) = Pkk qk (t) + Pkm qm (t ) where = rkm /c0
2010 IEEE EMC Symposium Slide 23
Lp 44
R4
3 1 p 33
1 p44 Lp R1 Lp 22 1 R2
i3 Lp R 2
3
11
33
Inductive Halfcell
i1 1 p11 i
2
1 p 22
Slide 24
The same formulation (equivalent circuit) can be used for both time and frequency domain analysis All the methods for circuit analysis can be used: nodal analysis, mesh analysis, Modied Nodal Analysis (MNA) Easy incorporation of linear and non linear lumped elements and/or electronic devices Spice-like solvers can be used eventually including delays
2010 IEEE EMC Symposium Slide 25
What is a Full Wave Solution? Highest Frequency, Fmax Given by Meshing Not Limited by Quasi Static Models (delay involved) What is a Full Spectrum Solution? Works for Low Frequencies, Including DC Limits of Lumped Circuit Element Solution? Same as Other Numerical Solution Techniques How Can We Add New Features? Very Flexible Circuit Based Solution Approach MNA (Spice) Circuit Stamps Technique
2010 IEEE EMC Symposium Slide 26
Zero Potential Ground Reference Node at Innity! N - Terminal Spice Circuit Element Included In Spice Input Language Syntax
I1
I2
I3
Slide 27
(Lp,C)PEEC
IL1
Lp11
sLp, 12 IL 2 V01 +
Ce 2 Ic 2
IL 2
Lp22
3 Ic 3
1 P
11
I1
1 P
22
I2
1 P
I3
33
a
6
2010 IEEE EMC Symposium Slide 30
Delayed Modied Nodal Analysis Formulation Multiple Lpij Delayed Inductive Couplings Multiple Pij Delayed Potential Couplings
Gi x(t i )+
i i
C0 x (t)+G0 x(t)+
Ci x (t i ) =
i
ui (t i )
Sparse L/U Circuit Matrix Solver, O(N 1.5 ) One Matrix Solve, Time Steps Back Substitutions Overall Solution Time O(N 2 ) Not O(N 3 )
2010 IEEE EMC Symposium Slide 31
*
X
Lp ij
(t- ) d Pij dt
V,I
Present Time
Slide 32
L = 50 mm
Voltage [V]
S = 20 m
Is W = 20 m
T = 1 m
0.1 0.15 0
0.5
2.5
3 x 10
3.5
9
Input Waveform Sine Square Current Source, Rise Time 100 ps, Fall Time 100 ps, Width 1.9 ns 20 non uniform cells along the length, 10 cells along the width, 1 cell along the thickness, largest Cell/Thickness to length ratio 1:4750 Cross Section: VFI Skin Eect Uniform Model
2010 IEEE EMC Symposium Slide 33
Voltage [V]
4 Time [s]
7 x 10
8
5
ilightning
n imax ks t/2 = e n) (1 + ks
Slide 34
Voltage [kV]
25 20 15 10
Striking point
Far ends 5 0 -5
10
20
30
40
50
60
70
80
90
100
Time [s]
2500 patches - 12000 spatial basis functions considering both currents and potentials to innity
Slide 35
Connectors
6 5 4 3
x 10
Coupled Noise on Passive Pin 20 ground pins 20 ground pins 6 ground pins : 6 ground pins : : Near noise : Far noise Near noise Far noise
Voltage (V)
2 1 0 1 2 3 4 0 1 2 3 Time (ns) 4 5 6
Slide 36
Summary
PEEC Model Evolution Excellent for Combined EM and Ckt. Modeling Helps Understand EM Problem Behavior, Couplings Etc. Inductance, Capacitance, Time and Frequency Domain Solutions Full Wave and Full Spectrum Solution (dc to daylight) PEEC Modeling and Solution Eciency Careful Algorithms With Engineering Accuracy Fast solvers (frequency and time domain) 3D PEEC Method Development is Continuing
Slide 37
Dispersive and lossy dielectrics [19, 20, 21, 22] Broadband modeling [23, 24, 25, 26] Input-to-state stability of PEEC models [27] Ecient identication of independent loops in PEEC circuits [28] Parametric Model Order Reduction [29, 30]
Slide 39
Slide 40
Slide 41
Slide 42
[29] F. Ferranti, G. Antonini, T. Dhaene and L. Knockaert. Passivity-Preserving Parameterized Model Order Reduction for PEEC-Based Full-Wave Analysis. In Proc. of Signal Propagation on Interconnects SPI10, Hildesheim, May 2010. [30] F. Ferranti, G. Antonini, T. Dhaene and L. Knockaert. Parameterized Model Order Reduction with Guaranteed Passivity for PEEC Circuits Analysis. In Proc. of the IEEE Int. Symp. on Electromagnetic Compatibility, Fort Lauderdale, 2010.
Slide 43