L370 2StageOLCompI 2UP

Lecture 370 Two-Stage Open-Loop Comparators-I (4/5/02) Page 370-1
ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

LECTURE 370 TWO-STAGE OPEN-LOOP COMPARATORS-I
(READING: AH 445-461)
Objective
The objective of this presentation is:
1.) Illustrate the performance and design of a two-stage open-loop comparator
Outline
Two-stage, open-loop comparator performance
Initial states of the two-stage, open-loop comparator
Propagation delay time of a slewing, two-stage, open-loop comparator
Design of a two-stage, open-loop comparator
Summary
Two-Stage Comparator
An important category of comparators are those which use a high-gain stage to drive
their outputs between V
OH
and V
OL
for very small input voltage changes.
The two-stage op amp without compensation is an excellent implementation of a high-
gain, open-loop comparator.
-
+
v
in
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+
-
C
L
Fig. 8.2-1
Performance of the Two-Stage, Open-Loop Comparator
We know the performance should be similar to the uncompensated two-stage op amp.
Emphasis on comparator performance:
Maximum output voltage
V
OH
= V
DD
- (V
DD
-V
G6
(min)-|V
TP
|)
|
|
|
|
|
|
1 - 1 -
8I
7
6
(V
DD
-V
G6
(min)-|V
TP
|)
2

Minimum output voltage
V
OL
= V
SS
Small-signal voltage gain
A
v
(0) =
\
|
|
[
)
j
j
g
m1
g
ds2
+g
ds4 \
|
|
[
)
j
j
g
m6
g
ds6
+g
ds7

Poles
Input: Output:
p
1
=
-(g
ds2
+g
ds4
)
C
I
p
2
=
-(g
ds6
+g
ds7
)
C
II

Frequency response
A
v
(s) =
A
v
(0)
\
|
|
[
)
j
j
s
p
1
+ 1
\
|
|
[
)
j
j
s
p
2
+ 1

Example 2-1 - Performance of a Two-Stage Comparator
Evaluate V
OH
, V
OL
, A
v
(0), V
in
(min), p
1
, p
2
, for the two-stage comparator in Fig. 8.2-1.
Assume that this comparator is the circuit of Ex. 6.3-1 with no compensation capacitor,
C
c
, and the minimum value of V
G6
= 0V. Also, assume that C
I
= 0.2pF and C
II
= 5pF.
Solution
Using the above relations, we find that
V
OH
= 2.5 - (2.5-0-0.7)
|
|
|
|
|
|
1 - 1 -
8234x10
-6
50x10
-6
38(2.5-0-0.7)
2
= 2.2V
The value of V
OL
is -2.5V. The gain was evaluated in Ex. 6.3-1 as A
v
(0) = 7696.
Therefore, the input resolution is
V
in
(min) =
V
OH
-V
OL
A
v
(0)
=
4.7V
7696
= 0.611mV
Next, we find the poles of the comparator, p
1
and p
2
. From Ex. 6.3-1 we find that
p
1
=
g
ds2
+ g
ds4
C
I
=
15x10
-6
(0.04+0.05)
0.2x10
-12
= 6.75x10
6
(1.074MHz)
and
p
2
=
g
ds6
+ g
ds7
C
II
=
95x10
-6
(0.04+0.05)
5x10
-12
= 1.71x10
6
(0.272MHz)
Linear Step Response of the Two-Stage Comparator
The step response of a circuit with two real poles (p
1
p
2
) is,
v
out
(t) = A
v
(0)V
in
|
|
|
|
|
|
|
|
1 +
p
2
e
-tp
1
p
1
-p
2
-
p
1
e
-tp
2
p
1
-p
2

Normalizing gives,
v
out
(t
n
) =
v
out
(t)
A
v
(0)V
in
= 1 -
m
m-1
e
-t
n
+
1
m-1
e
-mt
n
where m =
p
2
p
1
1 and t
n
= tp
1
=
t
1

If p
1
= p
2
(m =1), then v
out
(t
n
) = 1 - p
1
e
-t
n
-
t
n
p
1
e
-t
n
= 1 - e
-t
n
- t
n
e
-t
n
where p
1
= 1.
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10
Normalized Time (t
n
= tp
1
= t/
1
)
N
o
r
m
a
l
i
z
e
d

O
u
t
p
u
t

V
o
l
t
a
g
e
m = 0.25
m = 0.5
m = 1
m = 2
m = 4
m =
p
2
p
1
Fig. 8.2-2
Linear Step Response of the Two-Stage Comparator - Continued
The above results are valid as long as the slope of the linear response does not exceed the
slew rate.
Slope at t = 0 is zero
Maximum slope occurs at (m 1)
t
n
(max) =
ln(m)
m-1

and is
dv
out
(t
n
(max))
dt
n
=
m
m-1
|
|
|
|
|
|
exp
\
|
[
)
j
-ln(m)
m-1
- exp
\
|
[
)
j
-m
ln(m)
m-1

For the two-stage comparator using NMOS input transistors, the slew rate is
SR
-
=
I
7
C
II

SR
+
=
I
6
-I
7
C
II
=
0.5
6
(V
DD
-V
G6
(min)-|V
TP
|)
2
- I
7
C
II
Example 2-2 - Step Response of Ex. 2-1
Find the maximum slope of Ex. 2-1 and the time at which it occurs if the magnitude
of the input step is v
in
(min). If the dc bias current in M7 is 100A, at what value of load
capacitance, C
L
would the transient response become slew limited? If the magnitude of
the input step is 100v
in
(min), what is the new value of C
L
at which slewing would occur?
Solution
The poles of the comparator were given in Ex. 2-1 as p
1
= -6.75x10
6
rads/sec. and p
2
= -1.71x10
6
rads/sec. This gives a value of m = 0.253. From the previous expressions,
the maximum slope occurs at t
n
(max) = 1.84 secs. Dividing by |p
1
| gives t(max) =
0.272s. The slope of the transient response at this time is found as
dv
out
(t
n
(max))
dt
n
= -0.338[exp(-1.84) - exp(-0.2531.84)] = 0.159 V/sec
Multiplying the above by |p
1
| gives
dv
out
(t(max))
dt
= 1.072V/s
Therefore, if the slew rate is less than 1.072V/s, the transient response will experience
slewing. Also, if C
L
100A/1.072V/s or 93.3pF, the comparator will slew.
If the input is 100v
in
(min), then we must unnormalize the output slope as follows.
dv
out
(t( max))
dt
=
v
in
v
in
(min)

dv
out
(t( max))
dt
= 1001.072V/s = 107.2V/s
Therefore, the comparator will now slew with a load capacitance of 0.933pF.
Propagation Delay Time (Non-Slew)
To find t
p
, we want to set 0.5(V
OH
-V
OL
) equal to v
out
(t
n
). However, v
out
(t
n
) given as
v
out
(t
n
) = A
v
(0)V
in
|
|
|
|
|
|
1 -
m
m-1
e
-t
n
+
1
m-1
e
-mt
n

cant be easily solved so approximate the step response as a power series to get
v
out
(t
n
) A
v
(0)V
in
|
|
|
|
|
|
|
|
1 -
m
m-1
\
|
|
[
)
j
j
1-t
n
+
t
n
2
2
+ +
1
m-1
\
|
|
[
)
j
j
1-mt
n
+
m
2
t
n
2
2
+
mt
n
2
A
v
(0)V
in
2
Therefore, set v
out
(t
n
) = 0.5(V
OH
-V
OL
)
V
OH
+V
OL
2

mt
pn
2
A
v
(0)V
in
2
or
t
pn

V
OH
+V
OL
mA
v
(0)V
in
=
V
in
(min)
mV
in
=
1
mk

This approximation is particularly good for large values of k.
Example 2-3 - Propagation Delay Time of a Two-Pole Comparator (Non-Slew)
Find the propagation time delay of Ex. 2-1 if V
in
= 10mV, 100mV and 1V.
Solution
From Ex. 2-1 we know that
V
in
(min) = 0.611mV and m =
0.253. For V
in
= 10mV, k =
16.366 which gives t
pn
0.491.
The propagation time delay is
equal to 0.491/6.75x10
6
or
72.9nS.

This corresponds well
with Fig. 8.2-2 where the
normalized propagation time
delay is the time at which the
amplitude is 1/2k or 0.031
which corresponds to t
pn
of
approximately 0.5. Similarly,
for V
in
= 100mV and 1V we get
a propagation time delay of
23ns and 7.3ns, respectively.
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10
Normalized Time (t
n
= tp
1
= t/
1
)
N
o
r
m
a
l
i
z
e
d

O
u
t
p
u
t

V
o
l
t
a
g
e
m = 0.25
m = 0.5
m = 1
m = 2
m = 4
m =
p
2
p
1
Fig. 8.2-2A
= 0.031
0.52
1
2k
t
p =
6.75x10
6
0.52
= 77ns
Initial Operating States for the Two-Stage, Open-Loop Comparator
What are the initial operating states for
the two-stage, open-loop comparator?
1.) Assume v
G2
= V
REF
and v
G1
>V
REF
with i
1
0.
Initially, i
4
> i
2
and v
o1
increases,
M4 becomes active and i
4
decreases
until i
3
= i
4
. v
o1
is in the range of,
V
DD
- V
SD4
(sat) < v
o1
< V
DD
, v
G1
> V
REF
, i
1
 0
and the value of v
out
is
v
out
V
SS
v
G1
> V
REF
, i
1
 0
2.) Assume v
G2
= V
REF
and v
G1
>>V
REF
, therefore i
1
= I
SS
and i
2
= 0 which gives
v
o1
= V
DD
and v
out
= V
SS
v
G1
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+
-
C
II
Fig. 8.2-3
v
G2
i
1
i
2
C
I
I
SS
v
o1
i
4 i
3
Initial Operating States - Continued
3.) Assume v
G2
= V
REF
and v
G1
< V
REF
with i
1
>0 and i
2
<I
SS
.
Initially, i
4
< i
2
and v
o1
decreases. When v
o1
V
REF
- V
TN
, M2 becomes active and
i
2
decreases. When i
1
= i
2
= I
SS
/2 the circuit stabilizes and v
o1
is in the range of,
V
REF
- V
GS2
< v
o1
< V
REF
- V
GS2
+ V
DS2
(sat)
or
V
S2
< v
o1
< V
S2
+ V
DS2
(sat), v
G1
< V
G2
, i
1
> 0 and i
2
< I
SS
For the above conditions,
v
out
= V
DD
- (V
DD
-v
o1
-|V
TP
|)
|
|
|
|
|
|
|
|
1 - 1 -
7
I
SS
6
(V
DD
-v
o1
-|V
TP
|)
2

4.) Assume v
G2
= V
REF
and v
G1
<< V
REF
, therefore i
2
= I
SS
and i
1
= 0.
Same as in 3.) but now as v
o1
approaches v
S2
with I
SS
/2 flowing, the value of v
GS2
becomes larger and M5 becomes active and I
SS
decreases. In the limit, I
SS
0,v
DS2
0
and v
DS5
0 resulting in
v
o1
V
SS
and v
out
= V
DD
- (V
DD
-V
SS
-
|V
TP
|)
|
|
|
|
|
|
|
|
1 - 1 -
7
I
SS
6
(V
DD
-V
SS
-|V
TP
|)
2

5.) Assume v
G1
= V
REF
and v
G2
>V
REF
with i
2
0.
Initially, i
4
< i
2
and v
o1
falls, M2 becomes active and i
2
decreases until i
1
= i
2
= I
SS
/2.
Therefore,
V
REF
- V
GS2
(I
SS
/2) < v
o1
< V
REF
- V
GS2
(I
SS
/2) +V
DS2
(sat)
or
V
S2
(I
SS
/2) < v
o1
< V
S2
(I
SS
/2) + V
DS2
(sat), v
G2
> V
REF
, i
1
> 0 and i
2
> V
REF
. When the source voltage of M1 or M2
causes M5 to be active, then I
SS
decreases and
v
o1
V
SS
and v
out
= V
DD
- (V
DD
-V
SS
-|V
TP
|)
|
|
|
|
|
|
|
|
1 - 1 -
7
I
SS
6
(V
DD
-V
SS
-|V
TP
|)
2

7.) Assume v
G1
= V
REF
and v
G2
< V
REF
and i
1
 0. Consequently, i
4
>i
2
which causes v
o1
to increase. When M4 becomes active i
4
decreases until i
2
= i
4
at
which v
o1
stabilizes at (M6 will be off under these conditions and v
out
V
SS
).
V
DD
- V
SD4
(sat) < v
o1
< V
DD
, v
G2
< V
REF
, i
1
 0
8.) Finally if v
G2
<<V
REF
, then i
1
= I
SS
and i
2
=0 and
v
o1
V
DD
and v
out
V
SS
.
Summary of the Initial Operating States of the Two-Stage, Open-Loop Comparator using
a N-channel, Source-coupled Input Pair:
Conditions Initial State of v
o1
Initial State of v
out
v
G1
>V
G2
, i
1
0 V
DD
-V
SD4
(sat) < v
o1
< V
DD
V
SS
v
G1
>>V
G2
, i
1
=I
SS
and i
2
=0 V
DD
V
SS
v
G1
<V
G2
, i
1
>0 and i
2
0 and i
2
V
G1
, i
1
>0 and i
2
>V
G1
, i
1
>0 and i
2
0 V
DD
-V
SD4
(sat) < v
o1
< V
DD
V
SS
v
G2
<<V
G1
, i
1
=I
SS
and i
2
=0 V
DD
V
SS
TO BE CONTINUED IN THE NEXT LECTURE

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Lecture 370 Two-Stage Open-Loop Comparators-I (4/5/02) Page 370-1

ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

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