Lmos Evolution

6.720J/3.
43J - Integrated Microelectronic Devices - Spring 2007
Lecture 33-1
Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Eect Transistor (cont.) April 30, 2007 Contents: 1. MOSFET scaling (cont.) 2. Evolution of MOSFET design
Cite as: Jess del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 33-2
Key questions How has MOSFET scaling been taking place? Are there fundamental limits to MOSFET scaling? How far will MOSFET scaling go?
Lecture 33-3
1. Scaling (cont.) Scaling goal: extract maximum performance from each generation (maximize Ion), for a given amount of: short-channel eects (DIBL), and o-current To preserve electrostatic integrity, scaling has proceeded in a harmonious way: L (), W (), xox (), NA (), xj (), and VDD ().
Lecture 33-4
Illustration of key trade-os: Ion vs. Ioff
1E-01 MIT SSR III CMOS Technology 1E-02 1E-03 Ioff ( A/ m) 1E-04 1E-05 1E-06 1E-07 1E-08 0 200 400 Ion ( A/ m) 600 800 Vdd=2 V
Lecture 33-5
Ion vs. DIBL
Lecture 33-6
Limits to scaling
Text removed due to copyright restrictions. Markoff, John. "Chip Progress Forecast to Hit a Big Barrier." The New York Times (October 9, 1999).
The New York Times (Oct. 9, 1999)
Lecture 33-7
Four kinds of limits: Thermodynamics: doping concentration in source and drain Physics: tunneling through gate oxide Statistics: statistical uctuation of body doping Economics: factory cost
tunneling through gate oxide gate source drain
statistical fluctuations in body doping
doping concentration in source and drain
Lecture 33-8
Economics: factory cost also follows Moores law!
New factories cost well in excess of $1B!
Lecture 33-9
Physics: tunneling through gate oxide (most severe limit)
Ioff (100oC) Ioff (25oC)
Figure 13 on p. 491 in: Taur, Y., et al. "CMOS Scaling into the Nanometer Regime." Proceedings of the IEEE 85, no. 4 (1997): 486-504. 1997 IEEE.
Oxides thickness limit when: Igate Ioff @ VDD 1 V, Toper ( 100oC ) Translates to limiting gate current: Igate(25o C ) 100 pA Limiting gate current density: A 0.1 m 0.1 m = 1010 cm2 Jgate(25o C ) 1 A/cm2 Limiting xox 1.6 nm L 35 50 nm Solution: high-dielectric constant gate insulator
Lecture 33-10
Current wisdom for limiting bulk CMOS (with nitrided gate oxides): xox 1.2 nm Leff 25 35 nm but... unclear if industry will do it (there are better options).
What does this mean? Arno Penzias [1997]: We can look forward to a million-fold increase in the power of microelectronics. 10X transistor size reduction 100X device density 100X circuit speed 100X surprise 106X TOTAL To go beyond this, need: new materials that squeeze more performance out of existing device architecture new channel materials: strained Si, Si/SiGe heterostructores new gate insulators: high-K dielectric, such as HfO new gate conductors: metal gate, such fully silicided gate new device architecture (SOI, double gate, trigate) to improve electrostatic integrity
Lecture 33-11
2. Evolution of MOSFET design PMOS with metal gate:
Al gate
p+ n
circaearly 70s L 20 m A xox 1000 xj 3 m VDD = 12 V
p+
Main point: Na+ contamination made NMOS devices to have too negative a threshold voltage
Lecture 33-12
NMOS with metal gate:
Al gate
n+ p
circa1975 L 15 m A xox 600 xj 2 m VDD = 12 V
n+
Main point: with Na+ contamination under control, NMOS devices became possible (higher performance).
Lecture 33-13
CMOS with self-aligned polySi gate:

n+-polySi gate
n+ p
n+
circa1980 L 2 m A xox 400 xj 1 m VDD = 5 V
Main point: self-aligned process allows tighter overlap between gate and n+ regions and results in lower parasitic capacitance.
Lecture 33-14
Lightly-doped drain MOSFET (LDD-MOSFET):

polycide gate: deposited silicide (TaSi) n+-polySi n p
n+
n+
circa1985 L 0.75 m A xox 200 xj 0.2 m VDD = 5 V
Main point: lightly-doped n-region on drain side reduces electric eld there and allows a high VDD to be used.
Lecture 33-15
Salicide (self-aligned silicide) MOSFET:

self-aligned silicide (TaSi) n+-polySi n p
n+
n+
circa1989 L 0.4 m A xox 125 xj 0.15 m VDD = 3.3 V
Main point: salicided gate, source and drain reduces all parasitic resistances.
Lecture 33-16
MOSFET with p-pocket or halo implants:
n+
n p+ p
n p+
n+
circa1994 L 0.15 m A xox 60 xj 0.08 m VDD = 2.5 V Main point: p+ pockets control short-channel eects.
Lecture 33-17
Sub-0.1 m MOSFET:
n+
n p+ p+
n p+ p
n+
super-steep retrograde body doping
circalate 90s (manufacturing in early 00s) L < 0.1 m A xox 30 xj 0.06 m VDD = 0.8 1.5 V Main point: p+-super-steep retrograde body doping controls shortchannel eects while preserving high mobility.
Lecture 33-18
New device architecture: Silicon-on-Insulator (SOI)
Figure 25.1.1 in: Shahidi, G.G., et al. "Partially-depleted SOI Technology for Digital Logic." International Solid-State Circuits Conference, San Francisco, CA, Feb. 15-17, 1999. Digest of Technical Papers. New York, NY: Institute of Electrical and Electronics Engineers, 1999, pp. 426-427. ISBN: 9780780351264. 1999 IEEE.
A number of issues associated with existence of buried oxide: reduced junction capacitance oating body: kink eect, extra drive (VBS > 0 during switching) increased thermal resistance
Lecture 33-19
New device architecture: Dual-gate MOSFET
Figure 26 in Taur, Y., et al. "CMOS Scaling into the Nanometer Regime." Proceedings of the IEEE 85, no. 4 (1997): 486-504. 1997 IEEE.
Figure 29 in Taur, Y., et al. "CMOS Scaling into the Nanometer Regime." Proceedings of the IEEE 85, no. 4 (1997): 486-504. 1997 IEEE.
Lecture 33-20
Intels current (public) view of MOSFET scaling...
Chau, R., et.al. "Advanced CMOS Transistors in the Nanotechnology Era for High-Performance, Low-Power Logic Applications." In Proceedings of the 7th International Conference on Solid-State and Integrated Circuit Technology. Beijing, China: IEEE Press, 2004, pp. 26-30. Copyright 2004, IEEE. Used with permission.
Lecture 33-21
Key conclusions MOSFET scaling has taken place in a harmonious way with all dimensions and voltage scaling down. The end of conventional MOSFET scaling is close! Biggest barrier to MOSFET scaling is gate oxide leakage: need new gate dielectric with higher dielectric constant. To improve electrostatic integrity with limited oxide scaling: SOI, double gate designs, triple gate designs. To improve performance: use strained Si or strained-Si/SiGe heterostructures. Also, use metal gate.

Lmos Evolution

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Lmos Evolution

Uploaded by

Copyright:

Available Formats

6.720J/3.

43J - Integrated Microelectronic Devices - Spring 2007

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

Illustration of key trade-os: Ion vs. Ioff

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

Ion vs. DIBL

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

The New York Times (Oct. 9, 1999)

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

tunneling through gate oxide gate source drain

statistical fluctuations in body doping

doping concentration in source and drain

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

Economics: factory cost also follows Moores law!

New factories cost well in excess of $1B!

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

Physics: tunneling through gate oxide (most severe limit)

Ioff (100oC) Ioff (25oC)

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

2. Evolution of MOSFET design PMOS with metal gate:

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

NMOS with metal gate:

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

CMOS with self-aligned polySi gate:

circa1980 L 2 m A xox 400 xj 1 m VDD = 5 V

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

Lightly-doped drain MOSFET (LDD-MOSFET):

circa1985 L 0.75 m A xox 200 xj 0.2 m VDD = 5 V

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

Salicide (self-aligned silicide) MOSFET:

circa1989 L 0.4 m A xox 125 xj 0.15 m VDD = 3.3 V

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

MOSFET with p-pocket or halo implants:

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

super-steep retrograde body doping

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

New device architecture: Silicon-on-Insulator (SOI)

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

New device architecture: Dual-gate MOSFET

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

Intels current (public) view of MOSFET scaling...

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007

You might also like