LOGIC CIRCUITS AND SWITCHING THEORY

Engr. John David M. Ramos

Number Systems
Generalizations: 1. There is no number system with a base of 1 2. The no. of symbols in any number system is the radix (base) 3. The highest symbol in any number system is equal to radix -1 4. The highest symbol plus 1 equals 0 with carry 1

Decimal System - said to be of base 10 because it uses 10 digits and the coefficients are multiplied by powers of 10
Ex: 11010.11

Ex: 7392

Binary System - 2 possible values 0 and 1

Ex: (4021.2)5 Ex: B65F16

In general, a number expressed in base r system has coefficients multiplied by powers of r

Addition, Subtraction and Multiplication of Binary Numbers

Addition
101101
100111

Augend
Addend

1010100

Subtraction
101101 100111 Minuend Subtrahend

000000

Multiplication
1011 101 Multiplicand Multiplier

110111

Number Base Conversion

Number Systems
Binary Codes

Bit - binary digit - to represent a group of 2n distinct elements in a binary code requires a minimum of n bits - it is possible to arrange n bits in 2n distinct ways
N=2 2 n = 22 = 4 00,01,10,11

Decimal Codes
BCD - Binary Coded Decimal - a straight assignment of the binary equivalent - it is possible to arrange n bits in 2n distinct ways - difference between conversion of a decimal number to binary and the binary coding of a decimal number
Ex. 13 BCD
Binary

0001

0011
1101

Decimal Digit
0 1

BCD
0000 0001

Excess 3
0011 0100

2
3 4

0010
0011 0100

1010
0110 0111

5
6 7

0101
0110 0111

1000
1011 1010

8
9

1000
1001

1011
1100

Error Detection Codes

Parity Bit an extra bit included with a message to make the total no. of 1s either odd or even Ex: 0111 odd P = 0 even P = 1

Reflected Code Gray Code - a number in the reflected code changes by only one bit as its provides from one number to the next
Alphanumeric Codes - binary code of a group of elements consisting of the 10 decimal digits, the 26 letters of the alphabet and a certain number of special symbol such as $

Number Systems
ASCII American Standard Code for Information Interchange

Number Systems
EBCDIC Extended Binary Coded Decimal Interchange Code

Basic Logical Operations

1. AND (Intersection) - represented by a dot or by the absence of an operator x.y = z or xy = Z x AND y is equal to z - a logic circuit where output is high only when all inputs are high - interpreted to mean that z=1 if and only if x = 1 and y = 1 otherwise z = 0

Truth Table - a table that shows all input and output possibilities for a logic circuit
X 0 0 Y 0 1 Z 0 0

1 1

0 1

0 1

Basic Logical Operations

2. OR (Union) - represented by a plus sign x+y=z x OR y is equal to Z - a logic circuit with 2 or more inputs and only one output. 1 or more high inputs produce a high output

Z = 1 if X = 1 or if Y = 1 or if both X = 1 and Y = 1. If both X = 1, Y = 0 then Z = 0

X 0 0 Y 0 1 Z 0 1

1 1

0 1

1 1

Basic Logical Operations

3. NOT (Inversion) - represented by a prime (sometimes by a bar) X = Z ( or X = Z ) X NOT is equal to Z - a gate with only 1 input and 1 output (Complement)

if:

X = 1 then Z = 0 X = 0 then Z = 1
X 0 Z 1

Logic Gates
Electronic Digital Circuits Logic Circuits Block of hardware that produces a Logic 1 or Logic 0 output signal if input logic requirements are satisfied Digital Circuits Switching Circuits

Other Logic Operations

1. NOR Function - complement of the OR function and its name is an abbreviation of Not-OR - all inputs be low to get a high output

X
0 0 1 1 2. NAND Function - complement of AND - abbreviation of Not-AND

Y
0 1 0 1

F
1 0 0 0

X 0
0 1 1

Y 0
1 0 1

F 1
1 1 0

Other Logic Operations

3. Exclusive OR (XOR or EOR) - similar to OR but excludes the combination of both X and Y equal to 1 X 0 Y 0 F 0

0
1 1

1
0 1

1
1 0

4. Equivalence or Exclusive NOR or Exclusive OR-Not - a function that is 1 when the 2 binary variables are equal i.e. when both are o or both are 1. X Y F

0
0

0
1

1
0

1
1

0
1

0
1

Other Logic Operations

5. Buffer - produces a transfer function but does not produce any particular logic operation since the binary value of the output is equal to the binary value of the input X 0 1 F 0 1

NOR

NAND

XOR

XNOR

Boolean Algebra

Boolean Algebra ( Symbolic Logic)

- A set of elements, a set of operators and a number of unproved axioms or postulates History of Boolean Algebra 1854- George Boole introduced a systematic treatment of logic and developed for this purpose an algebraic system 1938 C.E Shannon introduced a 2-valued Boolean Algebra, in which he demonstrated that the properties of bistable electrical switching circuits can be represented by this algebra

Basic Theorems and Principles of Boolean Algebra

Duality Principle Every algebraic expression deducible from the postulates of Boolean Algebra remains valid if its operators and identity elements are interchanged
If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1s by 0s and 0s by 1s

Postulates and Theorems of Boolean Algebra

1. X + 0 = x ;X.1=X

2. X + X = 1
3. X + X = 1 4. X + 1 = 1

; X . X = 0
;X.X=X ;X.0=0

5. (X) = 1
6. X + Y = Y + X ; XY = YX 7. X + (Y + Z) = (X + Y) + Z 8. X (Y + Z) = XY + YZ ; X(YZ) = (XY)Z ; X + YZ = (X + Y) (X + Z)

Involution
Commutative Associative Distributive

9. (X + Y) = XY
10. X + XY = X

; (XY) = X + Y
; X (X + Y) = X

De Morgans
Absorption

BOOLEAN FUNCTIONS
Binary variable can take the value of 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators OR and AND. Ex. F = xyz + xyz + xy F = (A + B)(A+C)

MINTERMS

Binary variable may appear either

Normal form (x) Complement form (x)

-Primed variables corresponds to a binary number 0

-Unprimed variables corresponds to a binary number 1

MINTERMS
Ex. Consider two binary variables x and y combined with an AND operation: Since, each variable may appear in either form, there are 4 possible combinations. (from 2n. Where n is the no. of variables) xy xy

x y
xy Each of these four AND terms are called minterm or a standard product

MAXTERMS
A variable forming an OR terms Primed variables corresponds to a binary number 1 Unprimed variables corresponds to a binary number 0

MINTERMS x y z TERM DESIGNATION

m0
m1 m2 m3 m4 m5 m6

MAXTERMS x y z TERM DESIGNATION

0
0 0 0

0
0 1 1

0
1 0 1

xyz
xyz xyz xyz

0
0 0 0

0
0 1 1

0
1 0 1

x+y+z
x+y+z x+y+z x+y+z

M0
M1 M2 M3

1
1 1

0
0 1

0
1 0

xyz
xyz xyz

1
1 1

0
0 1

0
1 0

x+y+z
x+y+z x+y+z

M4
M5 M6

xyz

m7

x+y+z

M7

SUM OF MINTERMS
Boolean function can be expressed as a sum of minterms. The minterms whose sum defines the Boolean function are those that give the 1s of the function in a truth table.

Example
Express the Boolean function F = A + BC in a sum of minterms.

Truth Table for F = A + BC

A B C TERM DESIGNATION
m0 0

0 0
0 0 1

0 0
1 1 0

0 1
0 1 0

ABC ABC
ABC ABC ABC

m1
m2 m3 m4 m5

1
0 0 1 1

1 1
1

0 1
1

1 0
1

ABC ABC
ABC

m6
m7

1
1

PRODUCT OF MAXTERMS
To express the Boolean function as a product of maxterms, it must first be brought into a a form of OR terms. This may be done by using the distributive law, x + yz = (x + y)(x + z) Then, any missing variable n in each OR term is Ored with nn .

EXAMPLE
Express the Boolean function F = xy + xz in a product of maxterm form.

CONVERSION BETWEEN CANONICAL FORMS

The complement of a function expressed as the sum of minterms equals the sum of minterms missing from the original function.

Example:
F(A, B, C) = (1, 4, 5, 6, 7)

This has a complement that can be expressed as F(A, B, C) = (0, 2, 3) = m0 + m2 + m3

CONVERSION BETWEEN CANONICAL FORMS

Now, take the complement of F by DeMorgans Theorem; F = (m0 + m2 + m3) = m0.m2.m3 = M0M2M3 = (0, 2, 3)

KARNAUGH MAP

MAP METHOD
First proposed by Veitch and modified by Karnaugh, is also known as the Veitch Method or the Karnaugh Map

The map is a diagram made up of squares. Each square represents one minterm.

MAP METHOD
Advantages:
Presents a visual diagram of all possible ways a function may be expressed in a standard form. Derive alternative algebraic expressions for same function

MAP METHOD
Types of Maps
2-Variable Map 3-Variable Map 4-Variable Map

2-VARIABLE MAP
There are four minterms for two variables. The map consists of four squares, one for each minterm.
x y 0 1

m0

m1

m0

m1

m2

m3

m2

m3

2-VARIABLE MAP
Example: Represent F = x + y using K-map. Soln: F = x(y + y) + y (x + x) = xy + xy + xy + xy F = xy + xy + xy = m1 + m2 + m3

2-VARIABLE MAP
the function x + y is represented in the map by three squares marked with 1s.
x 0
y y

0
m0

1
m1

x 0

1
1

m2

m3

3-VARIABLE MAP
There are 8 minterms for three binary variables. Map consists of eight squares
yz

x 0

00 m0 m4

01 m1 m5

11 m3 m7

10 m2 m6

3-VARIABLE MAP
Simplify the Boolean function
F(x, y, z) = (2, 3, 4, 5)
yz x 0

00

01

11 1

10 1

F = xy + xy

3-VARIABLE MAP
Simplify the Boolean function F(x, y, z) = (3, 4, 6, 7)
yz x

00

01

11 1

10

0 1

F = yz + xz

3-VARIABLE MAP
The number of adjacent squares that may be combined must always represent a number that is a power of two such as 1, 2, 4, and 8. as a larger number of adjacent squares are combined, we obtain a product term with fewer literals.
One square represents one minterm, giving a term of 3 literals Two adjacent squares represent a term of two literals Four adjacent squares represent a term of one literal Eight adjacent squares encompass the entire map and produce a function that always equal to 1

3-VARIABLE MAP
Simplify the Boolean function F(x, y, z) = (0, 2, 4, 5, 6)
yz x

00 1 1

01

11

10 1

F = z + xy

3-VARIABLE MAP
Try this! Given the Boolean function: F = AC + AB + ABC + BC

(a) Express the function in sum of minterms (b) Find the minimal sum of products expression

4-VARIABLE MAP
16 minterms for four binary variables Map consists of 16 squares
wx yz 00 m0 m4 m12 01 m1 m5 m13 11 m2 m6 m15 10 m3 m7 m14

00
01 11 10

m8

m9

m11

m10

4-VARIABLE MAP
One square represents one minterm, giving a term of four literals Two adjacent squares represents a term of three literals Four adjacent squares represents a term of two literals Eight adjacent squares represents a term of one literals Sixteen adjacent squares represents a function equal to 1

Example
Given the Boolean function;

F = wyz +wyz + wxy

* Simplify the function using K-map.

Characteristics of the Basic Gate

1. Fan-out - specifies the no. of standard loads that the output of the gate can drive without impairment of its normal operation Standard Load- the current flowing in the input of a gate in the same IC family Power Dissipation - power consumed by the gate which must be available from the power supply Propagation Delay - the average transition delay time for the signal to propagate from input to output when the signals change in value Noise Margin - the limit of a noise voltage which may be present without impairing the proper operation of the circuit

2.
3. 4.

Dont Care Conditions

There are applications where certain combination of input variables never occur. As a result, we dont care what the function output is to be for those combination of the variables because they are guaranteed to never occur. However, these can be used on a map to provide further simplification of the function. When choosing adjacent squares to simplify the function in the map, the xs may be assumed to be either 0 or 1, which even gives the simplest expression. An x need not be used at all if it does not contribute to covering a larger area

COMBINATIONAL LOGIC CIRCUITS

Combinational Logic Circuits

-consists of logic gates whose outputs at any time are determined directly from the present combination of inputs without regard to previous inputs Half Adder -2 binary inputs and 2 binary outputs
Input Augend Output Sum Where: S = xy + xy

Addend
X 0

Carry
Y 0 C 0

C = xy
S 0

0
1 1

1
0 1

0
0 1

1
1 0

Combinational Logic Circuits

Full Adder -a combinational circuit that forms the arithmetic sum of 3 input bits - consists of 3 inputs and 2 outputs
X
0 0 0

Y
0 0 1

Z
0 1 0

C
0 0 0

S
0 1 1

0 1
1 1 1

1 0
0 1 1

1 0
1 0 1

1 0
1 1 1

0 1
0 0 1

Sum: S = xyz + xyz +xyz +xyz

Carry: C = xy + xz + yz

Combinational Logic Circuits

Decoder - a combinational logic circuit that recognizes the presence of a specific binary no. or word. The input is a multibit binary no. and the output is a signal that indicates the presence of a specific no. of bit combination - a combinational circuit that converts binary information from n inputs to a maximum of 2n unique output lines n to m lines decoders

When m =< 2 Encoder - a digital function that produces a reverse operation from that of a decoder. - a combinational logic circuit that accepts one or more inputs and generates a unique multibit binary output. The encoder generates a number or code in response to an input

Combinational Logic Circuits

Multiplexer (data selector circuit) - an electronic switch that permits any one of a number of inputs to be chosen and routed to the output - has 2 or more inputs and a single output - main function is to control the routing of data from one place to another Demultiplexer - a combinational logic circuit that receives information on a single line and transmits this information on one of 2n possible output lines Sequential Circuits - employ memory elements (binary cells) in addition to logic gates - their outputs are a function of the inputs and the state of the memory elements

Combinational Logic Circuits

Synchronous Sequential Circuit - a system whose behavior can be defined from the knowledge of its signals at discrete instant of time - depends upon the order in which its input signals change and can be affected at any instant of time
Flip Flop - a 2 state circuit that can remain in either state indefinitely - also called a Bistable Multivibrator - an external trigger can change the output

Definition of Terms
Race Condition - an undesirable condition which may exist in a system when 2 or more inputs change simultaneously Register - a group of memory elements that work together as a unit - primary purpose is to store a word Buffer Register - a register that temporarily stores a word during data processing Shift Register - a register that can shift the stored bits one position to the left or right (shift left, shift right) Controlled Shift Register - has control inputs determine what it does on the next clock pulse Serial Loading - means storing a word in the shift register by entering 1 bit per clock pulse Parallel Loading (Broadside Loading) - loading all bits of a word in parallel during one clock pulse

Definition of Terms
Counter - a register capable of counting the member of clock pulses that have arrived at its clock input - electronic equivalent of a binary odometer Controlled Counter - counts clock pulses only when commanded to do so Synchronous Counters - a counter in which the clock drives each F/F to eliminate the ripple delay Ring Counter - a counter producing words with 1 high bit which shifts one position per clock pulse Other Counters Modulus of a Counter - the number of stable states a counter has Mod 10 Counter - divide by 10 circuit - decade counter Down Counter - counts down Up Down Counter - F/F outputs are connected to steering networks Presettable Counter - the counter starts at a number greater than 0

Definition of Terms
3 State Registers 3 State switch - a non inverting buffer that can be closed or opened by a control signal - a tri state switch Bus - a group of wires used as a common word path by several registers Memory - where the programs and data are stored before calculations begin Address - a way of specifying the location of data in memory, similar to a house address Access Time - the time it takes to read the contents of a memory location after it has been addressed Volatile - a type of memory in which data stored in the memory is lost when the power is turned off Non-Volatile - a type of memory in which the stored data is not lost when the power is turned off

SEQUENTIAL CIRCUITS

Introduction

A sequential circuit consists of a feedback path,

and employs some memory elements.
Combinational outputs Memory outputs

Combinational logic

Memory elements

External inputs

Sequential circuit = Combinational logic + Memory Elements

Introduction

There are two types of sequential circuits:

synchronous: outputs change only at specific time asynchronous: outputs change at any time

Multivibrator: a class of sequential circuits. They

can be:
bistable (2 stable states) monostable or one-shot (1 stable state) astable (no stable state)

Bistable logic devices: latches and flip-flops. Latches and flip-flops differ in the method used
for changing their state.

Memory Elements

Memory element: a device which can remember

value indefinitely, or change value on command from its inputs.

command Memory element Q stored value

Characteristic table:
Command (at time t) Set Reset Memorise / No Change Q(t) X X 0 1 Q(t+1) 1 0 0 1

Q(t): current state

Q(t+1) or Q+: next state

 Memory element with clock. Flip-flops are memory

elements that change state on clock signals.
command Memory element Q stored value

clock

Clock is usually a square wave. Positive pulses

Positive edges

Negative edges

 Two types of triggering/activation:

pulse-triggered edge-triggered

Pulse-triggered
latches ON = 1, OFF = 0

Edge-triggered
flip-flops positive edge-triggered (ON = from 0 to 1; OFF = other

time) negative edge-triggered (ON = from 1 to 0; OFF = other time)

Latch

A type of memory storage device that has two

stable states (bistable) and is normally placed in a category separate from that of flip-flops.

Latches are basically similar to flip-flops, the main

difference between them is in the method used for changing their state.

A latch can be implemented using 2 NOR gates or

2 NAND gates.

S-R Latch
For active-LOW input S'-R' latch (also known as NAND
gate latch), R'=LOW (and S'=HIGH) a RESET state S'=LOW (and R'=HIGH) a SET state both inputs HIGH a no change both inputs LOW a Q and Q' both HIGH (invalid)!

Drawback of S-R latch: invalid condition exists and

must be avoided.

S-R Latch
S 0 1 0 1 R 0 0 1 1

Characteristics table for active-high input S-R latch:

Q NC 1 0 0 Q' NC 0 1 0 No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.
S
R

Q
Q'

Characteristics table for active-low input S'-R' latch:

S' 1 0 1 0 R' 1 1 0 0 Q NC 1 0 1 Q' NC 0 1 1 No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.
S R Q Q'

S-R Latch
10 100 R

Active-HIGH input S-R latch

Q 11000 Q' 0 0 1 1 0
S 1 0 0 0 1 R 0 0 1 0 1 Q Q' 1 0 initial 1 0 (afer S=1, R=0) 0 1 0 1 (after S=0, R=1) 0 0 invalid!

10 001 S

Active-LOW input S-R latch

S' Q Q' R'

S'

Q Q'

R'

S' R' 1 0 1 1 0 1 1 1 0 0

Q Q' 0 1 initial 0 1 (afer S'=1, R'=0) 1 0 1 0 (after S'=0, R'=1) 1 1 invalid!

Latch Circuits: Not Suitable

circuits.

Latch circuits are not suitable in synchronous logic

When the enable signal is active, the excitation inputs
are gated directly to the output Q. Thus, any change in the excitation input immediately causes a change in the latch output.

The problem is solved by using a special timing control

signal called a clock to restrict the times at which the states of the memory elements may change.

This leads us to the edge-triggered memory elements

called flip-flops.

Flip-flops

Flip-flops: synchronous bistable devices Output changes state at a specified point on a

triggering input called the clock. Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal.
Clock signal
Positive edges Negative edges

Flip-flops
FOUR FLIP-FLOP FUNCTIONS 1. Reset 2. Set 3. Toggle 4. No Change FOUR TYPES OF FLIP-FLOPS 1. S-R (Set-Rest) 2. D (Data or gated D-latch) 3. J-K 4. T (Toggle)

S-R Flip-flop

The S-R latch can be modified into an S-R flip-flop

by providing an additional control input that determines when the state of the circuit is to be changed. Usually, this additional control is in the form of a clock pulse (CP) Characteristic table of positive edge-triggered S-R flip-flop:
S 0 0 1 1 R 0 1 0 1 CLK X Q(t+1) Q(t) 0 1 ? Comments No change Reset Set Invalid

X = irrelevant (dont care) = clock transition LOW to HIGH

S-R Flip-flop

D Flip-flop

One way to eliminate the undesirable condition of

the indeterminate state in the S-R flip-flop is to ensure that inputs S and R are never equal to 1 at the same time. This is done by the D flip-flop. The D flip-flop receives the designation from its ability to hold data into its internal storage.
D S Q Q'
D 1 0 CLK Q(t+1) 1 0 Comments Set Reset

CLK

C
R

= clock transition LOW to HIGH

A positive edge-triggered D flip-flop formed with an S-R flip-flop.

Schematic Symbol

Example
Given the waveforms for the D input and the clock, determine the Q output waveform in the flip-flop starts out RESET. Assume that the positive edgetriggered flip-flop is given.

J-K Flip-flop
A J-K flip-flop is a refinement of the S-R flip-flop in that the indeterminate state of the S-R flip-flop is defined in the J-K flipflop. Inputs J and K behave like S and R, to set and reset the flip-flop, respectively. J S (set) and K R (reset) No invalid state. Include a toggle state.
J=HIGH (and K=LOW) a SET state K=HIGH (and J=LOW) a RESET state both inputs LOW a no change both inputs HIGH a toggle

Example
The waveforms are applied to the J, K and clock inputs as indicated. Determine the Q output, assuming that the negative edge-triggered flip-flop is initially RESET.

J-K Flip-Flop

T Flip-flop

T flip-flop is a single-input version of the J-K flip

flop. The designation T comes from the ability of the flip-flop to toggle or complement its state.

Asynchronous Inputs

S-R, D and J-K inputs are synchronous inputs, as data on

these inputs are transferred to the flip-flops output only on the triggered edge of the clock pulse. Asynchronous inputs affect the state of the flip-flop independent of the clock; example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)] When PRE=HIGH, Q is immediately set to HIGH. When CLR=HIGH, Q is immediately cleared to LOW. Flip-flop in normal operation mode when both PRE and CLR are LOW.

Asynchronous Inputs
inputs.
J
PRE J

A J-K flip-flop with active-LOW preset and clear

PRE Q Pulse transition detector Q'

Q
CLK

C
K Q'

K CLR

CLR CLK PRE CLR

J = K = HIGH

Preset

Toggle

Clear