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A New Optimal Space-vector Modulation Technique for Three-PhaseVoltage Source Inverters

Shao-Liang An, Jian-Yuan Wang, Xiang-Dong Sun, Yan-Ru Zhong


Department of Electrical Engineering Xian University of Technology Xian, China e-mail: shawn_an@163.com
AbstractIn this paper, a new optimal space-vector pulsewidth modulation (SVPWM) technique is presented for threephase voltage source inverters. 6 sectors are redivided into 12 ones based on SVPWM, and combining with local overmodulation method, the discontinuous SVPWM strategies called as DSVPWMx including DSVPWMP, DSVPWMN, DSVPWMPN1 and DSVPWMPN3 are proposed. The principle of the new DSVPWMx is developed, and essential relations among the different DSVPWMx strategies are discussed. The simulation and experimental results verify that the DSVPWMx strategies are right and feasible. Keywords-discontinuous SVPWM, inverter, overmodulation.

The conventional 6 sectors employed in SVPWM are redivided into 12 ones, the discontinuous SVPWM (DSVPWMx) strategies are proposed by means of local over modulation method and linearity transformation. The presented DSVPWMx strategies are proved by the theoretical analysis and simulation and experimental results. II. REFERENCE VOLTAGE OF DSVPWM

I.

INTRODUCTION

Space-vector pulse-width modulation (SVPWM) strategy is a mainstream for three-phase voltage source inverters (VSIs). A variety of pulse-width modulation (PWM) strategies defined as discontinuous PWM (DPWM) are obtained by changing locations and action time of the zero vectors in each switching period in order to reduce the switching times. Compared with continuous PWM (CPWM), when the switching frequencies are the same, DPWM strategies can effectively reduce the switching loss. Consequently, DPWM strategies are widely applied to the fields of power electronics such as AC drives [1,2], active filters [3,4], DC-DC converters [5,6]. Two zero vectors (000 and 111) and six non-zero vectors are used to achieve two 60 intervals without switching action, which are located respectively at the symmetrical peak areas of the positive and negative half cycle in each phase (DPWM1)[7]. Only zero vector (000) and other nonzero vectors are utilized to clamp output voltage to the negative DC bus voltage in the 120 interval in the negative half cycle of the reference voltage (DPWMMIN) [8]. The DPWMMAX strategy is proposed in [9], which utilizes only zero vector (111) and other non-zero vectors to clamp output voltage to the positive DC bus voltage in the 120 interval in the positive half cycle of the reference voltage. Reference [10] presents that there is an interval of 30 without switching operation every other 60 intervals for each phase (DPWM3). DPWMMAX, DPWMMIN, DPWM1 and DPWM3 are named as DPWMx in this paper.
This research is supported by Shanxi provincial project of special foundation of key disciplines.

Fig.1 shows a three-phase voltage source inverter, where, Lload and Rload are the inductance and resistance loads respectively. Six sectors in Fig.2-(a) are redivided into 12 ones as shown in Fig.2-(b), the corresponding 12 sectors to 0 ~ 2 in a fundamental cycle are labeled in Fig.3.The horizontal axis is the phase angle. The vertical axis is the normalization voltage, 1 and -1 mean +vdc and vdc respectively. Switching action does not occur in the sectors where the reference voltage is clamped to the positive or negative DC bus voltage, and these sectors are defined as discontinuous modulation sectors, while the others are named as continuous
P

~R ~S ~T
Figure 1.

vdc
o

s1
a

s3
b

s5
va
vb
Lloa d
Rload

vdc
s2
N

vc

s4

s6

Three-phase voltage source inverter.

(a) 6 sector Figure 2. (b) 12 sectors Basic space-vector sectors.

978-1-4577-0547-2/12/$31.00 2012 IEEE

TABLE I.

TRANSFORMATION COMPONENTS OF DSVPWMX


30 sectors

[ 0, [ / 6, [ 2 / 6, [ 3 / 6, [ 4 / 6, [ - ,
/ 6]
2 / 6] 3 / 6] 4 / 6] 5 / 6]

vz ** /vdc
P + P1 P + P3
P + P3 N + N3 N + N3 N + N1

1 2 3 4 Figure 3. Reference voltage of SVPWM, M=0.5. 5 6


va**

[ 5 / 6, [ -5 / 6, [ -4 / 6, [ -3 / 6, [ -2 / 6,

va

va***
vb** vc**
transformation

-5 / 6] -4 / 6] -3 / 6] -2 / 6] - / 6]

N + N1 N + N3
N +N3 P + P3 P + P3 P + P1

s1
vb***

8 9 10 11 12

vb* vc*
components
* zero sequence vz

s3
vc***

components

vaz ** vbz vc** z


**

s5

[ - / 6, 0]

Figure 4. Pulse generating method of DSVPWMx.

modulation sectors. Fig.4 is the pulse generating method of DSVPWMx strategies. The reference voltages va***, vb***, vc*** of DSVPWMx are defined by

TABLE II.

PARAMETER VALUES OF TRANSFORMATION COMPONENTS FOR SVPWM AND DSVPWMX


DSVPWMx , ( 0 = M 3 / 2) DSVPWMP DSVPWMN DSVPWMPN1 DSVPWMPN3

va ,b,c

***

= va ,b ,c + vaz ,bz ,cz

**

**

(1).

Type

SV PWM

*** +vdc , va ,b,c +vdc *** va ,b,c = *** vdc , va ,b ,c vdc

0 0 0 0 0 0

1 0 1 0
0 1 3 / 2

0 1 0 1

0 1
1 0
2 0

0 1
1 0

(2)

N P1
N1 P3 N3

are reference voltages of SVPWM expressed Where, by (3). The SVPWM is generated by the traditional sinetriangular PWM and zero-sequence voltage injection.

va,b,c**

)
0

3 / 2 +1

)
2 0

0 0

0
0 1 3 / 2

( (

3 / 2 1

) )

3 / 2 +1 2

)
0

0
3 / 2 1

0 0

3 / 2 +1

va ,b,c** = va ,b,c* + vz*

(3).

3 / 2 +1 2

Where, va,b,c* expresses three-phase sinusoidal reference voltages va*, vb*, vc* defined by (4). vz* is the zero-sequence components calculated by (5), (6) and (7).

a is the unit vector operator.

va = Mvm cos(t ) * vb = aMvm cos(t ) * 2 vc = a Mvm cos(t )


*

a = e j 2 /3
(4)

(8)

vm is the maximum magnitude of six non-zero vectors shown in Fig.2.

vz = (vmax + vmin ) / 2
vmax = max {va , vb , vc
* * * *

vm = 4vdc / 3
(5)

(9)

(6) (7)

Modulation index M is defined as the ratio of the reference voltage magnitude vo and its maximum value vm.

vmin * = min {va * , vb* , vc* }

M = vo / vm

(10)

vaz,bz,cz** in (1) are transformation components in each phase expressed by (11).

(a) DSVPWMP

(b) DSVPWMN

Figure 6. Reference voltages of SVPWM and DSVPWMPN1, M=0.5.

III.

ESSENTIAL RELATIONSHIPS AMONG SVPWM AND DSVPWMX REFERENCE VOLTAGES

(c) DSVPWMPN1

(d) DSVPWMPN3

Figure 5. Reference voltage of DSVPWMx, M=0.5.

vaz ** = vz ** ** ** vbz = avz ** 2 ** vcz = a vz

(11)

Where, vz** is the transformation component of phase a defined in Table . It can be seen that vz** equals either the sum of P and i (i=P1, P3) or the sum of N and j (j=N1, N3) depending on the 30 sectors. The values of P, N, P1, N1, P3 and N3 in Table are determined by the modulation strategy type of DSVPWMx including DSVPWMP, DSVPWMN, DSVPWMPN1 and DSVPWMPN3 as shown in Table . Especially, when all their values are equal to zero, DSVPWMx presents for SVPWM strategy. Therefore, reference voltages of DSVPWMx are obtained as shown in Fig.5. Reference voltage of DSVPWMP in Fig.5-(a) has unswitching interval of 120 in the positive half cycle of the reference voltage by comparison with DPWMMAX; Reference voltage of DSVPWMN in Fig.5-(b) places unswitching interval of 120 in the negative half cycle of the reference voltage, and it is corresponding to DPWMMIN; In a word, DSVPWMPN1 in Fig.5-(c), DSVPWMPN3 in Fig.5-(d) are defined respectively corresponding to DPWM1 and DPWM3. According to the different locations of the discontinuous modulation sectors in positive and negative half cycle, four strategies in Fig.5 are classified into two categories: unipolar DSVPWMx, their discontinuous sectors are in the positive half cycle (DSVPWMP) or in the negative half cycle (DSVPWMN); bipolar DSVPWMx, which is characterized by discontinuous sectors alternating in positive and negative half cycles of reference voltage (DSVPWMPN1, DSVPWMPN3). Obviously, the transformation of DSVPWMx reference voltage is very simple, which is implemented on the basis of SVPWM algorithm.

DSVPWMx reference voltages originate from the transformation results of SVPWM. However, this process is not just a simple transformation in style. To take reference voltages of SVPWM and DSVPWMPN1 for example, they are drawn in Fig.6. Observing the sectors 4, 5, 6, 7, 8 and 9 in Fig.6, i.e., the negative half cycle of DSVPWMPN1 reference voltage, reference voltage of DSVPWMPN1 in the sectors 6 and 7 is clamped to negative DC bus voltage. Its physical meaning is that the area enclosed by the inverter output voltages and their action time in the sectors 6 and 7 increases. In the light of volt-second balance, if linearity modulation must be satisfied, the reference voltages in the remaining sectors 4, 5, 8 and 9 should be transformed in a reverse direction in order to reduce the area enclosed by inverter output voltages and their action time in the sectors 4, 5, 8 and 9, so that the volt-second product in the negative reference voltage of DSVPWMPN1 equals or approximates to that in the negative half cycle of SVPWM. The transformation principle in the positive half cycle of DSVPWMPN1 reference voltage is the same as that in the negative half cycle. On the whole, other three modulation strategies are also designed in term of the volt-second balance like DSVPWMPN1. Therefore, the above analysis can be rearranged as follows: reference voltages of DSVPWMx strategies can be generated by injecting zero-sequence components into three-phase sinusoidal voltages and transformation components into SVPWM reference voltage, and output voltages corresponding to these two strategies are the same; its very easy to achieve DSVPWMx algorithm based on SVPWM on the account that transformation component vz** is constant in the same sector. IV. SIMULATION AND EXPERIMENTAL RESULTS The inverter based on new DSVPWMx strategies based on SVPWM is shown in Fig.1. The same circuit parameters are used in simulations and experiments as follows: threephase line voltage 229V/50Hz, DC bus voltage 298V, the switching frequency 10kHz, rated output voltage 117V/50Hz, rated output current 10A, rated output power 3.5kW, resistance load 16, inductance load 40mH. New DSVPW-Mx strategies are implemented in MATLAB Version 7.1 (R14). Experimental platform is built with a control core of Infineon microcontroller (XE164FM72F80L), and switching frequency and dead time are 10kHz

and 3s respectively. Its very easy to implement the software algorithm of SVPWM and DSVPWMx in accordance with Fig.4. Fig.7 to Fig.9 are simulation and experimental results of SVPWM and DSVPWMx, where, va*** is the reference voltage of phase a, vao is the output voltage of phase a, i.e., the voltage between a-phase bridge and the middle point of DC bus voltage, and ia is load current of phase a. Fig.7 are simulation and experimental results of continuous modulation SVPWM strategy when M=1.15, and it shows that output voltage of phase a varies between positive and negative DC bus voltages in the switching frequency mode. Fig.8 presents the simulation results of DSVPWMx when M=1.15. Its seen from that output currents of different strategies are very similar when M remains the same value indicating that different strategies of DSVPWMx meet the volt-second balance. Since the magnitude of output current of DSVPWMx is slightly more than that of SVPWM at the same modulation index, the voltage-utilization level of DSVPWMx is improved. Fig.9 provides experimental results of DSVPWMx and it shows similarly that vao is clamped to the positive and negative DC bus voltage in some intervals, and ia in Fig.8 and Fig.9 are almost the same due to the same strategy. We can achieve the same analysis from Fig.9 as from Fig.8. In short, simulation and experimental results are identical, they verify that different discontinuous modulation strategies correspond to different unswitching intervals, and output voltage of discontinuous modulation strategies is slightly greater than that of continuous modulation. V. CONCLUSION

(a) DSVPWMP

(b) DSVPWMN

(c) DSVPWMPN1

(d) DSVPWMPN3

The new DSVPWMx technique is presented by means of local overmodulation and linearity transformation and in accordance with volt-second balance rule. Theoretical analysis and results of simulations and experiments indicate that new DSVPWMx strategies are feasible. DSVPWMx strategies have the same unswitching intervals to reduce the switching loss, and in the meanwhile, the software algorithm of DSVPWMx is very easy due to the basis of SVPWM and the simple addition operation.

Figure 8. Simulation results of DSVPWMx, M=1.15.

(a) DSVPWMP

(b) DSVPWMN

(c) DSVPWMPN1 (a) Simulation results (b) Experimental results Figure 7. Continuous strategy, M=1.15.

(d) DSVPWMPN3

Figure 9. Experimental results of DSVPWMx, M=1.15.

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