Serial Peripheral Interface Bus

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SPI bus: single master and single slave The Serial Peripheral Interface Bus or SPI (pronounced as either ess-pee-eye or spy) bus is a synchronous serial data link standard, named by Motorola, that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses. SPI is often referred to as SSI (Synchronous Serial Interface).

Contents

1 Interface 2 Operation o 2.1 Data transmission 2.1.1 Clock polarity and phase 2.1.2 Mode numbers o 2.2 Independent slave SPI configuration o 2.3 Daisy chain SPI configuration o 2.4 Valid SPI communications o 2.5 Interrupts o 2.6 Example of bit-banging the SPI master protocol 3 Pros and cons of SPI o 3.1 Advantages o 3.2 Disadvantages 4 Applications 5 Standards 6 Development tools o 6.1 Host adapters o 6.2 Protocol analyzers o 6.3 Oscilloscopes o 6.4 Logic analyzers 7 Related terms o 7.1 Intelligent SPI controllers o 7.2 Microwire

7.3 Three-wire serial buses 7.4 Multi I/O SPI 8 See also 9 References 10 External links

o o

Interface
The SPI bus specifies four logic signals:

SCLK: serial clock (output from master); MOSI; SIMO: master output, slave input (output from master); MISO; SOMI: master input, slave output (output from slave); SS: slave select (active low, output from master).

Alternative naming conventions are also widely used:

SCK; CLK: serial clock (output from master) SDI; DI, DIN, SI: serial data in; data in, serial in SDO; DO, DOUT, SO: serial data out; data out, serial out nCS, CS, CSB, CSN, nSS, STE: chip select, slave transmit enable (active low, output from master)

The SDI/SDO (DI/DO, SI/SO) convention requires that SDO on the master be connected to SDI on the slave, and vice-versa. Chip select polarity is rarely active high, although some notations (such as SS or CS instead of nSS or nCS) suggest otherwise. SPI port pin names for particular IC products may differ from those depicted in these illustrations.

Operation
The SPI bus can operate with a single master device and with one or more slave devices. If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some slaves require the falling edge (highlow transition) of the chip select to initiate an action such as the Maxim MAX1242 ADC, which starts conversion on said transition. With multiple slave devices, an independent SS signal is required from the master for each slave device. Most slave devices have tri-state outputs so their MISO signal becomes high impedance (disconnected) when the device is not selected. Devices without tri-state outputs can't share SPI bus segments with other devices; only one such slave could talk to the master, and only its chip select could be activated.

Data transmission

A typical hardware setup using two shift registers to form an inter-chip circular buffer To begin a communication, the bus master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 1100 MHz. The master then transmits the appropriate chip select bit for the desired chip to a logic 0. A logic 0 is transmitted because the chip select line is active low, meaning its off state is a logic 1; on is asserted with a logic 0. If a waiting period is required (such as for analog-to-digital conversion), then the master must wait for at least that period of time before starting to issue clock cycles. During each SPI clock cycle, a full duplex data transmission occurs:

the master sends a bit on the MOSI line; the slave reads it from that same line the slave sends a bit on the MISO line; the master reads it from that same line

Not all transmissions require all four of these operations to be meaningful but they do happen. Transmissions normally involve two shift registers of some given word size, such as eight bits, one in the master and one in the slave; they are connected in a ring. Data is usually shifted out with the most significant bit first, while shifting a new least significant bit into the same register. After that register has been shifted out, the master and slave have exchanged register values. Then each device takes that value and does something with it, such as writing it to memory. If there is more data to exchange, the shift registers are loaded with new data[1] and the process repeats. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops toggling its clock. Normally, it then deselects the slave. Transmissions often consist of 8-bit words, and a master can initiate multiple such transmissions if it wishes/needs. However, other word sizes are also common, such as 16-bit words for touchscreen controllers or audio codecs, like the TSC2101 from Texas Instruments; or 12-bit words for many digital-to-analog or analog-to-digital converters.

Every slave on the bus that hasn't been activated using its chip select line must disregard the input clock and MOSI signals, and must not drive MISO. The master must select only one slave at a time. Clock polarity and phase

A timing diagram showing clock polarity and phase In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Freescale's SPI Block Guide[2] names these two options as CPOL and CPHA respectively, and most vendors have adopted that convention. The timing diagram is shown to the right. The timing is further described below and applies to both the master and the slave device.

At CPOL=0 the base value of the clock is zero o For CPHA=0, data is captured on the clock's rising edge (lowhigh transition) and data is propagated on a falling edge (highlow clock transition). o For CPHA=1, data is captured on the clock's falling edge and data is propagated on a rising edge. At CPOL=1 the base value of the clock is one (inversion of CPOL=0) o For CPHA=0, data is captured on clock's falling edge and data is propagated on a rising edge. o For CPHA=1, data is captured on clock's rising edge and data is propagated on a falling edge.

That is, CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle. For all CPOL and CPHA modes, the initial clock value must be stable before the chip select line goes active.

The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle. This adds more flexibility to the communication channel between the master and slave. Some products use different naming conventions. For example, the TI MSP430 uses the name UCCKPL instead of CPOL, and its UCCKPH is the inverse of CPHA. When connecting two chips together, carefully examine the clock phase initialization values to be sure of using the right settings. Mode numbers The combinations of polarity and phases are often referred to as modes which are commonly numbered according to the following convention, with CPOL as the high order bit and CPHA as the low order bit: Mode CPOL CPHA 0 0 0 1 0 1 2 1 0 3 1 1 Another commonly used notation represents the mode as a (CPOL, CPHA) tuple; e.g., the value '(0, 1)' would indicate CPOL=0 and CPHA=1

Independent slave SPI configuration

Typical SPI bus: master and three independent slaves

In the independent slave configuration, there is an independent chip select line for each slave. This is the way SPI is normally used. Since the MISO pins of the slaves are connected together, they are required to be tri-state pins.

Daisy chain SPI configuration

Daisy-chained SPI bus: master and cooperative slaves Some products with SPI bus are designed to be capable of being connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of what it received during the first group of clock pulses. The whole chain acts as an SPI communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Such a feature only requires a single SS line from the master, rather than a separate SS line for each slave.[3] Applications (discussed later) that require a daisy chain configuration include SGPIO and JTAG.

Valid SPI communications

Some slave devices are designed to ignore any SPI communications in which the number of clock pulses is greater than specified. Others don't care, ignoring extra inputs and continuing to shift the same output bit. It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access the scan chain of a digital IC by issuing a command word of one size (perhaps 32 bits) and then getting a response of a different size (perhaps 153 bits, one for each pin in that scan chain).

Interrupts

SPI devices sometimes use another signal line to send an interrupt signal to a host CPU. Examples include pen-down interrupts from touchscreen sensors, thermal limit alerts from temperature sensors, alarms issued by real time clock chips, SDIO, and headset jack insertions from the sound codec in a cell phone. Interrupts are not covered by the SPI standard; their usage is neither forbidden nor specified by the standard.

Example of bit-banging the SPI master protocol

Below is an example of bit-banging the SPI protocol as an SPI master with CPOL=0, CPHA=0, and eight bits per transfer. The example is written in the C programming language. Because this is CPOL=0 the clock must be pulled low before the chip select is activated. The chip select line must be activated, which normally means being toggled low, for the peripheral before the start of the transfer, and then deactivated afterwards. Most peripherals allow or require several transfers while the select line is low; this routine might be called several times before deselecting the chip.
/* return: 0 is OK, */ unsigned char SPIWriteData(unsigned char byte) { unsigned char bit; /* Negative clock polarity */ SETGPHA(0); /* Data are propagated on a falling edge (high->low clock transition). */ SETGPOL(0); for (bit = 0; bit < 8; bit++) { /* delay between raise of clock */ SPIDELAY(SPISPEED/2); SETCLK(); /* delay between fall of clock */ /* gives the h/w time to setup MISO line */ SPIDELAY(SPISPEED - (SPISPEED/2)); CLRCLK(); /* write MOSI on falling edge of previous clock */ if (byte & 0x80) SETMOSI(); else CLRMOSI(); byte <<= 1; } return byte; }

Pros and cons of SPI

Advantages

Full duplex communication Higher throughput than IC or SMBus Complete protocol flexibility for the bits transferred o Not limited to 8-bit words o Arbitrary choice of message size, content, and purpose Extremely simple hardware interfacing o Typically lower power requirements than IC or SMBus due to less circuitry (including pull up resistors) o No arbitration or associated failure modes o Slaves use the master's clock, and don't need precision oscillators o Slaves don't need a unique address unlike IC or GPIB or SCSI o Transceivers are not needed Uses only four pins on IC packages, and wires in board layouts or connectors, much less than parallel interfaces At most one unique bus signal per device (chip select); all others are shared Signals are unidirectional allowing for easy Galvanic isolation Not limited to any maximum clock speed, enabling potentially high throughput

Disadvantages

Requires more pins on IC packages than IC, even in the three-wire variant No in-band addressing; out-of-band chip select signals are required on shared buses No hardware flow control by the slave (but the master can delay the next clock edge to slow the transfer rate) No hardware slave acknowledgment (the master could be transmitting to nowhere and not know it) Supports only one master device No error-checking protocol is defined Generally prone to noise spikes causing faulty communication Without a formal standard, validating conformance is not possible Only handles short distances compared to RS-232, RS-485, or CAN-bus Many existing variations, making it difficult to find development tools like host adapters that support those variations SPI does not support hot plugging (dynamically adding nodes).

Applications
The board real estate savings compared to a parallel I/O bus are significant, and have earned SPI a solid role in embedded systems. That is true for most system-on-a-chip processors, both with higher end 32-bit processors such as those using ARM, MIPS, or PowerPC and with other microcontrollers such as the AVR, PIC, and MSP430. These chips usually include SPI controllers capable of running in either master or slave mode. In-system programmable AVR controllers (including blank ones) can be programmed using an SPI interface.[4] Chip or FPGA based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as its on-board cousin.

The full-duplex capability makes SPI very simple and efficient for single master/single slave applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as digital audio, digital signal processing, or telecommunications channels, but most off-the-shelf chips stick to half-duplex request/response protocols. SPI is used to talk to a variety of peripherals, such as

Sensors: temperature, pressure, ADC, touchscreens, video game controllers Control devices: audio codecs, digital potentiometers, DAC Camera lenses: Canon EF lens mount Communications: Ethernet, USB, USART, CAN, IEEE 802.15.4, IEEE 802.11, handheld video games Memory: flash and EEPROM Real-time clocks LCD displays, sometimes even for managing image data Any MMC or SD card (including SDIO variant)

For high performance systems, FPGAs sometimes use SPI to interface as a slave to a host, as a master to sensors, or for flash memory used to bootstrap if they are SRAM-based. JTAG is essentially an application stack for a three-wire SPI flavor, using different signal names[citation needed]: TCK not SCK, TDI not MOSI, TDO not MISO. It defines a state machine (driven by a TMS signal instead of a chip select line), protocol messages, a core command set, the ability to daisy-chain devices in a "scan chain", and how vendors define new commands. The devices in a scan chain are initially treated as a single device, and transitions on TMS update their state machines; once the individual devices are identified, commands may be issued that affect only one device in that scan chain. Different vendors use different JTAG connectors. Bit strings used in JTAG are often long and not multiples of 8 bit words; for example, a boundary scan reports signal state on each of several hundred pins. SGPIO is essentially another (incompatible) application stack for SPI designed for particular backplane management activities[citation needed]. SGPIO uses 3-bit messages.

Standards
The SPI bus is a de facto standard. However, the lack of a formal standard is reflected in a wide variety of protocol options. Different word sizes are common. Every device defines its own protocol, including whether or not it supports commands at all. Some devices are transmit-only; others are receive-only. Chip selects are sometimes active-high rather than active-low. Some protocols send the least significant bit first. Some devices even have minor variances from the CPOL/CPHA modes described above. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response. Some devices have two clocks, one to read data, and another to transmit it into the device. Many of the read clocks run from the chip select line.

Some devices require an additional flow control signal from slave to master, indicating when data are ready. This leads to a 5-wire protocol instead of the usual 4. Such a ready or enable signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI masters don't support that signal directly, and instead rely on fixed delays.) Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the JTAG or SGPIO protocols, or any other protocol that requires messages that are not multiples of 8 bits. There are even hardware-level differences. Some chips combine MOSI and MISO into a single data line (SI/SO); this is sometimes called three-wire signaling (in contrast to normal four-wire SPI). Another SPI flavor removes the chip select line, managing protocol state machine entry/exit using other methods; this isn't usually called three-wire though. Anyone needing an external connector for SPI defines their own: UEXT, JTAG connector, Secure Digital card socket, etc. Signal levels depend entirely on the chips involved.

Development tools
When developing or troubleshooting systems using SPI, visibility at the level of hardware signals can be important.

Host adapters
There are a number of USB hardware solutions to provide computers, running Linux, Mac, or Windows, SPI master and/or slave capabilities. Many of them also provide scripting and/or programming capabilities (Visual Basic, C/C++, etc.). An SPI host adapter lets the user play the role of a master on a SPI bus directly from PC. They are used for embedded systems, chips (FPGA/ASIC/SoC) and peripheral testing, programming and debugging. The key parameters of SPI adapters are: the maximum supported frequency for the serial interface, command-to-command latency and the maximum length for SPI commands. It is possible to find SPI adapters on the market today that support up to 100 MHz serial interfaces, with virtually unlimited access length. SPI protocol being a de facto standard, some SPI host adapters also have the ability of supporting other protocols beyond the traditional 4-wires SPI (for example, support of quad-SPI protocol or other custom serial protocol that derive from SPI[5]). Examples of SPI adapters (manufacturers in alphabetical order):

Manufacturer SPI host adapter Host bus Bus protocol support Max frequency Byte Paradigm SPI Storm USB SPI, dual/quad, custom 100 MHz National Instruments USB-8541 USB IC, SPI 12 MHz Total Phase Cheetah USB SPI 40 MHz Microchip MCP2210 Kit USB SPI 12 MHz

Protocol analyzers
SPI Protocol Analyzers are tools which sample a SPI bus and decode the electrical signals to provide a higher-level view of the data being transmitted on a specific bus.

Oscilloscopes
Every major oscilloscope vendor offers oscilloscope-based triggering and protocol decoding for SPI. Most support 2-, 3-, and 4-wire SPI. The triggering and decoding capability is typically offered as an optional extra. SPI signals can be accessed via analog oscilloscope channels or with digital MSO channels.[6]

Logic analyzers
When developing and/or troubleshooting the SPI bus, examination of hardware signals can be very important. Logic analyzers are tools which collect, analyze, decode, store signals so people can view the high-speed waveforms at their leisure. Logic analyzers display time-stamps of each signal level change, which can help find protocol problems. Most logic analyzers have the capability to decode bus signals into high-level protocol data and show ASCII data.

Related terms
Intelligent SPI controllers
The queued serial peripheral interface (QSPI) is one type of SPI controller, not another bus type. It uses a data queue with programmable queue pointers allowing some data transfers without CPU intervention.[7] It also has a wrap-around mode allowing continuous transfers to and from the queue with no CPU intervention. Consequently, the peripherals appear to the CPU as memory-mapped parallel devices. This feature is useful in applications such as control of an A/D converter. Other programmable features in QSPI are chip selects and transfer length/delay. SPI controllers from different vendors support different feature sets; such DMA queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself, such as used by multichannel buffered serial port (MCBSP).[8] Most SPI master controllers integrate support for up to four chip selects,[9] although some require chip selects to be managed separately through GPIO lines.

Microwire

Microwire is essentially a predecessor of SPI. It's a strict subset: half duplex, and using SPI mode 0. (Microwire-Plus supports other SPI modes.) Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2 MHz vs. 20 MHz. Some Microwire chips also support a three-wire mode (see below), which fits neatly with the restriction to half duplex.

Three-wire serial buses

As mentioned above, one variant of SPI uses single bidirectional data line (slave out/slave in, called SISO) instead of two unidirectional ones (MOSI and MISO). Clearly, this variant is restricted to a half duplex mode. It tends to be used for lower performance parts, such as small EEPROMs used only during system startup and certain sensors, and Microwire. As of this writing, few SPI master controllers support this mode; although it can often be easily bit-banged in software. When someone says a part supports SPI or Microwire, you can normally assume that means the four-wire version. However, when someone talks about a part supporting a three-wire serial bus you should always find out what it means: standard four-wire SPI, without the chip select pin from that count, since most buses use chip selects but only three wires carry "real" signals; (More, sometimes with an unshared SPI bus segment the device's chip select will be hard-wired as "always selected".) "real" three-wire SPI; or even a RS-232 cable with RXD, TXD, and shield/ground, or an application-specific signaling scheme.

Multi I/O SPI

As opposed to three-wire serial buses, multi I/O SPI uses multiple parallel data lines (e.g., IO0 to IO3) to increase throughput. Dual I/O SPI using two data lines has comparable throughput to fast single I/O (MISO/MOSI). Quad I/O SPI using four data lines has approximately double the throughput.[10] Multi I/O SPI devices tend to be half duplex similar to three-wire devices to avoid adding too many pins. These serial memory devices combine the advantage of more speed with reduced pin count as compared to parallel memory.

IC ("eye-squared cee"; Inter-Integrated Circuit; generically referred to as "two-wire interface") is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. Since the mid 1990s, several competitors (e.g., Siemens AG (later Infineon Technologies AG, now Intel mobile communications), NEC, Texas Instruments, STMicroelectronics (formerly SGS-Thomson), Motorola (later Freescale), Intersil, etc.) brought IC products on the market, which are fully compatible with the NXP (formerly Philips's semiconductor division) ICsystem. As of October 10, 2006, no licensing fees are required to implement the IC protocol. However, fees are still required to obtain IC slave addresses allocated by NXP.[1] SMBus, defined by Intel in 1995, is a subset of IC that defines the protocols more strictly. One purpose of SMBus is to promote robustness and interoperability. Accordingly, modern IC systems incorporate policies and rules from SMBus, sometimes supporting both IC and SMBus with minimal re-configuration required.

Contents

1 Revisions 2 Design o 2.1 Reference design o 2.2 Message protocols o 2.3 Messaging example: 24c32 EEPROM o 2.4 Physical layer 2.4.1 Clock stretching using SCL 2.4.2 Arbitration using SDA 2.4.2.1 Arbitration in SMBus o 2.5 Buffering and multiplexing o 2.6 Timing diagram o 2.7 Example of bit-banging the IC Master protocol 3 Applications 4 Operating system support 5 Development tools o 5.1 IC host adapters o 5.2 IC protocol analyzers o 5.3 Logic analyzers 6 Limitations 7 Derivative technologies 8 See also 9 References 10 Further reading 11 External links o 11.1 Official specification o 11.2 Other sources

Revisions

In 1982, the original 100-kHz IC system was created as a simple internal bus system for building control electronics with various Philips chips. In 1992, Version 1.0 (the first standardized version) added 400-kHz Fast-mode (Fm) and a 10-bit addressing mode to increase capacity to 1008 nodes. In 1998, Version 2.0 added 3.4-MHz High-speed mode (Hs) with power-saving requirements for electric voltage and current. In 2000, Version 2.1[2] introduced a minor cleanup of version 2.0. In 2007, Version 3.0[3] added 1-MHz Fast-mode plus (Fm+), and a device ID mechanism. In 2012, Version 4.0[4] added 5-MHz Ultra Fast-mode (UFm) for new USDA and USCL lines using push-pull logic without pull-up resistors, and added assigned manufacturer ID table. This is the most recent standard.

Design

A sample schematic with one master (a microcontroller), three slave nodes (an ADC, a DAC, and a microcontroller), and pull-up resistors Rp

IC uses only two bidirectional open-drain lines, Serial Data Line (SDA) and Serial Clock (SCL), pulled up with resistors. Typical voltages used are +5 V or +3.3 V although systems with other voltages are permitted. The IC reference design has a 7-bit or a 10-bit (depending on the device used) address space.[5] Common IC bus speeds are the 100 kbit/s standard mode and the 10 kbit/s low-speed mode, but arbitrarily low clock frequencies are also allowed. Recent revisions of IC can host more nodes and run at faster speeds (400 kbit/s Fast mode, 1 Mbit/s Fast mode plus or Fm+, and 3.4 Mbit/s High Speed mode). These speeds are more widely used on embedded systems than on PCs. There are also other features, such as 16-bit addressing.

Note that the bit rates quoted are for the transactions between master and slave without clock stretching or other hardware overhead. Protocol overheads include a slave address and perhaps a register address within the slave device as well as per-byte ACK/NACK bits. So the actual transfer rate of user data is lower than those peak bit rates alone would imply. For example, if each interaction with a slave inefficiently allows only 1 byte of data to be transferred, the data rate will be less than half the peak bit rate. The maximum number of nodes is limited by the address space, and also by the total bus capacitance of 400 pF, which restricts practical communication distances to a few meters.

Reference design
The reference design, as mentioned above, is a bus with a clock (SCL) and data (SDA) lines with 7-bit addressing. The bus has two roles for nodes: master and slave:

Master node node that issues the clock and addresses slaves Slave node node that receives the clock line and address.

The bus is a multi-master bus which means any number of master nodes can be present. Additionally, master and slave roles may be changed between messages (after a STOP is sent). There are four potential modes of operation for a given bus device, although most devices only use a single role and its two modes:

master transmit master node is sending data to a slave master receive master node is receiving data from a slave slave transmit slave node is sending data to the master slave receive slave node is receiving data from the master

The master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave. If the slave exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that address. The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complementary mode (receive or transmit, respectively). The address and the data bytes are sent most significant bit first. The start bit is indicated by a high-to-low transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of SDA with SCL high. If the master wishes to write to the slave then it repeatedly sends a byte with the slave sending an ACK bit. (In this situation, the master is in master transmit mode and the slave is in slave receive mode.)

If the master wishes to read from the slave then it repeatedly receives a byte from the slave, the master sending an ACK bit after every byte but the last one. (In this situation, the master is in master receive mode and the slave is in slave transmit mode.) The master then ends transmission with a stop bit, or it may send another START bit if it wishes to retain control of the bus for another transfer (a "combined message").

Message protocols
IC defines three basic types of messages, each of which begins with a START and ends with a STOP:

Single message where a master writes data to a slave; Single message where a master reads data from a slave; Combined messages, where a master issues at least two reads and/or writes to one or more slaves.

In a combined message, each read or write begins with a START and the slave address. After the first START, these are also called repeated START bits; repeated START bits are not preceded by STOP bits, which is how slaves know the next transfer is part of the same message. Any given slave will only respond to particular messages, as defined by its product documentation. Pure IC systems support arbitrary message structures. SMBus is restricted to nine of those structures, such as read word N and write word N, involving a single slave. PMBus extends SMBus with a Group protocol, allowing multiple such SMBus transactions to be sent in one combined message. The terminating STOP indicates when those grouped actions should take effect. For example, one PMBus operation might reconfigure three power supplies (using three different I2C slave addresses), and their new configurations would take effect at the same time: when they receive that STOP. With only a few exceptions, neither IC nor SMBus define message semantics, such as the meaning of data bytes in messages. Message semantics are otherwise product-specific. Those exceptions include messages addressed to the IC general call address (0x00) or to the SMBus Alert Response Address; and messages involved in the SMBus Address Resolution Protocol (ARP) for dynamic address allocation and management. In practice, most slaves adopt request/response control models, where one or more bytes following a write command are treated as a command or address. Those bytes determine how subsequent written bytes are treated and/or how the slave responds on subsequent reads. Most SMBus operations involve single byte commands.

Messaging example: 24c32 EEPROM

One specific example is the 24c32 type EEPROM, which uses two request bytes that are called Address High and Address Low. (Accordingly, these EEPROMs aren't usable by pure SMBus hosts, which only support single byte commands or addresses.) These bytes are used to address bytes within the 32 kbit (4 kB) supported by that EEPROM; the same two byte addressing is also used by larger EEPROMs, such as 24c512 ones storing 512 kbits (64 kB). Writing and reading data to these EEPROMs uses a simple protocol: the address is written, and then data is transferred until the end of the message. (That data transfer part of the protocol also makes trouble for SMBus, since the data bytes are not preceded by a count and more than 32 bytes can be transferred at once. IC EEPROMs smaller than 32 kbits, such as 2 kbit 24c02 ones, are often used on SMBus with inefficient single byte data transfers.) To write to the EEPROM, a single message is used. After the START, the master sends the chip's bus address with the direction bit clear (write), then sends the two byte address of data within the EEPROM and then sends data bytes to be written starting at that address, followed by a STOP. When writing multiple bytes, all the bytes must be in the same 32 byte page. While it's busy saving those bytes to memory, the EEPROM won't respond to further IC requests. (That's another incompatibility with SMBus: SMBus devices must always respond to their bus addresses.) To read starting at a particular address in the EEPROM, a combined message is used. After a START, the master first writes that chip's bus address with the direction bit clear (write) and then the two bytes of EEPROM data address. It then sends a (repeated) START and the EEPROM's bus address with the direction bit set (read). The EEPROM will then respond with the data bytes beginning at the specified EEPROM data addressa combined message, first a write then a read. The master issues a STOP after the first data byte it NACKs rather than ACKs (when it's read all it wants). The EEPROM increments the address after each data byte transferred; multibyte reads can retrieve the entire contents of the EEPROM using one combined message.

Physical layer
At the physical layer, both SCL & SDA lines are of open-drain design, thus, pull-up resistors are needed. Pulling the line to ground is considered a logical zero while letting the line float is a logical one. This is used as a channel access method. High speed systems (and some others) also add a current source pull up, at least on SCL; this supports faster rise times and higher bus capacitance. An important consequence of this is that multiple nodes may be driving the lines simultaneously. If any node is driving the line low, it will be low. Nodes that are trying to transmit a logical one (i.e. letting the line float high) can see this, and thereby know that another node is active at the same time. When used on SCL, this is called "clock stretching" and gives slaves a flow control mechanism. When used on SDA, this is called arbitration and ensures there is only one transmitter at a time. When idle, both lines are high. To start a transaction, SDA is pulled low while SCL remains high. Releasing SDA to float high again would be a stop marker, signalling the end of a bus

transaction. Although legal, this is typically pointless immediately after a start, so the next step is to pull SCL low. Except for the start and stop signals, the SDA line only changes while the clock is low; transmitting a data bit consists of pulsing the clock line high while holding the data line steady at the desired level. While SCL is low, the transmitter (initially the master) sets SDA to the desired value and (after a small delay to let the value propagate) lets SCL float high. The master then waits for SCL to actually go high; this will be delayed by the finite rise-time of the SCL signal (the RC time constant of the pull-up resistor and the parasitic capacitance of the bus), and may be additionally delayed by a slave's clock stretching. Once SCL is high, the master waits a minimum time (4 s for standard speed IC) to ensure the receiver has seen the bit, then pulls it low again. This completes transmission of one bit. After every 8 data bits in one direction, an "acknowledge" bit is transmitted in the other. The transmitter and receiver switch roles for one bit and the erstwhile receiver transmits a single 0 bit (ACK) back. If the transmitter sees a 1 bit (NACK) instead, it learns that:

(If master transmitting to slave) The slave is unable to accept the data. No such slave, command not understood, or unable to accept any more data. (If slave transmitting to master) The master wishes the transfer to stop after this data byte.

After the acknowledge bit, the master may do one of three things:
1. Prepare to transfer another byte of data: the transmitter set SDA, and the master pulses SCL high.. 2. Send a "Stop": Set SDA low, let SCL go high, then let SDA go high. This releases the IC bus. 3. Send a "Repeated start": Set SDA high, let SCL go high, and pull SDA low again. This starts a new IC bus transaction without releasing the bus.

Clock stretching using SCL One of the more significant features of the IC protocol is clock stretching. An addressed slave device may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The master that is communicating with the slave may not finish the transmission of the current bit, but must wait until the clock line actually goes high. If the slave is clock stretching, the clock line will still be low (because the connections are opendrain). The same is true if a second, slower, master tries to drive the clock at the same time. (If there is more than one master, all but one of them will normally lose arbitration.) The master must wait until it observes the clock line going high, and an additional minimum time (4 s for standard 100 kbit/s IC) before pulling the clock low again. Although the master may also hold the SCL line low for as long as it desires, the term "clock stretching" is normally used only when slaves do it. Although in theory any clock pulse may be

stretched, generally it is the intervals before or after the acknowledgment bit which are used. For example, if the slave is a microcontroller, its IC interface will stretch the clock after each byte, until the software decides whether to send a positive acknowledgment or a NACK. Clock stretching is the only time in I2C where the slave drives SCL. Many slaves do not need to clock stretch and thus treat SCL as strictly a input with no circuitry to drive it. Some masters, such as those found inside custom ASICs may not support clock stretching; often these devices will be labeled as a "two-wire interface" and not IC. To ensure a minimum bus throughput, SMBus places limits on how far clocks may be stretched. Hosts and slaves adhering to those limits can't block access to the bus for more than a short time, which is not a guarantee made by pure IC systems. Arbitration using SDA Every master monitors the bus for start and stop bits, and does not start a message while another master is keeping the bus busy. However, two masters may start transmission at about the same time; in this case, arbitration occurs. Slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. In contrast to protocols (such as Ethernet) that use random back-off delays before issuing a retry, IC has a deterministic arbitration policy. Each transmitter checks the level of the data line (SDA) and compares it with the levels it expects; if they don't match, that transmitter has lost arbitration, and drops out of this protocol interaction. If one transmitter sets SDA to 1 (not driving a signal) and a second transmitter sets it to 0 (pull to ground), the result is that the line is low. The first transmitter then observes that the level of the line is different than expected, and concludes that another node is transmitting. The first node to notice such a difference is the one that loses arbitration: it stops driving SDA. If it's a master, it also stops driving SCL and waits for a STOP; then it may try to reissue its entire message. In the meantime, the other node has not noticed any difference between the expected and actual levels on SDA, and therefore continues transmission. It can do so without problems because so far the signal has been exactly as it expected; no other transmitter has disturbed its message. If the two masters are sending a message to two different slaves, the one sending the lower slave address always "wins" arbitration in the address stage. Since the two masters may send messages to the same slave addressand addresses sometimes refer to multiple slavesarbitration must continue into the data stages. Arbitration occurs very rarely, but is necessary for proper multi-master support. As with clockstretching, not all devices support arbitration. Those that do generally label themselves as supporting "multi-master" communication. In the extremely rare case that two masters simultaneously send identical messages. then both will regard the communication as successful, but the slave will only see one message. Slaves that can be accessed by multiple masters must have commands that are idempotent for this reason.

Arbitration in SMBus

While IC only arbitrates between masters, SMBus uses arbitration in three additional contexts, where multiple slaves respond to the master, and one gets its message through.
1. Although conceptually a single-master bus, a slave device that supports the "host notify protocol" acts as a master to perform the notification. It seizes the bus and writes a 3-byte message to the reserved "SMBus Host" address (0x08), passing its address and two bytes of data. When two slaves try to notify the host at the same time, one of them will lose arbitration and need to retry. 2. An alternative slave notification system uses the separate SMBALERT# signal to request attention. In this case, the host performs a 1-byte read from the reserved "SMBus Alert Response Address" (0x0c), which is a kind of broadcast address. All alerting slaves respond with a data bytes containing their own address. When the slave successfully transmits its own address (winning arbitration against others) it stops raising that interrupt. In both this and the preceding case, arbitration ensures that one slave's message will be received, and the others will know they must retry. 3. SMBus also supports an "address resolution protocol", wherein devices return a 16-byte "universal device ID" (UDID). Multiple devices may respond; the one with the least UDID will win arbitration and be recognized.

Buffering and multiplexing

When there are many IC devices in a system, there can be a need to include bus buffers or multiplexers to split large bus segments into smaller ones. This can be necessary to keep the capacitance of a bus segment below the allowable value or to allow multiple devices with the same address to be separated by a multiplexer. Many types of multiplexers and buffers exist and all must take into account the fact that IC lines are specified to be bidirectional. Multiplexers can be implemented with analog switches which can tie one segment to another. Analog switches maintain the bidirectional nature of the lines but do not isolate the capacitance of one segment from another or provide buffering capability. Buffers can be used to isolate capacitance on one segment from another and/or allow IC to be sent over longer cables or traces. Buffers for bi-directional lines such as IC must use one of several schemes for preventing latch-up. IC is open-drain so buffers must drive a low on one side when they see a low on the other. One method for preventing latch-up is for a buffer to have carefully selected input and output levels such that the output level of its driver is higher than its input threshold, preventing it from triggering itself. For example, a buffer may have an input threshold of 0.4 V for detecting a low, but an output low level of 0.5 V. This method requires that all other devices on the bus have thresholds which are compatible and often means that multiple buffers implementing this scheme cannot be put in series with one another. Alternatively, other types of buffers exist that implement current amplifiers, or keep track of the state (i.e. which side drove the bus low) to prevent latch-up. The state method typically means that an unintended pulse is created during a hand-off when one side is driving the bus low, then the other drives it low, then the first side releases (this is common during an IC acknowledgement).

Timing diagram

Data transfer is initiated with the START bit (S) when SDA is pulled low while SCL stays high. Then, SDA sets the transferred bit while SCL is low (blue) and the data is sampled (received) when SCL rises (green). When the transfer is complete, a STOP bit (P) is sent by releasing the data line to allow it to be pulled up while SCL is constantly high. In order to avoid false marker detection, SDA is launched on the negative edge and captured on the positive edge of SCL.

Applications
IC is appropriate for peripherals where simplicity and low manufacturing cost are more important than speed. Common applications of the IC bus are:

Reading configuration data from SPD EEPROMs on SDRAM, DDR SDRAM, DDR2 SDRAM memory sticks (DIMM) and other stacked PC boards Supporting systems management for PCI cards, through an SMBus 2.0 connection. Accessing NVRAM chips that keep user settings. Accessing low speed DACs and ADCs. Changing contrast, hue, and color balance settings in monitors (Display Data Channel). Changing sound volume in intelligent speakers. Controlling OLED/LCD displays, like in a cellphone. Reading hardware monitors and diagnostic sensors, like a CPU thermostat and fan speed. Reading real-time clocks. Turning on and turning off the power supply of system components.

A particular strength of IC is that a microcontroller can control a network of device chips with just two general purpose I/O pins and software. Many other bus technologies used in similar applications, such as Serial Peripheral Interface Bus, require more pins and signals to connect devices.