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Logic Synthesis
Use of Logic Synthesis has become common industrial practice.

The advantages are many:


Technology portability Design Documentation

Logic Synthesis with VHDL Combinational Logic

Constraint Driven Synthesis Two major languages are Verilog and VHDL. This tutorial will con-

ver logic synthesis via VHDL.


We will split the tutorials into three parts: Introduction to VHDL via combinational synthesis examples Sequential synthesis examples (registers, finite state

machines)

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System examples (combined datapath and control)

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Combinational Synthesis with VHDL

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Tutorial Caveats
Tutorial examples have been made as simple and portable as pos-

VHDL Synthesis Subset


The VHDL language has a reputation for being very complex - that

sible.
Will stay away from topics such as parameterization which

reputation is well deserved!


Fortunately, the subset of VHDL which can be used for synthesis is

SMALL - very easy to learn.


Primary VHDL constructs we will use for synthesis: signal assignment

may involve vendordependent features.


Will also stay away from coding styles which involve type

conversion as this tends to add extra complications.


Examples have been tested with the Synopsys and Viewlogic syn-

nextstate <= HIGHWAY_GREEN


comparisons

thesis tools; most of the synthesized schematics shown in the slides are from the Viewlogic synthesis tool. Some of the more complex examples are only compatible with the Synopsys environment
In these tutorials, the suggested styles for writing synthesizable

= (equal), /= (not equal), > (greater than), < (less than) <= ( less than or equal), >= (greater than or equal)
logical operators

(and, xor, or, nand, nor, xnor, not )


if statement

VHDL models come from my own experience in teaching an ASIC design course for Senior/Graduate EE students.
Coverage of VHDL packages will be light; the block structural

if ( presentstate = CHECK_CAR ) then .... end if | elsif ....


for statement (used for looping in creating arrays of

statements and VHDL configurations are skipped. Generics are not mentioned until late in the tutorial since support from a synthesis point of view is vendor dependent.
This tutorial is no substitute for a good, detailed VHDL textbook or

elements)
Other constructs are when else, case , wait . Also := for

variable assignment.

the language reference manual. Get one or both!!!


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General Comments on VHDL Syntax


Most syntax details will be introduced on an asneeded basis. The full syntax of a statement type including all of its various

Combinational Logic Examples


We will go through some combinational examples to introduce you

options will often NOT be presented; instead, these will be introduced via examples as the tutorial progresses.
There are many language details which will be glossed over or

to the synthesizable subset of VHDL. Usually, we will demonstrate multiple methods of implementing the same design.
Examples are: 2 to 1 Mux 8-level priority circuit 3 to 8 Decoder Synthesis boundary conditions Ripplecarry adder

simply skipped for the sake of brevity.


Generalities: VHDL is not case sensitive. The semicolon is used to indicate termination of a statement. Two dashes () are used to indicate the start of a comment. Identifiers must begin with a letter, subsequent characters

must be alphanumeric or _ (underscore).


VHDL is a strongly typed language.

There is very little automatic type conversion; most operations have to operate on common types. Operator overloading is supported in which a function or procedure can be defined differently for different argument lists.

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CombSyn5

Combinational Synthesis with VHDL

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CombSyn6

Combinational Synthesis with VHDL

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Model Template
entity model_name is port ( list of inputs and outputs ); end model_name;

2to1 MUX Using when else

library IEEE; use IEEE.std_logic_1164.all; vhdl model for 2 to 1 mux, 8bits wide entity mux2to1 is port ( signal s: in std_logic; signal zero,one: in std_logic_vector(7 downto 0); signal y: out std_logic_vector(7 downto 0) ); end mux2to1; architecture behavior of mux2to1 is begin
mux2to1

architecture architecture_name of model_name is begin ... VHDL concurrent statements .... end architecture_name ;

y <= one when (s = 1) else zero; end behavior;

8 zero 8 one s y 8

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CombSyn7

Combinational Synthesis with VHDL

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CombSyn8

Combinational Synthesis with VHDL

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Standard Logic 1164


library IEEE; use IEEE.std_logic_1164.all;
The LIBRARY statement is used to reference a group of previous-

2/1 MUX Entity Declaration


entity mux2to1 is port ( signal s: in std_logic; signal zero,one: in std_logic_vector(7 downto 0); signal y: out std_logic_vector(7 downto 0) ); end mux2to1;
The entity declaration defines the external interface for the model. The port list defines the external signals. The signal definition con-

ly defined VHDL design units (other entities or groups procedures/functions known as packages.
The USE statement specifies what entities or packages to use out

of this library; in this case USE IEEE.std_logic_1164.all imports all procedures/functions in the std_logic_1164 package.
The std_logic_1164 package defines a multivalued logic system

sists of the signal name, mode, and type.


For synthesis purposes (and for this tutorial), the mode can be

which will be used as the data types for the signals defined in our examples.
The VHDL language definition had a builtin bit type which

either in, out or inout.


In this tutorial, the signal types will be either std_logic (single bit) or

only supported two values, 1 and 0 which was insufficient for modeling and synthesis applications.
The 1164 standard defines a 9valued logic system; only 4 of

std_logic_vector (busses).
The array specification on the std_logic_vector type defines the

these have meaning for synthesis: 1, 0, Z ( high impedance), (dont care).


The 1164 single bit type std_logic and vector type std_logic_vec-

tor (for busses) will be used for all signal types in the tutorial examples.
Bob Reese 5/95 CombSyn9 Combinational Synthesis with VHDL

width of signal: std_logic_vector (7 downto 0) (descending range) std_logic_vector (0 to 7) (ascending range) Both of these are 8bit wide signals. The descending/ascending range declaration will affect assignment statements such as: y <= 11110000; For descending rage, y(7) is 1; for ascending range y(0) is 1.
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2/1 MUX Architecture Declaration


architecture behavior of mux2to1 is begin y <= one when (s = 1) else zero; end behavior;
The architecture block specifies the model functionality. The

MX2

MX2

MX2

MX2

MX2

MX2

MX2

MX2

architecture name is userdefined. Multiple architectures can be defined for the same entity. VHDL configurations can be used to specify which architecture to use for a particular entity.

Y3

Y4

Y6

Y5

Y0

Y7

Y1

Y
ONE1 ZERO2 ONE2

Y2

This tutorial will only use one architecture per entity and it will
ONE3 ONE4 ONE6 ONE5 ONE0 ZERO3 ZERO4 ZERO6 ZERO5 ZERO0 ZERO7 ONE7 ZERO1

always be called behavior .


The when ... else statement is a conditional signal assignment

statement. When ... else statements can be chained such as: signal_name <= value1 when condition1 else value2 when condition2 else, ...... value N when conditionN else default_value;
The when ... else statement is a particular type of statement

known as a concurrent statement as opposed to a sequential statement. The differences between concurrent and sequential statements will be discussed in more detail later.
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2/1 MUX Architecture Using Booleans


architecture behavior of mux2to1 is signal temp: std_logic_vector(7 downto 0); begin temp <= (s, s, s, s, others => s); y <= (temp and one) or (not temp and zero); end behavior;
Boolean operators are used in an assignment statement to gener-

2/1 MUX Architecture Using a Process


architecture behavior of mux2to1_8 is begin comb: process (s, zero, one) begin y <= zero; if (s = 1) then y <= one; end if; end process comb; end behavior;
This architecture uses a process block to describe the mux opera-

ate the mux operation.


The s signal cannot be used in a boolean operation with the one or

zero signals because of type mismatch (s is a std_logic type, one/ zero are std_logic_vector types)
An internal signal of type std_logic_vector called temp is

tion.
The process block itself is considered a single concurrent

statement.
Only sequential VHDL statements are allowed within a

declared. Note that there is no mode declaration for internal signals. The temp signal will be used in the boolean operation against the zero/one signals.
Every bit of temp is to be set equal to the s signal value. An array

process block.
Signal assignments are assumed to occur sequentially so that

assignment will be used; this can take several forms: temp <= (others => s); others keyword gives default value temp <= (s, s, s, s, s, s, s, s) ; positional assignment, 7 downto 0 temp <= (4=>s, 7=>s, 2=>s, 5=>s, 3=>s, 1=>s, 6=>s, 0=>s) ; named assignment or combinations of the above.
Bob Reese 5/95 CombSyn13 Combinational Synthesis with VHDL

an assignment can supercede a previous assignment to the same signal.


if ... else, case, for ... loop are sequential statements. The list of signals after the process block is called the sensitivity

list; an event on any of these signals will cause the process block to be evaluated during model simulation.
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VEC2

VEC0

VEC1

8level Priority Encoder


vhdl model for 8 level priority circuit IO Interface Declaration entity priority is port ( signal y1, y2, y3, y4, y5, y6, y7: in std_logic; signal vec: out std_logic_vector(2 downto 0) ); end priority; Architecture body architecture behavior of priority is begin process (y1,y2,y3,y4,y5,y6,y7) begin if (y7 = 1) then vec <= 111; elsif (y6 = 1) then vec <= 110; elsif (y5 = 1) then vec <= 101; elsif (y4 = 1) then vec <= 100; elsif (y3 = 1) then vec <= 011; elsif (y2 = 1) then vec <= 010; elsif (y1 = 1) then vec <= 001; else vec <= B000; end if; end process; end behavior;
F

OF

priority

OR4

AO1A

SHEET WIR:priority SCH:priority Jan 6 A B C 94 D 4 13:36 E

A B C

Uses elsif construct for logic


Y6 Y4 Y5 Y7 Y2 Y1 1 2 3 Y3

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CombSyn15

Combinational Synthesis with VHDL

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CombSyn16

AO1A

Combinational Synthesis with VHDL

NAND2B

y1 y2 y3 y4 y5 y6 y7

AO1A

vec

priority

AO2

NOR2

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Priority Encoder again.....


In a process, the ordering of sequential statements which affect a

3 to 8 Decoder Example
entity dec3to8 is port ( signal sel: in std_logic_vector(2 downto 0); selector signal en: in std_logic; enable signal y: out std_logic_vector(7 downto 0) outputs are low true ); end dec3to8; architecture behavior of dec3to8 is begin process (sel,en) begin case statement used for implementation y <= 11111111; if (en = 1) then case sel is when 000 => y(0) <= 0; when 001 => y(1) <= 0; when 010 => y(2) <= 0; when 011 => y(3) <= 0; when 100 => y(4) <= 0; when 101 => y(5) <= 0; when 110 => y(6) <= 0; when 111 => y(7) <= 0; end case; end if; end process; end behavior;

common output define the priority of those assignments.


By using normal if statements and reversing the order of the

assignments we achieve the same results as with the chained elsif statements.
Architecture body architecture behavior of priority is begin process (y1,y2,y3,y4,y5,y6,y7) begin vec <= 000; if (y1 = 1) then vec <= 001; end if; if (y2 = 1) then vec <= 010; end if; if (y3 = 1) then vec <= 011; end if; if (y4 = 1) then vec <= 100; end if; if (y5 = 1) then vec <= 101; end if; if (y6 = 1) then vec <= 110; end if; if (y7 = 1) then vec <= 111; end if; end process; end behavior;

Since y7 is tested last it will have highest priority.

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CombSyn17

Combinational Synthesis with VHDL

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CombSyn18

Combinational Synthesis with VHDL

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A B
1 SEL2

A Common Error
Y
NAND3B

Y5 1

When using processes, a common error is to forget to assign an


A B C Y
NAND3B

Y3

output a default value. ALL outputs should have DEFAULT values!!!!


2

EN 2 SEL0

A Y B
OR2A

A B Y
NAND3B

If there is a logical path in the model such that an output is not

Y4

A Y B
SEL1 3
OR2B

C A B
OR3B

Y6 3

assigned any value then the synthesizer will assume that the output must retain its current value and a latch will be generated.
Example: In dec3to8.vhd do not assign y the default value of

C A B
OR3

Y1

B11111111. If en is 0, then y will not be assigned a value! process (sel,en) begin y <= 11111111; if (en = 1) then .......... Comment out the default assignment to y.

A
4

B C A B

Y
NAND3B

4 Y2

Y
OR3

Y0

C
5 5

A B
OR3B

In the new synthesized logic, all y outputs are latched!

Y7

dec3to8
6 WIR:dec3to8 SCH:dec3to8 6 A Jan 94 B 13:48 C SHEET 1 OF D 1 6

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CombSyn19

Combinational Synthesis with VHDL

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CombSyn20

Combinational Synthesis with VHDL

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Alternative 3to8 Decoder


vhdl model for the 3 to 8 decoder uses conditional signal assignments which are concurrent statements entity dec3to8_alt is port ( signal sel: in std_logic_vector(2 downto 0); selector signal en: in std_logic; enable
DL1

Y6

Y5

Y4

Y7

Y0

Y1

Y2

DL1

DL1

DL1

DL1

DL1

DL1

DL1

Y3

signal y: out std_logic_vector(7 downto 0) outputs are low true ); end dec3to8_alt; Conditional signal architecture behavior of dec3to8_alt is begin
C

AND3A

AND3B

AND3B

AND3B

AND3B

AND3A

NOR3

NOR3

assignment used for each output bit.

y(0) <= 0 when (en = 1 and sel = 000) else 1; y(1) <= 0 when (en = 1 and sel = 001) else 1;
Y Y

y(2) <= 0 when (en = 1 and sel = 010) else 1; y(3) <= 0 when (en = 1 and sel = 011) else 1; y(4) <= 0 when (en = 1 and sel = 100) else 1; y(5) <= 0 when (en = 1 and sel = 101) else 1;
B
SEL0

OR2B

SEL2

OR2A

SEL1

GND

EN

y(6) <= 0 when (en = 1 and sel = 110) else 1; y(7) <= 0 when (en = 1 and sel = 111) else 1; end behavior;

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CombSyn21

Combinational Synthesis with VHDL

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CombSyn22

Combinational Synthesis with VHDL

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Generic Decoder
Shown below is an architecture block for a generic decoder:
....

Generic Decoder (cont.)


for i in yrange loop if ( en = 1 and bvtoi(To_Bitvector(sel)) = i ) then y(i) <= 0 ; end if ;
In order to compare loop variable i with the value of sel, a type con-

architecture behavior of generic_decoder is begin process (sel, en) begin y <= (others => 1) ; for i in yrange loop if ( en = 1 and bvtoi(To_Bitvector(sel)) = i ) then y(i) <= 0 ; end if ; end loop; end process; end behavior;
This architecture block can be used for any binary decoder ( 2 to 4,

version must be done on sel to convert from std_logic_vector to integer.


The Standard Logic 1164 package defines a conversion from

std_logic_vector to bit_vector (bit_vector is a primitive VHDL type).


Unfortunately, the VHDL language standard does not define type

3 to 8, 4 to 16, etc).
The for ... loop construct is used to repeat a sequence of state-

conversions between bit_vector and integer; these conversion functions are vendor dependent.
bvtoi is the Synopsys bit_vector to integer conversion

ments.
The yrange is the range of values for loop variable i. The

range attribute of the signal y is defined as the array range of the signal. In this case, i will vary from 7 to 0 if the array range of y was defined as 7 downto 0.
Other attributes useful for synthesis are: LEFT, RIGHT (left,

function; vlb2int is the Viewlogic equivalent; the Cypress WARP equivalent is bv2i.

right array indices); HIGH, LOW (max, min array indices); EVENT (boolean which is true if event occurred on signal).
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Synthesis Boundary Conditions


F

OF

boundtest

What happens when:


Z_HIGH

13:55 6 Jan 94

Two outputs are reduced to the same logic equation?


E

SHEET WIR:boundtest SCH:boundtest A B C D E

An output is is reduced to 0, 1 or to a primary input? synthesis boundary conditions.. entity boundtest is port ( signal a,b,c: in std_logic; signal w, x, y, z_low, z_high: out std_logic ); end boundtest; architecture behavior of boundtest is begin x and y reduce to the same logic equation the w output should be just a wire from c... the z_low output will be 0, the z_high will be 1 x <= a or b; y <= a or ( (b and not c) or (b and c)); w <= (c and b) or (c and not b); z_low <= b and not b; z_high <= b or not b; end behavior;
1

Z_LOW

NAND2B

NAND2B

INVA

INVA

INVA

INVA

GND

VDD

INVA

INVA

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CombSyn25

Combinational Synthesis with VHDL

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CombSyn26

Combinational Synthesis with VHDL

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SUM1

SUM2

SUM0

COUT

2 SUM3

adder4_alt

Ripple Carry Adder


F

SHEET WIR:adder4_alt SCH:adder4_alt 6 A B C D E

AO1

OF

XOR

XOR

XOR

XOR

OA1

Library IEEE; use IEEE.std_logic_1164.all;


XOR XOR XOR

entity adder4 is port ( signal a,b: in std_logic_vector (3 downto 0); signal cin: in std_logic; signal sum: out std_logic_vector(3 downto 0); signal cout: out std_logic ); end adder4;

Explicit CarryIn and CarryOut


D

architecture behavior of adder4 is signal c: std_logic_vector(4 downto 0); begin process (a,b,cin,c) Temporary signal begin to hold internal carries. c(0) <= cin; for i in 0 to 3 loop sum(i) <= a(i) xor b(i) xor c(i); c(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i))); end loop; cout <= c(4); Use Looping construct to create logic for ripple carry end process; adder. end behavior;

OA1

AO1

OA1

AO1

AO1

A1

B1

A2

B2

B0

A0

OA1

A3

CIN

B3

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CombSyn27

Combinational Synthesis with VHDL

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CombSyn28

XOR

Combinational Synthesis with VHDL

Jan

94

14:07

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Ripple Carry Adder Comments


The Standard Logic 1164 package does not define arithmetic op-

Summary
Logic synthesis offers the following advantages: Faster design time, easier to modify The synthesis code documents the design in a more readable

erators for the std_logic type.


Most vendors supply some sort of arithmetic package for 1164

data types.
Some vendors also support synthesis using the + operation

manner than schematics.


Different optimization choices (area or speed) Several combinational VHDL examples were examined. Both concurrent and sequential statements can be used to

between two std_logic signal types (Synopsis). provide an explicit function call (Viewlogic).

Others

For code portability, it is best to avoid use of vendorspecific

arithmetic functions.

specify combination logic which you use is up to individual preference.

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CombSyn29

Combinational Synthesis with VHDL

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CombSyn30

Combinational Synthesis with VHDL

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Sequential Circuits
Logic which contains both combinational logic and storage ele-

ments form sequential circuits. All sequential circuits can be divided into a combinational block and a storage element block.
Inputs Outputs Combinational Logic

Logic Synthesis with VHDL Sequential Circuits

PresentState

State FlipFlops

NextState CLK

Single Phase Sequential System The above diagram shows a single-phase sequential system. In a

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single-phase system the storage elements are edgetriggered devices (flip-flops).


Mooretype outputs are a combinatorial function of

PresentState signals.
Mooretype outputs are a combinatorial function of both

PresentState and external input signals.


Multiple-phase design is also supported since latches can be syn-

thesized as the storage elements.

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SeqSyn2

Sequential Circuits

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Sequential Template
library declarations entity model_name is port ( list of inputs and outputs ); end model_name; architecture behavior of model_name is internal signal declarations begin the state process defines the storage elements state: process ( sensitivity list clock, reset, next_state inputs) begin vhdl statements for state elements end process state; the comb process defines the combinational logic comb: process ( sensitivity list usually includes all inputs) begin vhdl statements which specify combinational logic end process comb; end behavior;

8bit Loadable Register with Asynchronous clear


library ieee; use ieee.std_logic_1164.all; entity reg8bit is port ( signal clk, reset, load: signal din: signal dout: ); end reg8bit; in std_logic; in std_logic_vector(7 downto 0); out std_(7 downto 0)

architecture behavior of reg8bit is signal n_state,p_state : std_logic_vector(7 downto 0); begin dout <= p_state; comb: process(p_state,load,din) begin n_state <=p_state; if (load=1) then n_state <= din; end if; end process comb; state: process(clk, reset) begin if (reset = 0) then p_state <= (others => 0); elsif (clkevent and clk = 1) then p_state <= n_state; end if; end process state; end behavior;

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SeqSyn3

Sequential Circuits

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SeqSyn4

Sequential Circuits

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reg8bit State Process


DIN5 1

DOUT5

A B A Y B
OR2A AO1C

D Y

DFC1B

CLK CLR
1

state: process(clk, reset) begin if (reset = 0) then p_state <= (others => 0); elsif (clkevent and clk = 1) then p_state <= n_state; end if; end process state;

DIN4

B C
AO1C

DOUT4

DFC1B

CLK CLR

A Y
2

DOUT7

D A

Q
2

B
DIN7

OR2A DFC1B

B C
AO1C

CLK CLR

A Y B
DIN6
OR2A

DOUT6

D A B C
AO1C

DFC1B

CLK CLR

The state process defines a storage element which is 8bits wide,

A Y B
DIN1
OR2A

DOUT1

D A

DFC1B

rising edge triggered, and had a low true asynchronous reset.


The output of this process is the p_state signal.
4

B C
AO1C

CLK CLR

A Y B
OR2A

DOUT0

D A

Q
4

DFC1B

Note that the reset input has precedence over the clock in

DIN0

B C A Y B
OR2A AO1C

CLK CLR

order to define the asynchronous operation.


DIN2

A B C
AO1C

DOUT2

DFC1B

The event attribute is used to detect a change in the clock

A Y B
OR2A

CLK CLR

signal; comparing the current clock value against 1 implies that p_state gets the n_state value on a 0 to 1 transition (rising edge).
The state holding action of the process arises from the fact

A
5

Y B
DIN3
OR2A

A B C
AO1C

Y D Q

DOUT3

DFC1B

CLK

CLK CLR A

RESET_B

CLEAR_B

Y B
OR2A

A Y B
LOAD 6 6
OR2B

that p_state is not assigned a value is reset is not asserted and a rising clock edge does not occur.
A B C

reg8bit
WIR:reg8bit SCH:reg8bit 6 Jan D 94 14:25 SHEET E 1 OF 1

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SeqSyn5

Sequential Circuits

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SeqSyn6

Sequential Circuits

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wait Statement
An alternative method of specifying the storage elements is shown
HG

Finite State Machine Example


FG

below:
Traffic Light Controller

HL:GRN FL:RED

HL:RED FL:GRN

state: process begin wait until ((clkevent and clk = 1) or (reset = 0)); if (reset = 0) then p_state <= (others => 0); else p_state <= n_state; end if; end process state;
The wait statement is a sequential statement. The wait statement causes a suspension of a process or proce-

F TIMER T HGC HL:GRN FL:RED ALARM + CAR

TSTART_SHORT_TIMER

F CAR
start timer with short value

FY

HL:RED FL:YEL

T F ALARM T

TSTART_SHORT_TIMER

dure until the condition clause is satisfied.


The signals used in the condition clause form an implicit sensitivity

HY

HL:YEL FL:RED

TSTART_LONG_TIMER

list for the wait statement.


Can use wait on sig1, sig2, ..sigN until condition_clause to
start timer with long value

ALARM T

HG

explicitly specify the sensitivity list.


Note that the process has no sensitivity list. if statements used with processes generally give more flexibility

Upon RESET enter state HGC TSTART_LONG_TIMER

and control than wait statements .


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Traffic Light Controller Block Diagram

VHDL For Traffic Light FSM Control


library ieee; use ieee.std_logic_1164.all; vhdl model for the Traffic Light Control, sync reset, encoded states entity tlc_enc is port( signal reset, car, timer, clk: in std_logic; signal stateout: out std_logic_vector(2 downto 0); signal highway_light, farm_light: out std_logic_vector(1 downto 0); signal start_short_timer, start_long_timer: out std_logic ); end tlc_enc; State assignments architecture behavior of tlc_enc is constant HGC: std_logic_vector(2 downto 0) := constant HY: std_logic_vector(2 downto 0) := constant FG: std_logic_vector(2 downto 0) := constant FY: std_logic_vector(2 downto 0) := constant HG: std_logic_vector(2 downto 0) := 000; 001; 010; 011; 100; 00; 01; 11;

Glue select 0/1 0


long load LONG REG

TimerIn N

SHORT REG

load

1 en

short load

N TLC Control car car start_short_timer start_long_timer timer start_A start_B alarm count Timer Port B

N Port A

fl 2

hl 2

constant GREEN: std_logic_vector(1 downto 0) := constant YELLOW: std_logic_vector(1 downto 0) := constant RED: std_logic_vector(1 downto 0) := signal p_state, n_state : std_logic_vector(2 downto 0);

fl

hl

count

begin stateout <= p_state; statereg: process(clk, reset) if (reset = 0) then p_state <= HGC; elsif (clkevent and clk = 1) then p_state <= n_state; end if; end process statereg;

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VHDL For Traffic Light FSM (cont)


comb:process(car, timer, p_state) begin default assignments VERY IMPORTANT start_short_timer <= 0; start_long_timer <= 0; by default, stay in same state!!! n_state <= p_state; highway_light <= GREEN; farm_light <= RED;

VHDL For Traffic Light FSM Control (cont.)

All outputs should be assigned default values!! If you do not assign default values then outputs may get synthesized with output latches! Use if statements to enumerate states.

if p_state = FG then highway_light <= RED; farm_light <= GREEN; if timer = 1 or car = 0 then n_state <= FY; start_short_timer <= 1; end if; end if; if p_state = FY then highway_light <= RED; farm_light <= YELLOW; if timer = 1 then n_state <= HG; start_long_timer <= 1; end if; end if;

if p_state = HG then highway_light <= GREEN; farm_light <= RED; if (timer = 1) then n_state <= HGC; end if; end if;

if p_state = HGC then highway_light <= GREEN; farm_light <= RED; if car = 1 then n_state <= HY; start_short_timer <= 1; end if; end if; Start timer with long timeout value. if p_state = HY then highway_light <= YELLOW; farm_light <= RED; if timer = 1 then n_state <= FG; start_long_timer <= 1; end if; end if;

Start timer with short timeout value (yellow light).

end process comb; end behavior;

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START_SHORT_TIMER

START_LONG_TIMER

HIGHWAY_LIGHT0

HIGHWAY_LIGHT1

OneHot Encoding for FSMs


FARM_LIGHT1 STATEOUT0

FARM_LIGHT0

STATEOUT1

STATEOUT2

OneHot encoding of FSMs uses one flipflop per state. Only one flipflop is allowed on at anytime. E.G., states are 00001, 00010, 00100, 01000, 10000

for a five state FSM. All other states are illegal.


Y Y
AO1C

A Q B DFMB S CLK CLR

AO1C

OneHot encoding trades combinational logic for flipflops.


Y
INVA

INVA

NAND2B

Good for flipflop rich implementation technologies. Because the combinational logic is reduced, the length of the

critical path can be reduced resulting in a faster FSM. Speed increase is more significant for larger finite state machines.

CLK CLR

Q B D
CLK

OR2A

OR2A

INVA

A B C D

AO1

AO1

OR2A

Y A B C A B C Y Y Y A B C A B
NAND3B

OR2A

AND3

IMER

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ESET

CAR

INVA

CLK CLR

DFC1B

DFC1B

OR4A

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One Hot Encoding for TLC


library IEEE; use IEEE.std_logic_1164.all; entity tlc_onehot is port ( signal reset, car, timer, clk: in std_logic; signal stateout: out std_logic_vector(4 downto 0); signal highway_light,farm_light: out std_logic_vector(1 downto 0); signal start_long_timer,start_short_timer: out std_logic ); end tlc_onehot; architecture behavior of tlc_onehot is constant HG: integer := 0; constant HGC: integer := 1; constant HY: integer := 2; constant FG: integer := 3; constant FY: integer := 4;

One Hot Encoding for TLC


comb:process(car, timer, p_state) begin default assignments VERY IMPORTANT start_long_timer <= 0; start_short_timer <= 0; start <= 0; n_state <= p_state; highway_light <= GREEN; farm_light <= RED; if p_state(HG) = 1 then highway_light <= GREEN; farm_light <= RED; if (timer = 1) then n_state(HG) <= 0; n_state(HGC) <= 1; end if; end if; if p_state(HGC) = 1 then highway_light <= GREEN; farm_light <= RED; if car = 1 then n_state(HGC) <= 0; n_state(HY) <= 1; start_short_timer <= 1; end if; end if; if p_state(HY) = 1 then highway_light <= YELLOW; farm_light <= RED; if timer = 1 then n_state(HY) <= 0; n_state(FG) <= 1; start_long_timer <= 1; end if; end if;

State assignments now specify bit positions in the state FFs

constant GREEN: std_logic_vector(1 downto 0) := 00; constant YELLOW: std_logic_vector(1 downto 0) := 01; constant RED: std_logic_vector(1 downto 0) := 11; signal p_state, n_state : std_logic_vector(4 downto 0); begin stateout <= p_state; state: process(clk, reset) begin if (reset = 0) then p_state <= (HGC => 1, others => 0); elsif (clkevent and clk = 1) then p_state <= n_state; end if; end process state;

When changing states you must turn off current state FF and turn on next state FF.

Initial state is 00010

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One Hot Encoding for TLC


STATEOUT1 STATEOUT0 STATEOUT4 STATEOUT2 STATEOUT3 STIME START LTIME FL0 FL1 HL1 HL0

if p_state(FG) = 1 then highway_light <= RED; farm_light <= GREEN; if timer = 1 or car = 0 then n_state(FG) <= 0; n_state(FY) <= 1; start_short_timer <= 1; end if; end if; if p_state(FY) = 1 then highway_light <= RED; farm_light <= YELLOW; if timer = 1 then n_state(FY) <= 0; n_state(HG) <= 1; start_long_timer <= 1; end if; end if;
Y Y
AO1C

PRE D Q

DFP1B

DFMB

S CLK CLR

CLK

Y
INVA INVA

A B

A Q
NAND2B

AO1

OAI1

CLK CLR

CLK CLR

B CLK CLR
DFC1B

DFC1B

DFC1B

AO1C

AO1C

AO1C

NAND2B

OR2A

OR2A

AND2

OR3B

Y A B C A B C A B C C Y Y
OR2A OR3B

end process comb; end behavior;

OR3B

LARM

OR2A

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ESET

CAR

CLK

INVA

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Simple 4bit Shift Register


library IEEE; use IEEE.std_logic_1164.all;

Loop function for Shift Register


comb:process (p_state,din) begin n_state(0) <= din; for i in 3 downto 1 loop n_state(i) <= p_state(i 1); end loop;

din is serial input MSB of dout is the serial output

entity shift4 is port( signal clk, reset: in std_logic; signal din: in std_logic; signal dout: out std_logic_vector(3 downto 0) ); end shift4; architecture behavior of shift4 is signal n_state, p_state : std_logic_vector(3 downto 0); begin dout <= p_state; state: process(clk, reset) begin if (reset = 0) then p_state <= (others => 0); elsif (clkevent and clk = 1) then p_state <= n_state; end if; end process state; comb:process (p_state,din) begin n_state(0) <= din; for i in 3 downto 1 loop n_state(i) <= p_state(i 1); end loop; end process comb; end behavior;

end process comb;


LSB n_state(0) D Q DIN p_state(0) Left Shift Operation (LSB to MSB) n_state(1) D Q p_state(1) n_state(2) D Q p_state(2) i=1 i=2 MSB

Assign serial input din to the data input of the first flipflop Use for loop to connect output of previous flipflop to input of current flopflop

i=0

n_state(i) D p_state(i1) Q p_state(i)

ith stage

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Scan Path Synthesis


F OF 1 F SHEET

The forloop VHDL construct can be used to create a scanpath

shift4

DOUT0

DOUT1

DOUT2

DOUT3

in your design. A scan path is a design technique used for improving the testability of a design.
A scan path requires three extra pins on the design: scan,
E

14:46

scan_in, and scan_out.


When scan is asserted, all flipflops in the design act like a

WIR:shift4

SCH:shift4

CLK CLR

DFC1B

Jan

94

serial shift register; the scan_in pin is the serial input and the scan_out pin the serial output. When scan is negated the design functions normally.
Because all flipflops in the design are on the scan path the

6 D

CLK CLR

CLK CLR

CLK CLR

DFC1B

DFC1B

DFC1B

circuit can be placed in any desired state.


C

To enter a test vector via the scan path do: Assert scan.
DIN CLK RESET_B

Apply the test vector serially to the scan_in input; this


B

requires N clocks if N flipflops are on the scan path.


Negate scan, clock the circuit once. This will allow the circuit

to operate normally for one clock cycle; the result of the test vector will be loaded into the flipflops.
Assert scan; clock N times to clock out the test vector result

and to clock in the next test vector. Thus, each test vector requires N+1 clocks.
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4bit Register with Scan Path


entity scanreg4 is port ( scan, scan_in signal clk, reset_b, load: in std_logic; signals signal scan, scan_in: in std_logic; signal din: in std_logic_vector(3 downto 0); signal dout: out std_logic_vector(3 downto 0) scan_out will be ); end scanreg4; MSB of dout; dont need an extra pin architecture behavior of scanreg4 is for scan_out. signal n_state, p_state : std_logic_vector(3 downto 0); begin dout <= p_state; state: process(clk, reset) begin if (reset = 0) then p_state <= (others => 0); elsif (clkevent and clk = 1) then p_state <= n_state; end if; end process state;

Adding Scan to tlc_onehot.vhd


Add scan, scan_in to port list. scan_out will be MSB of port

stateout. entity tlc_onehot_scan is port ( signal reset, car, timer, clk: in std_logic; signal scan, scan_in: in std_logic; signal stateout: out std_logic_vector(4 downto 0); signal highway_light,farm_light: out std_logic_vector(1 downto 0); signal start_long_timer, start_short_timer: out std_logic ); end tlc_onehot_scan;
Add scan, scan_in to sensitivity list of process: state_machine.

When scan is asserted the scan path is active.

state_machine:process(scan, scan_in, reset, car, timer, p_state)


Add scan path in Architecture body:

process (scan,scan_in,load,p_state,din) begin n_state <= p_state; if (scan = 1) then n_state(0) <= scan_in; for i in 3 downto 1 loop n_state(i) <= p_state(i 1); Register functions end loop; normally when elsif (load = 1) then scan is negated. n_state <= din; end if; end process; end behavior;
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if (scan = 1) then n_state(0) <= scan_in; for i in 4 downto 1 loop n_state(i) <= p_state(i 1); end loop; else
if p_state(HG) = 1 then highway_light <= GREEN; farm_light <= RED; .... etc...
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Mapped to ITD stdcell library because Actel ACT1 does not have tristate capability.
A B C D

Register with TriState Output


A1 O invf101 A1 B1 C2 O 1 DIN5 A1 O invf101 D2 oaif2201

DATA1 dfrf301 Q CLK2 RST3 1

library IEEE; use IEEE.std_logic_1164.all;


A1 O invf101 A1 B1 C2 DIN4 A1 O invf101 buff121 CLK2 D2 oaif2201 RST3 DATA1 EN2 O DOUT4 O DATA1 dfrf301 Q

entity tsreg8bit is port ( signal clk, reset, load, en: in std_logic; signal din: in std_logic_vector(7 downto 0); signal dout: out std_logic_vector(7 downto 0) ); end tsreg8bit; architecture behavior of tsreg8bit is signal n_state, p_state : std_logic_vector(7 downto 0);

EN2 DATA1 A1 2 invf101 B1 C2 DIN7 A1 O invf101 CLK2 D2 oaif2201 RST3 buff121 DATA1 O O A1 DATA1 dfrf301 Q EN2 O O buff121

DOUT1

2 DOUT5

EN2 DATA1 O buff121 A1 O invf101 A1 B1 C2 DIN6 A1 O invf101 3 CLK2 D2 oaif2201 RST3 buff121 O DATA1 dfrf301 Q EN2 DATA1 O

DOUT7

DOUT6

begin dout <= p_state when (en = 1) else ZZZZZZZZ;

Make Z assignment to specify tristate capability.

A1

O invf101

A1 B1 C2 O

DATA1 dfrf301 Q CLK2

DIN1

A1

O invf101

D2 oaif2201 RST3

state: process(clk, reset) begin if (reset = 0) then p_state <= (others => 0); elsif (clkevent and clk = 1) then p_state <= n_state; end if; end process state; comb: process (p_state, load, din) begin n_state <= p_state; if (load = 1) then n_state <= din; end if; end process comb; end behavior;

A1

O invf101 A1 B1 O DATA1 dfrf301 Q invf101 D2 oaif2201 CLK2 RST3 buff121 EN2 DATA1 O DOUT0 4

DIN0

A1

C2

LOAD

A1 O B1 nanf201

CLEAR_B

A1 O B2 nanf251 DATA1 A1 O invf101 C2 5 DIN2 A1 O invf101 D2 oaif2201 RST3 5 A1 B1 O CLK2 buff121 dfrf301 Q EN2 DATA1 O DOUT2

A1

O invf101

A1 B1 C2 O DATA1 dfrf301 Q oaif2201 CLK2 RST3 EN2 DATA1 O buff121 DOUT3

DIN3

A1

O invf101

D2

CLK

RESET_B 6 EN 6

tsreg8bit
WIR:tsreg8bit SCH:tsreg8bit 6 A B C Jan 94 14:50 SHEET D 1 OF 1

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VHDL Packages
A VDHL package is a mechanism for collecting procedures, func-

tions, constants, and components for future reuse.


A package contains a package declaration followed by a package

body.
Package declaration

Logic Synthesis with VHDL System Synthesis

package package_name is

{ external constant, procedure, function, component declarations } end package_name;


Package body

package body package_name is

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{constant, procedure, function, component definitions } end package_name;


Any items in the package declaration are available for external

use. There can be items in the package body which are not in the package declaration; these items are only available for use within the package.

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Example VHDL Package


Library IEEE; use IEEE.std_logic_1164.all; package iscas is procedure ripple_adder (a,b: in std_logic_vector; cin: in std_logic; sum: inout std_logic_vector; cout: out std_logic); end iscas; package body iscas is function xor3 (a,b,c: in std_logic) return std_logic is begin return (a xor b xor c); end xor3; procedure ripple_adder (a,b: in std_logic_vector; cin: in std_logic; sum: inout std_logic_vector; cout: out std_logic) is variable c: std_logic_vector((ahighalow+1) downto 0); begin c(0) := cin; for i in 0 to (ahighalow) loop sum(i+sumlow) := xor3 (a(i+alow), b(i+blow), c(i) ); c(i+1) := (a(i+alow) and b(i+blow)) or (c(i) and (a(i+alow) or b(i+blow))); end loop; cout := c(chigh); end ripple_adder; end iscas;
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VHDL Functions
General form:

function function_name ( parameter list) return return_type is {variable declarations} begin {sequential statements} end function_name; function xor3 (a,b,c: in std_logic) return std_logic is begin return (a xor b xor c); end xor3;
A VHDL function computes a return value based upon its parame-

ter list.
All parameters passed to a VHDL function must be of mode in;

i.e, the function is not allowed to modify any of the function parameters.
The default class of the elements in a parameter list for either

procedures or functions is variable.


Signals can be passed in the parameter list; in this case the

parameter list would look like: (signal a, b, c: std_logic)


More on the difference between variables and signals will be

given later.
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VHDL Procedures
General form:

Signals vs Variables
Only signals are used as the connection ports for VHDL entities. Variables are declared within process blocks, procedures,

procedure procedure_name ( parameter list) is {variable declarations} begin {sequential statements} end procedure_name;
The ripple_adder procedure implements the ripple carry adder

and functions.
Signals can only be declared within architecture bodies; they

can be passed as parameters to functions and procedures.


Signals are assigned via <=; Variables are assigned via :=. From a simulation point of view: Signals have events occurring on them and this event history

used in previous examples.


The ripple_adder procedure uses the local xor3 function defined

within the package. sum(i+sumlow) := xor3 (a(i+alow), b(i+blow), c(i) );


For generality, the input parameters a and b as well as the output

is tracked via an internal event list.


Signal assignment can be delayed such as:

a <= 1 after 10 ns
Variable assignment is always immediate.

sum are declared as unconstrained array types; i.e., no array bounds are given for the std_logic_vector type.
Allows any width vector to be passed as a parameter. Array indices must be computed using the low attribute as an

a <= 1;
Signals require more overhead in terms of storage and

offset in order to achieve independence from the actual array indices which are passed in.

simulation time than variables. A general rule of thumb is to use variables wherever possible.
From a synthesis point of view, both variables and signals can turn

into internal circuit nodes.

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Using the ripple_adder Procedure


Library IEEE; use IEEE.std_logic_1164.all; use work.iscas.all;

A Carry Select Adder


Each stage computes part of the sum. Typically, the stage sizes increase; so a 16 bit adder stage sizes might be 4, 5, 7 = total of 16 bits. Ripple adders are used for stage adders. CS0 0 A CI A 1 CI 0 1 MUX SUM

entity adder_test is port ( signal a,b: in std_logic_vector (15 downto 0); signal cin: in std_logic; signal sum: out std_logic_vector(15 downto 0); signal cout: out std_logic ); end adder_test; architecture behavior of adder_test is

work is the default library name for packages. The all keyword says to use all externally available package items in the iscas package.

CI SUM

SUM B COUT K bits

SUM B COUT L bits CS0

SUM B COUT

begin process (a,b,cin) variable temp_sum: std_logic_vector (sumrange); variable temp_cout: std_logic; begin ripple_adder(a, b, cin, temp_sum, temp_cout); sum <= temp_sum; cout <= temp_cout; Call the ripple_adder procedure. Variables are used as parameters end process; end behavior;
within ripple_adder so variables must be passed in as arguments. These variables are then assigned to the target signals.

0 A CI A

1 CI 0 1 MUX

CS1 SUM

M bits

SUM B COUT

SUM B COUT

CS1 ....... etc.


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Carry_Select_Adder Procedure
procedure carry_select_adder (groups: iarray; a,b: in std_logic_vector; cin: in std_logic; sum: inout std_logic_vector; cout: out std_logic) is variable low_index, high_index :integer; variable temp_sum_a, temp_sum_b : std_logic_vector(sumrange); variable carry_selects :std_logic_vector(groupsrange); variable carry_zero :std_logic_vector(groupslow to (groupshigh1)); variable carry_one :std_logic_vector(groupslow to (groupshigh1)); begin low_index := 0; for i in groupslow to groupshigh loop high_index := (groups(i)1) + low_index ; if (i = 0) then first group, just do one ripplecarry ripple_adder (a(high_index downto low_index), b(high_index downto low_index), cin, sum(high_index downto low_index), carry_selects(0) ); else need to do two ripple carry adders then use mux to select ripple_adder (a(high_index downto low_index), b(high_index downto low_index), 0, temp_sum_a(high_index downto low_index), carry_zero(i1)); ripple_adder (a(high_index downto low_index), b(high_index downto low_index), 1, temp_sum_b(high_index downto low_index), carry_one(i1)); if (carry_selects(i1) = 0) then sum(high_index downto low_index) := temp_sum_a(high_index downto low_index); else sum(high_index downto low_index) := temp_sum_b(high_index downto low_index); end if; carry_selects(i) := (carry_selects(i1) and carry_one(i1) ) or carry_zero(i1); end if; low_index := high_index + 1; end loop; cout := carry_selects(groupshigh); end ripple_adder;

iscas Package Declaration


Library IEEE; use IEEE.std_logic_1164.all; package iscas is type IARRAY is array (natural range <>) of integer; procedure ripple_adder (a,b: in std_logic_vector; cin: in std_logic; sum: inout std_logic_vector; cout: out std_logic); procedure carry_select_adder (groups: iarray; a,b: in std_logic_vector; cin: in std_logic; sum: inout std_logic_vector; cout: out std_logic); end iscas;
We need to declare an array type for integers; call this IARRAY.

This type will be used to pass in an integer array to the carry_select_adder procedure; the integer array will be define the stage sizes for the adder.
Since xor3 is to be local to the iscas package; it is not in the pack-

age declaration. However, if it was to be made externally available, its declaration would be: function xor3 (a,b,c: in std_logic) return std_logic;

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6 5 2

7 3

4 8 9

11 9 10

12

12

13

14

15

n1044 n1038 n1031 n1024 n1018 n1011 n1042

a(4)

a(6)

a(1)

a(7)

a(11)

a(12)

a(12)

a(8)

a(13)

b(15:0) 4 5 6 2 1 7 3 8 5 8 9 7 3 2 1 11 10 12 12 13 14 13 11 15 4 10 0

a(14)

b(7)

n1040 n1041 n1039

b(11)

n1035

n1055

n1026 n1028

n1029

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n1015

a(10) 10 n1054 10b(10) n1001 n974 n975 b(4) n976

n1000

1 b(1) n966 1 a(1) b(1) 2 b(2) a(2) 2 n1048 n1047

a(9)

n984

a(10)

n1059

b(8)

n1053

n994

8 a(6) 6 b(6) 6 n977 n995

a(8)

n1064 n961

n1032

b(5)

n1004

n1051 n1050

n1003 sum(5) 5

n982 n992

n958

n1045

sum(15:0)

n959 n963 n986 n989 n990 b(15) n957 a(15) cout 15 15 a(15) b(15) cout n960

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n997

System12
C

n1058

Bob Reese 5/95


1
cin a(15:0) a(15:0) b(15:0)

n1027

10

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Library IEEE; use IEEE.std_logic_1164.all; use work.iscas.all;

end behavior;

architecture behavior of adder_cs is the adder. 4 + 5 + 7 = 16 bits.

entity adder_cs is port ( signal a,b: in std_logic_vector (15 downto 0); signal cin: in std_logic; signal sum: out std_logic_vector(15 downto 0); signal cout: out std_logic ); Define local constant array of inend adder_cs;

stage sizes are known at compile begin time. process (a,b,cin) variable temp_sum: std_logic_vector (sumrange); variable temp_cout: std_logic; constant groups: iarray(0 to 2) := (4,5,7);

Using the carry_select_adder Procedure

begin carry_select_adder(groups,a,b,cin,temp_sum, temp_cout); sum <= temp_sum; cout <= temp_cout; end process;

System11

Must be a constant array so that

tegers to define the stage sizes for

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System Design with VHDL


2 3 4 5
n993 n1020 n1021 n1057

A
n1016 a(6) 6 n1065 6 b(6) sum(6) n1043 6

n1034

sum(7) n1033 7 a(7) n1036 b(7)

n1037

sum(11) n1025 11 a(11) b(11)

11

n1030

a(12) 12 n1063 12b(12) n1023 n1022 sum(12) 12

n1019

n1013

sum(13)

13

B
13 b(13) a(14) 14 14a(14) b(14) 14 b(14) 14 a(13)

n1012

B
n1017 n1060

n1009 sum(14) n1062 n1010 14

n1061 n1008 b(14) a(9) 9 a(0) n1005 b(0) sum(0) 0 n1007

a(10) 9 b(9) b(10)

sum(10)

10

sum(15:0)

0 b(0) cin b(0) 0 0 a(0) b(10) n965 b(12)

n1056 n973

sum(15) n999 n985 b(12) b(13) b(2) a(2) 3 b(3) n968 a(3) 3 b(2) n967 b(3) a(3) a(2) n988 sum(2) n983

15

n1014

a(1) n991 b(1)

sum(1)

C
a(3) n987 b(8) a(8) 8 a(5) n1049 n969 n996 n964 n962 n1006 sum(9) 9 b(8) 8 b(3) sum(3) 3

b(9) b(6) n1052 n998 n972 b(5)

a(9)

n971

sum(8)

a(8) n1002

n980 n981 n970 a(4) n1046 b(4) n979

sum(4)

a(5)

D
n978

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VHDL Generic lists


Library IEEE; use IEEE.std_logic_1164.all; use work.iscas.all; Generic declaration which is used to define the a,b,sum signal widths.

VHDL Generic lists (cont.)


VHDL generic lists are used in entity declarations for passing stat-

ic information.
Typical uses of generics are for controlling bus widths, feature

Default value is specified entity adder_test is as 16. generic ( N : integer := 16); port ( signal a,b: in std_logic_vector (N1 downto 0); signal cin: in std_logic; signal sum: out std_logic_vector(N1 downto 0); signal cout: out std_logic ); end adder_test; architecture behavior of adder_test is begin process (a,b,cin) variable temp_sum: std_logic_vector (sumrange); variable temp_cout: std_logic; begin ripple_adder(a, b, cin, temp_sum, temp_cout); sum <= temp_sum; cout <= temp_cout; end process; end behavior;
Bob Reese 5/95 System13 System Design with VHDL

inclusion, message generation, timing values.


A generic will usually have a specified default value; this value can

be overridden via VHDL configurations or by vendorspecific backannotation methods.


Generics

offer a method for parameterizing entity declarations and architectures. Because the method of specifying generic values (other than defaults) can be vendor specific, generics will not be covered further in this tutorial.

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System Design with VHDL

Electrical & Computer Engineering

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Operator Overloading
Library IEEE; use IEEE.std_logic_1164.all; package genmux is 2/1 version, 1 bit inputs function mux (a,b: std_logic; sel: std_logic) return std_logic; 2/1 version, N bit inputs function mux (a,b: std_logic_vector; sel: std_logic) return std_logic_vector; 3/1 version, 1 bit inputs function mux (a,b,c: std_logic; sel: std_logic_vector) return std_logic; 3/1 version, N bit inputs function mux (a,b,c: std_logic_vector; sel: std_logic_vector) return std_logic_vector; 4/1 version, 1 bit inputs function mux (a,b,c,d: std_logic; sel: std_logic_vector) return std_logic; 4/1 version, N bit inputs function mux (a,b,c,d: std_logic_vector; sel: std_logic_vector) return std_logic_vector; end genmux; package body genmux is function mux (a,b: std_logic; sel: std_logic) return std_logic is variable y: std_logic; begin y := a; if (sel = 1) then y := b; end if; return(y); end mux; 2/1 version, 1 bit inputs function mux (a,b: std_logic_vector; sel: std_logic) return std_logic_vector is variable y: std_logic_vector(arange); begin y := a; if (sel = 1) then y := b; end if; return(y); end mux; 2/1 version, N bit inputs

Operator Overloading (cont.)


function mux (a,b,c: std_logic; sel: std_logic_vector) return std_logic is variable y: std_logic; begin y := ; Dont care for default state if (sel = 00) then y := a; end if; if (sel = 01) then y := b; end if; if (sel = 10) then y := c; end if; return(y); end mux; 3/1 version, 1 bit inputs function mux (a,b,c: std_logic_vector; sel: std_logic_vector) return std_logic_vector is variable y: std_logic_vector(arange); begin y := (others => ); Dont care for default state if (sel = 00) then y := a; end if; if (sel = 01) then y := b; end if; if (sel = 10) then y := c; end if; return(y); end mux; 3/1 version, N bit inputs function mux (a,b,c,d: std_logic; sel: std_logic_vector) return std_logic is variable y: std_logic; begin y := d; if (sel = 00) then y := a; end if; if (sel = 01) then y := b; end if; if (sel = 10) then y := c; end if; return(y); end mux; 4/1 version, 1 bit inputs function mux (a,b,c,d: std_logic_vector; sel: std_logic_vector) return std_logic_vector is variable y: std_logic_vector(arange); begin y := d; if (sel = 00) then y := a; end if; if (sel = 01) then y := b; end if; if (sel = 10) then y := c; end if; return(y); end mux; 4/1 version, N bit inputs end genmux;

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System Design with VHDL

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System Design with VHDL

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Test of mux Function


A B C

Library IEEE; use IEEE.std_logic_1164.all; use work.genmux.all; entity muxtest is port ( signal a,b,c: in std_logic; signal s_a: in std_logic_vector(1 downto 0); signal y: out std_logic; signal j,k,l: in std_logic_vector(3 downto 0); signal s_b: in std_logic_vector(1 downto 0); signal z: out std_logic_vector(3 downto 0) ); end muxtest; architecture behavior of muxtest is

z(3:0)

z(0) 0

z(1) 1

z(2) 2

z(3) 3

n156

n154

n152

n155

n153

n151

n164

n149

n150

k(0) 0

k(1) 1

2 k(2)

j(0)

j(1)

j(2)

k(3) 3

3 j(3)

2 l(2)

1 l(1)

0 l(0)

n157

n159

l(3)

s_a(0) 0

s_a(0) 0

n163

n158

n160

s_b(0) 0

s_a(1)

s_b(1) 1

s_a(1:0)

l(3:0)

k(3:0)

j(3:0)

j(3:0)

l(3:0)

The mux operator is overloaded; the correct mux function is chosen by doing template matching on the parameter lists.

s_b(1:0)

s_a(1:0)

k(3:0)

end behavior;

s_b(1:0)

Bob Reese 5/95

System17

System Design with VHDL

Bob Reese 5/95

System18

System Design with VHDL

y <= mux (a,b,c,s_a); z <= mux (j,k,l,s_b);

n161

begin

s_b(0) 0

5
n162

8
z(3:0)

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BlackJack Dealer
This example will be a BlackJack Dealer circuit (example taken
GET

BlackJack Dealer Control


BlackJack Dealer

from The Art of Digital Design, Prosser & Winkel, PrenticeHall).


One VHDL model will be written for the control and one for the dawait for card F card.rdy.sync T card.rdy.delay F Fstand.out Fbroke.out Start game over stand + broke F ADD MUX: Select Card REG: Load score T acecard F ace11flag T MUX: Select ADD10 REG: Load score Tace11flag.out Use ACE as 11 T REG: Clear score Face11flag.out T wait until button is lifted Thit

tapath. A schematic will be used to tie these two blocks together.


Later, a VHDL structural model will be used to connect the

blocks.
Control: Four States:

Get get a card Add add current card to score Use use an ACE card as 11 Test see if we should stand or if we are broke
Datapath: 5bit register for loading score; needs a synchronous clear. Mux for choosing between card value, plus 10 and minus 10. Adder for adding card with current score. ACE card detect (an ACE card has value 0001) Comparator logic for checking is score is greater than 16 or

Add card value

F USE

greater than 21.


Bob Reese 5/95 System19 System Design with VHDL Bob Reese 5/95

To TEST state
System20 System Design with VHDL

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BlackJack Dealer Control (cont)

BlackJack Datapath
5 +10 5 Card Switches 10 4 5 ADDER 2 5 5 Score REG 5 MUX 5

clear

TEST Cancel ACE=11 F score16gt T score21gt F Tstand.out Score is > 16 and < 21 so stand T ace11flag F Tbroke.out Score > 21 and we cant adjust an ACE value so we are broke MUX: Select SUB10 REG: Load score Face11flag.out T

sel
Ace Finder

load acecard score

ace11flag.out

ace11flag
5 Comparator

score16gt score21gt

Miscellanous Flip Flops to be included in Control Card Rdy button

card.rdy.sync

stand.out

stand

To GET state

card.rdy.delay

broke.out

broke

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System21

System Design with VHDL

Bob Reese 5/95

System22

System Design with VHDL

Electrical & Computer Engineering

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VHDL File for BlackJack Datapath


entity bjdpath is port ( signal clk,reset_b, load, clear_b: in std_logic; signal sel: in std_logic_vector(1 downto 0); signal card: in std_logic_vector(3 downto 0); signal acecard,score16gt,score21gt: out std_logic; signal score: out std_logic_vector(4 downto 0) );end bjdpath; architecture behavior of bjdpath is signal adder_out, score_in: std_logic_vector(4 downto 0) mux_out, score_out : std_logic_vector(4 downto 0); temporary signal for carries signal c: std_logic_vector (5 downto 0); begin score_state: process(clk, reset_b) begin if (reset_b = 0) then score_out <= 00000; elsif (clkevent and clk = 1) THEN score_out <= score_in; END IF; end process score_state; combinational logic for score register score_in <= 00000 when (clear_b = 0) else adder_out when (load = 1) else score_out;
State process for score register flip flops.

VHDL File for BlackJack Datapath (cont.)

ADDER process adder process adder_out <= score_out + mux_out adder:process (score_out, mux_out) begin c(0) <= 0; for i in score_outrange loop adder_out(i) <= score_out(i) xor mux_out(i) xor c(i); c(i+1) <= (score_out(i) and mux_out(i)) or (c(i) and (score_out(i) or mux_out(i))); end loop; MUX for end process adder;

mux_out <= 01010 when (sel = B00) else 10110 when (sel = B10) else 0 & card; acecard <= 1 when (card = B0001) else 0; score <= score_out;

card, plus 10, minus 10.

Combinational logic for Score Register

Ace Finder

score16gt <= 1 when (score_out > B10000) else 0; score21gt <= 1 when (score_out > B10101) else 0; end behavior;
Comparators

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System23

System Design with VHDL

Bob Reese 5/95

System24

System Design with VHDL

Electrical & Computer Engineering

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VHDL File for BlackJack Control

VHDL File for BlackJack Control (cont.)


begin state process to implement flag flipflops and FSM state state: process(clk, reset_b) begin if (reset_b = 0) then p_state <= 00; elsif (clkevent and clk = 1) THEN p_state <= n_state; ace11flag_pstate <= ace11flag_nstate; broke_pstate <= broke_nstate; stand_pstate <= stand_nstate; card_rdy_dly <= card_rdy_sync; State process to define flip card_rdy_sync <= card_rdy; flops for various flags and END IF; finite state machine . end process state; broke <= broke_pstate; stand <= stand_pstate;

entity bjcontrol is port ( signal clk, reset_b, card_rdy, acecard: in std_logic; signal score16gt, score21gt: in std_logic; signal hit, broke, stand: out std_logic; signal sel: out std_logic_vector(1 downto 0); signal score_clear_b, score_load: out std_logic ); end bjcontrol; architecture behavior of bjcontrol is
Entity declaration and State Assignments

declare internal signals here signal n_state, p_state : std_logic_vector(1 downto 0); signal ace11flag_pstate, ace11flag_nstate: std_logic; signal broke_pstate, broke_nstate: std_logic; signal stand_pstate, stand_nstate: std_logic; signal card_rdy_dly, card_rdy_sync: std_logic; state assignments are as follows constant get_state: std_logic_vector(1 downto 0) := B00; constant add_state: std_logic_vector(1 downto 0) := B01; constant test_state: std_logic_vector(1 downto 0) := B10; constant use_state: std_logic_vector(1 downto 0) := B11; constant constant constant add_10_plus: std_logic_vector(1 downto 0) := B00; add_card: std_logic_vector(1 downto 0) := B01; add_10_minus: std_logic_vector(1 downto 0) := B10;

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System25

System Design with VHDL

Bob Reese 5/95

System26

System Design with VHDL

Electrical & Computer Engineering

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VHDL File for BlackJack Control (cont.)


comb: process (p_state, ace11flag_pstate, broke_pstate, stand_pstate, acecard, card_rdy_dly, card_rdy_sync, score16gt, score21gt) begin sel <= B00; score_load <= 0; score_clear_b <= 1; hit <= 0; n_state <= p_state; ace11flag_nstate <= ace11flag_pstate; stand_nstate <= stand_pstate; broke_nstate <= broke_pstate; case p_state is when get_state => if (card_rdy_sync = 0) then hit <= 1; elsif (card_rdy_dly = 0) then stand_nstate <= 0; broke_nstate <= 0; if (stand_pstate = 1 or broke_pstate = 1) then score_clear_b <= 0; ace11flag_nstate <= 0; end if; get and add states n_state <= add_state; end if; when add_state => sel <= add_card; score_load <= 1; if (acecard = 1 and ace11flag_pstate = 0) then n_state <= use_state; else n_state <= test_state; end if;
Bob Reese 5/95 System27 System Design with VHDL

VHDL File for BlackJack Control (cont.)


when use_state => sel <= add_10_plus; score_load <= 1; ace11flag_nstate <= 1; n_state <= test_state; when test_state => use and if (score16gt = 0) then test states n_state <= get_state; elsif (score21gt = 0) then stand_nstate <= 1; n_state <= get_state; elsif (ace11flag_pstate = 0) then broke_nstate <= 1; n_state <= get_state; else sel <= add_10_minus; score_load <= 1; ace11flag_nstate <= 0; end if; when OTHERS => n_state <= p_state; end case; end process comb; end behavior;
Bob Reese 5/95 System28 System Design with VHDL

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Top Level Schematic for Dealer

Blackjack Dealer Simulation


Enter 5 Card Enter 8 Card Enter 4 Card

Initial Score of zero

Score = 5 + 0 = 5 Score = 8 + 5 = 13 Score = 13 + 4 = 17; score is > 16 so we STAND.

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System29

System Design with VHDL

Bob Reese 5/95

System30

System Design with VHDL

Electrical & Computer Engineering

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Blackjack Dealer Simulation (cont.)


First card is an Ace. Next card is a 2 Next card is a 9 Final card is a 10 (facecard)

Structural VHDL
You do not have to use a schematic to connect VHDL blocks. You

can write a structural VHDL model which ties the blocks together.
Pros: When you synthesize the design all of the VHDL blocks are

flattened (collapsed into one block) and it is possible that the resulting logic may be more efficient.
The structural VHDL code is more portable to other design

systems than a schematic.


Cons: Writing structural VHDL code can be more error prone than

creating a schematic (very easy to misplace a net when you dont have a picture to go by).
The resulting flattened netlist can be more difficult to debug.

Assertion of STAND from previous game causes us to start new game.

We will use the first Ace as a value of 11. Score = 11 + 2 = 13

13 + 9 > 21 so we break; however, we have an Ace so we can treat it as a value of 1; the new score is: 1 + 2 + 9 = 12. 12 + 10 > 21 so we are BROKE.

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System31

System Design with VHDL

Bob Reese 5/95

System32

System Design with VHDL

Electrical & Computer Engineering

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Structural VHDL for BlackJack Player


entity bj_struct is port ( Normal entity signal reset_b, clk, card_rdy : in std_logic; declaration. signal card: in std_logic_vector(3 downto 0); signal stand, broke,hit: out std_logic; signal score: out std_logic_vector(4 downto 0) ); end bj_struct; architecture structure of bj_struct is component bjcontrol port ( signal clk,reset_b: signal card_rdy, acecard: signal score16gt, score21gt: signal hit, broke,stand: signal sel: signal score_clear_b: signal score_load: end component; component bjdpath port ( signal clk, reset_b: signal load, clear_b: signal sel: signal card: signal acecard, score16gt: signal score21gt: signal score: end component; Need a component declaration for each different type of component used in the schematic

Structural VHDL for BlackJack Player (cont)


signal load_net, clear_net, acecard_net : std_logic; Internal signal declarasignal sel_net : std_logic_vector (1 downto 0); tion for those nets not signal s21gt_net, s16gt_net: std_logic; connected to external ports. begin c1: bjcontrol Each component used in the port map ( design is given along with its port map. clk => clk, reset_b => reset_b, c1 is the component label, card_rdy => card_rdy, bjcontrol gives the compoacecard => acecard_net, nent type. score16gt => s16gt_net, score21gt => s21gt_net, hit => hit, broke => broke, stand => stand, sel => sel_net, score_clear_b => clear_net, score_load => load_net); Only two components in c2: bjdpath this design. port map ( clk => clk, reset_b => reset_b, load => load_net, clear_b => clear_net, sel => sel_net, card => card, acecard => acecard_net, score16gt => s16gt_net, score21gt => s21gt_net, score => score ); end structure;

in std_logic; in std_logic; in std_logic; out std_logic; out std_logic_vector(1 downto 0); out std_logic; out std_logic );

in std_logic; in std_logic; in std_logic_vector(1 downto 0); in std_logic_vector(3 downto 0); out std_logic; out std_logic; out std_logic_vector(4 downto 0) );

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System33

System Design with VHDL

Bob Reese 5/95

System34

System Design with VHDL

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Results of bj_struct Synthesis

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System35

System Design with VHDL

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