Lecture21&22-MOS Theory and I-V

characteristics
Jagannadha Naidu K
Ref : Weste CMOS VLSI Design, 3
rd
edition, 2006
Outline
Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed
MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
V
g
< 0
(b)
+
-
0 < V
g
< V
t
depletion region
(c)
+
-
V
g
> V
t
depletion region
inversion region
Terminal Voltages
Mode of operation depends on V
g
, V
d
, V
s
V
gs
= V
g
V
s
V
gd
= V
g
V
d
V
ds
= V
d
V
s
= V
gs
- V
gd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence V
ds
0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
V
g
V
s
V
d
V
gd
V
gs
V
ds
+
-
+
-
+
-
nMOS Cutoff
No channel
I
ds
= 0
+
-
V
gs
= 0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
nMOS Linear
Channel forms
Current flows from d to s
e
-
from s to d
I
ds
increases with V
ds
Similar to linear resistor
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
= V
gs
+
-
V
gs
> V
t
n+ n+
+
-
V
gs
> V
gd
> V
t
V
ds
= 0
0 < V
ds
< V
gs
-V
t
p-type body
p-type body
b
g
s
d
b
g
s
d
I
ds
nMOS Saturation
Channel pinches off
I
ds
independent of V
ds
We say current saturates
Similar to current source
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
< V
t
V
ds
> V
gs
-V
t
p-type body
b
g
s
d
I
ds
I-V Characteristics
In Linear region, I
ds
depends on
How much charge is in the channel?
How fast is the charge moving?
Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Q
channel
=
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Q
channel
= CV
C =
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Q
channel
= CV
C = C
g
=
ox
WL/t
ox
= C
ox
WL
V =
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
C
ox
=
ox
/ t
ox
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel
Q
channel
= CV
C = C
g
=
ox
WL/t
ox
= C
ox
WL
V = V
gc
V
t
= (V
gs
V
ds
/2) V
t
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
C
ox
=
ox
/ t
ox
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v =
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E =
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E = V
ds
/L
Time for carrier to cross channel:
t =
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E = V
ds
/L
Time for carrier to cross channel:
t = L / v
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
ds
I =
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ds
Q
I
t
=
=
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W
V
C V V V
L
V
V V V

=

=



=


ox
=
W
C
L

nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases
current
ds
I =
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases
current
2
dsat
ds gs t dsat
V
I V V V

=


nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases
current
( )
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V

=


=
nMOS I-V Summary
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V

<

= <

>

Shockley 1
st
order transistor models
Example
We will be using a 0.6 m process for your project
From AMI Semiconductor
t
ox
= 100
= 350 cm
2
/V*s
V
t
= 0.7 V
Plot I
ds
vs. V
ds
V
gs
= 0, 1, 2, 3, 4, 5
Use W/L = 4/2
( )
14
2
8
3.9 8.85 10
350 120 /
100 10
ox
W W W
C A V
L L L

= = =

0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
d
s

(
m
A
)
V
gs
= 5
V
gs
= 4
V
gs
= 3
V
gs
= 2
V
gs
= 1
pMOS I-V
All doping and voltages are inverted for pMOS
Mobility
p
is determined by holes
Typically 2-3x lower than that of electrons
n
120 cm
2
/V*s in AMI 0.6 m process
Thus pMOS must be wider to provide same current
In this class, assume
n
/
p
= 2
Capacitance
Any two conductors separated by an insulator
have capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion
Gate Capacitance
Approximate channel as connected to source
C
gs
=
ox
WL/t
ox
= C
ox
WL = C
permicron
W
C
permicron
is typically about 2 fF/m
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9
0
)
polysilicon
gate
Diffusion Capacitance
C
sb
, C
db
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to C
g
for contacted diff
C
g
for uncontacted
Varies with process