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74ACT164 Serial-In Parallel-Out Shift Register

November 1993

74ACT164 Serial-In Parallel-Out Shift Register


General Description
The 74ACT164 is a high-speed 8-bit serial-in parallel-out shift register Serial data is entered through a 2-input AND gate synchronous with the Low-to-High transition of the clock The device features an asynchronous Master Reset which clears the register setting all outputs Low independent of the clock

Features
Y Y

Outputs source sink 24 mA ACT has TTL-compatible inputs

Logic Symbol

Connection Diagram
Pin Assignment for SOIC

TL F 11553 1

Pin Names A B CP MR Q0 Q7

Description Data Inputs Clock Pulse Input (Active Rising Edge) Master Reset Input (Active Low) Outputs

TL F 11553 2

FACTTM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation

TL F 11553

RRD-B30M75 Printed in U S A

Functional Description
The 74ACT164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages Data is entered serially through one of two inputs (A or B) either of these inputs can be used as an active High Enable for data entry through the other input An unused input must be tied High Each Low-to-High transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A  B) that existed before the rising clock edge A Low level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously forcing all Q outputs Low

Function Table
Operating Mode Reset (Clear) Shift Inputs MR L H H H H A X L L H H B X L H L H Q0 L L L L H Outputs Q1 Q7 LL Q0 Q6 Q0 Q6 Q0 Q6 Q0 Q6

H e High Voltage Levels L e Low Voltage Levels X e Immaterial Q e Lower case letters indicate the state of the referenced input or output one setup time prior to the Low-to-High clock transition

Logic Diagram

TL F 11553 3

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

Absolute Maximum Ratings (Note 1)


If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) DC Input Diode Current (IIK) VI e b0 5V VI e VCC a 0 5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO e b0 5V VO e VCC a 0 5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) SOIC
b 0 5V to a 7 0V b 20 mA a 20 mA b 0 5V to VCC a 0 5V b 20 mA a 20 mA b 0 5V to VCC a 0 5V
g 50 mA g 50 mA

Recommended Operating Conditions


Supply Voltage (VCC) ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 74ACT Minimum Input Edge Rate (DV Dt) ACT Devices VIN from 0 8V to 2 0V VCC 4 5V 5 5V 4 5V to 5 5V 0V to VCC 0V to VCC
b 40 C to a 85 C

125 mV ns

b 65 C to a 150 C

140 C

Note 1 Absolute maximum ratings are values beyond which damage to the device may occur The databook specifications should be met without exception to ensure that the system design is reliable over its power supply temperature and output input loading variables National does not recommend operation of FACT TM circuits outside databook specifications

DC Characteristics for ACT Family Devices


74ACT Symbol Parameter VCC (V) TA e a 25 C Typ VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 45 55 45 55 45 55 45 55 VOL Maximum Low Level Output Voltage 45 55 45 55 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC Input Minimum Dynamic Output Current Maximum Quiescent Supply Current 55 55 55 55 55 40 06 0 001 0 001 15 15 15 15 4 49 5 49 20 20 08 08 44 54 3 86 4 86 01 01 0 36 0 36
g0 1

74ACT TA e b 40 C to a 85 C Guaranteed Limits 20 20 08 08 44 54 3 76 4 76 01 01 0 44 0 44


g1 0

Units

Conditions

V V V

VOUT e 0 1V or VCC b 0 1V VOUT e 0 1V or VCC b 0 1V IOUT e b50 mA VIN e VIL or VIH b 24 mA IOH b 24 mA IOUT e 50 mA VIN e VIL or VIH 24 mA IOL 24 mA VI e VCC GND VI e VCC b 2 1V VOLD e 1 65V Max VOHD e 3 85V Min VIN e VCC or GND

V V

V mA mA mA mA mA

15 75
b 75

40 0

All outputs loaded thresholds on input associated with output under test Maximum test duration 2 0 ms one output loaded at a time

AC Electrical Characteristics
74ACT Symbol Parameter VCC (V) Min fmax tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Propagation Delay MR to Qn 50 50 50 50 100 10 10 10 60 60 60 11 5 11 5 13 0 TA e a 25 C CL e 50 pF Typ Max 74ACT TA e b40 C to a 85 C CL e 50 pF Min 80 10 10 10 12 5 12 5 14 5 Max MHz ns ns ns Units

Voltage Range 5 0 is 5 0V g 0 5V

AC Operating Requirements
74ACT Symbol Parameter VCC (V) TA e a 25 C CL e 50 pF Typ tS tH tW tREC Set-Up Time HIGH or LOW A or B to CP Hold Time HIGH or LOW CP to A or B Pulse Width HIGH or LOW CP to MR Recovery Time MR to CP 50 50 50 50 05 00 05 05 74ACT TA e b40 C to a 85 C CL e 50 pF Units

Guaranteed Minimum 70 15 70 20 80 15 80 20 ns ns ns ns

Voltage Range 5 0 is 5 0V g 0 5V

Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 45 45 0 Units pF pF Conditions VCC e OPEN VCC e 5 0V

Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows

74ACT Temperature Range Family 74ACT e Commercial TTL-Compatible Device Type Package Code S e Small Outline Package (SOIC)

164

X Special Variations X e Devices Shipped in 13 reels Temperature Range C e Commercial (b40 C to a 85 C)

74ACT164 Serial-In Parallel-Out Shift Register

Physical Dimensions inches (millimeters)

14-Lead Small Outline Integrated Circuit (S) NS Package Number M14A

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