S i 5 2 11 2 - B 5 / B 6

PCI-E XPRESS G EN 3 DUAL O UTPUT C LOCK G ENERATOR

Features

PCI-Express Gen 1, Gen 2, and Gen 3 compliant Low power HCSL differential output buffers Supports Serial-ATA (SATA) at 100 MHz No termination resistors required 25 MHz Crystal Input or Clock input Triangular spread spectrum profile for maximum EMI reduction (Si52112-B6)

Extended Temperature: 40 to 85 C 3.3 V Power supply Small package 10-pin TDFN (3x3 mm) Si52112-B5 does not support spread spectrum outputs Si52112-B6 supports 0.5% down spread outputs

Ordering Information: See page 12

Applications
Network attached storage Multi-function printer

Pin Assignments Wireless access point Routers

VDD XOUT

1 2 3 4 5

10 9 8 7 6

VDD DIFF2 DIFF2 DIFF1 DIFF1

Description
XIN/CLKIN

Si52112-B5/B6 is a high-performance, PCIe clock generator that can source two PCIe clocks from a 25 MHz crystal or clock input. The clock outputs are compliant to PCIe Gen 1, Gen 2, and Gen 3 specifications. The ultra-small footprint (3x3 mm) and industry leading low power consumption make Si52112-B5/B6 the ideal clock solution for consumer and embedded applications.

VSS VSS

Patents pending

VDD

DIFF1 XIN/CLKIN XOUT

PLL

Divider DIFF2

VSS

Rev 1.0 4/13

Copyright 2013 by Silicon Laboratories

Si52112-B5/B6

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Si52112-B5/B6 TABLE O F C ONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Crystal Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. Calculating Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 6.1. TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2. TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

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1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Supply Voltage (extended) Supply Voltage (commercial) Symbol VDD(extended) VDD(commercial) Test Condition 3.3 V 5% 3.3 V 10% Min 3.13 2.97 Typ 3.3 3.3 Max 3.46 3.63 Unit V V

Table 2. DC Electrical Specifications

Parameter Operating Voltage Operating Supply Current Input Pin Capacitance Output Pin Capacitance Symbol VDD IDD CIN COUT Test Condition 3.3 V 10% Full Active Input Pin Capacitance Output Pin Capacitance Min 2.97 Typ 3.30 3 Max 3.63 17 5 5 Unit V mA pF pF

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Table 3. AC Electrical Specifications
Parameter Crystal Long-term Accuracy Clock Input CLKIN Duty Cycle CLKIN Rise and Fall Times CLKIN Cycle-to-Cycle Jitter CLKIN Long Term Jitter Input High Voltage Input Low Voltage Input High Current Input Low Current DIFF Clocks
Duty Cycle

Symbol LACC TDC TR/TF TCCJ TLTJ VIH VIL IIH IIL TDC TSKEW FOUT FACC tr/f2 TCCJ
Pk-PkGEN1

Test Condition Measured at VDD/2 differential Measured at VDD/2 Measured between 0.2 VDD and 0.8 VDD Measured at VDD/2 Measured at VDD/2 XIN/CLKIN pin XIN/CLKIN pin XIN/CLKIN pin, VIN = VDD XIN/CLKIN pin, 0 < VIN <0.8 Measured at 0 V differential Measured at 0 V differential VDD = 3.3 V All output clocks Measured differentially from 150 mV Measured at 0 V differential PCIe Gen 1 10 kHz < F < 1.5 MHz 1.5 MHz < F < Nyquist Includes PLL BW 24 MHz, CDR = 10 MHz

Min 45 0.5 2 35 45 0.6 300 0.3

Typ 100 28 24 1.35 1.4 0.4 0.5 31.5

Max 250 55 4.0 250 350 VDD+0.3 0.8 35 55 60 100 4.0 70 86 3.0 3.1 1.0 550 1.15 33 3

Unit ppm % V/ns ps ps V V A A % ps MHz ppm V/ns ps ps ps ps ps mV V V % kHz ms ns

Skew Output Frequency Frequency Accuracy Slew Rate Cycle-to-Cycle Jitter PCIe Gen 1 Pk-Pk Jitter PCIe Gen 2 Phase Jitter PCIe Gen 3 Phase Jitter Crossing Point Voltage at 0.7 V Swing Voltage High Voltage Low Spread Range Modulation Frequency Enable/Disable and Set-up Clock Stabilization from Powerup Stopclock Set-up Time

RMSGEN2 RMSGEN3 VOX VHIGH VLOW SRNG FMOD TSTABLE TSS

Down Spread, -B6 only -B6 only

30 10.0

Note: Visit www.pcisig.com for complete PCIe specifications.

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Table 4. Thermal Conditions
Parameter Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case (TDFN) Dissipation, Junction to Case (TSSOP) Dissipation, Junction to Ambient (TDFN) Dissipation, Junction to Ambient (TSSOP) Symbol TS TA TJ JC JC JA JA Test Condition Non-functional Functional Functional JEDEC (JESD 51) JEDEC (JESD 51) JEDEC (JESD 51) JEDEC (JESD 51) Min 65 40 Typ Max 150 85 150 38.3 37.0 90.4 Unit C C C C/W C/W C/W

124.0 C/W

Table 5. Absolute Maximum Conditions

Parameter Main Supply Voltage Input Voltage ESD Protection (Human Body Model) Flammability Rating Symbol VDD_3.3V VIN ESDHBM UL-94 Relative to VSS JEDEC (JESD 22 - A114) UL (Class) Test Condition Min 0.5 2000 Typ V0 Max 4.6 4.6 Unit V VDC V

Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during powerup. Power supply sequencing is not required.

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2. Crystal Recommendations
If using a crystal input, the device requires a parallel resonance crystal.

Table 6. Crystal Recommendations

Frequency Cut Loading Load Cap (Fund) 25 MHz AT Parallel ESR Drive Shunt Motional Tolerance Stability Cap (max) (max) (max) (max) 5 pF 0.016 pF 35 ppm 30 ppm Aging (max) 5 ppm

1215 pF <50 >150 W

2.1. Crystal Loading

Crystal loading is critical in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using two trim capacitors. It is important that the trim capacitors are in series with the crystal.

Figure 1. Crystal Capacitive Clarification

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2.2. Calculating Load Capacitors
In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading correctly. Again, the capacitance on each side is in series with the crystal. The total capacitance on both sides is twice the specified crystal load capacitance (CL). Trim capacitors are calculated to provide equal capacitive loading on both sides.

Figure 2. Crystal Loading Example

Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side)
Ce = 2 CL Cs + Ci

Total Capacitance (as seen by the crystal)

1 CLe = -----------------------------------------------------------------------------------------------------1 1 -------------------------------------------- + -------------------------------------------- Ce1 + Cs1 + Ci1 Ce2 + Cs2 + Ci2

CL:

Crystal load capacitance Actual loading seen by crystal using standard value trim capacitors Ce: External trim capacitors Cs: Stray capacitance (terraced) Ci: Internal capacitance (lead frame, bond wires, etc.)
CLe:

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3. Test and Measurement Setup
Figures 3 through 5 show the test load configuration for the differential clock signals.

O U T+
L1 = 5"

L1 5 0 2 pF

M e a s u re m e n t P o in t

O U T-

L1 5 0 2 pF

M e a s u re m e n t P o in t

Figure 3. 0.7 V Differential Load Configuration

Figure 4. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)

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Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)

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4. Pin Descriptions

VDD XOUT XIN/CLKIN VSS VSS

1 2 3 4 5

10 9 8 7 6

VDD DIFF2 DIFF2 DIFF1 DIFF1

Figure 6. 10-Pin TDFN Table 7. 10-Pin TDFN Descriptions

Pin # 1 2 3 4 5 6 7 8 9 10 Name VDD XOUT XIN/CLKIN VSS VSS DIFF1 DIFF1 DIFF2 DIFF2 VDD Type PWR 3.3 V power supply. O I GND GND 25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input). 25.00 MHz crystal input or 3.3 V, 25 MHz clock Input. Ground. Ground. Description

O, DIF 0.7 V, 100 MHz differential clock output. O, DIF 0.7 V, 100 MHz differential clock output. O, DIF 0.7 V, 100 MHz differential clock output. O, DIF 0.7 V, 100 MHz differential clock output. PWR 3.3 V power supply.

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5. Ordering Guide
Part Number Si52112-B5-GM2 Si52112-B5-GM2R Si52112-B5-GT Si52112-B5-GTR Si52112-B6-GM2 Si52112-B6-GM2R Si52112-B6-GT Si52112-B6-GTR Spread Option No Spread No Spread No Spread No Spread 0.5% Spread 0.5% Spread 0.5% Spread 0.5% Spread Package Type 10-pin TDFN 10-pin TDFNTape and Reel 8-pin TSSOP 8-pin TSSOP - Tape and Reel 10-pin TDFN 10-pin TDFNTape and Reel 8-pin TSSOP 8-pin TSSOP - Tape and Reel Temperature Extended, 40 to 85 C Extended, 40 to 85 C Extended, 40 to 85 C Extended, 40 to 85 C Extended, 40 to 85 C Extended, 40 to 85 C Extended, 40 to 85 C Extended, 40 to 85 C

Si52112

Bx

GM2R/GTR
Operating Temp Range: G: -40 to +85 C M2 :10-TDFN Package, ROHS6, Pb-free T: 8-TSSOP Package, ROHS6, Pb-free R: Tape & Reel (blank) = Tubes

Base part number

A: Product Revision A x=5: non spread outputs x=6: -0.5% spread outputs

Figure 7. Ordering Information

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6. Package Outlines
6.1. TDFN Package
Figure 8 illustrates the package details for the 10-pin TDFN. Table 8 lists the values for the dimensions shown in the illustration.

Figure 8. 10-Pin TDFN Package Drawing

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Table 8. TDFN Package Diagram Dimensions
Symbol A A1 A3 b D D2 e E E2 L aaa bbb ccc ddd eee 1.40 0.25 1.90 0.18 Min 0.70 0.00 Nom 0.75 0.02 0.20 REF. 0.25 3.00 BSC. 2.00 0.50 BSC 3.00 BSC 1.50 0.30 0.10 0.10 0.10 0.10 0.08 1.60 0.35 2.10 0.30 Max 0.80 0.05

Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 4. This drawing conforms to the JEDEC Solid State Outline MO-229.

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7. TSSOP Package
Figure 9 illustrates the package details for the 8-pin TSSOP. Table 9 lists the values for the dimensions shown in the illustration.

Figure 9. 8-Pin TSSOP Package Drawing

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Table 9. TSSOP Package Diagram Dimensions
Symbol A A1 A2 b c D E E1 e L L2 aaa bbb ccc ddd 0 0.45 4.30 Min 0.05 0.80 0.19 0.09 2.90 Nom 0.90 3.00 6.40 BSC 4.40 0.65 BSC 0.60 0.25 BSC 0.10 0.10 0.05 0.20 8 0.75 4.50 Max 1.20 0.15 1.05 0.30 0.20 3.10

Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AA. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.

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8. Recommended Design Guideline
3.3 V

VDD 4.7 F 0.1 F Si5211x

Note: FB Specifications: DC resistance 0.10.3 Impedance at 100 MHz > 1000

Figure 10. Recommended Application Schematic

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CONTACT INFORMATION
Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request.

Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

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