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EE201:

Digital Circuits and Systems

Section 4 Sequential Circuits

4.1 Overview o Sequential Circuits: De inition

The circuit whose outputs and ne t state depend on !oth the input signals and the present state of the circuit

!rinci"le #s"ot t$e error%&

'emory Elements
!resent State Cloc*e+t State

Com(inational )ogic
,n"ut Signals Out"ut Signals

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4.2 .li"/.lo"s S0 .li"/.lo"

S
SET

C"#

S 0 0 1 1 1 0 0 1 1

0 0 1 0 1

45 4 0 1 6

4 45 0 0 0 1 1 0 1 1 4 45 0 0 0 1 1 0 1 1

S 0 1 0 6 1 0 1 6 6

0 6 0 1 0 2 6 6 1 0

12 .li"/.lo"

$ %

SET

C"#

2 45 0 4 1 0 0 1 1 %4

D .li"/.lo"

SET

D 0 1

45 0 1

4 45 6 0 6 1

D 0 1

C"#

3 .li"/.lo"

D T

SET

3 0 1

45 4 %4

C"#

4 45 0 0 0 1 1 0 1 1

3 0 1 1 0

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4.7 Design o Sequential Circuits

8lgorit$m:
O(tain t$e descri"tion o circuit and create t$e

State Diagram
Determine t$e State 3a(le 'inimi9e t$e num(er o states 8ssign (inary codes to eac$ state Determine t$e num(er o C$oose t$e ty"e o

li"/ lo"s needed and give a letter sym(ol to eac$ o t$em li"/ lo"s

Starting rom State 3a(le: derive t$e E+citation

3a(le and t$e Out"ut 3a(le

Derive t$e minimi9ed circuit out"ut

unctions

and li"/ lo" in"ut unctions

Draw t$e )ogic Diagram

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4.4 E+am"le o Design

Design a sequential logic circuit w$ose out"ut ; is 1 e+ce"t w$en t$e in"ut 6 < 1 or at least our cloc- "eriods. 3$en t$e out"ut ; is 0. =se 1/2 li"/ lo"s.

State Diagram #6>;&

1>1 8 0>1 0>1 0>1 0>1 ? 1>1 C 1>1 D 1>0

State Coding
!resent State 8 ? C D Code 0 0 1 1 0 1 0 1

.li" .lo"s
@e require two 12 li"/ lo"s. )et5s name t$em 128 and 12?

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State 3a(le
!resent State 8 ? C D *e+t State 6<0 6<1 8 ? 8 C 8 D 8 D Out"ut ; 6<0 6<1 1 1 1 1 1 1 1 0

E+citation 3a(le
48 0 0 0 0 1 1 1 1 4? 0 0 1 1 0 0 1 1 6 0 1 0 1 0 1 0 1 458 0 0 0 1 0 1 0 1 45? 0 1 0 0 0 1 0 1 18 0 0 0 1 + + + + 28 + + + + 1 0 1 0 1? 0 1 + + 0 1 + + 2? + + 1 1 + + 1 0 ; 1 1 1 1 1 1 1 0

'inimisations and Equations JA

6A 48 4? 0 1 00 0 0 01 0 1 11 10

J A = XQ B

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KA
6A 48 4? 0 1 00 ) ) 01 11 1 0 10 1 0
KA = X

JB
6A 48 4? 0 1 00 0 1 01 11 10 0 1
JB = X

KB
6A 48 4? 0 1 00 01 1 1 11 1 0 10

K B = X + Q A = XQ A

Z
6A 48 4? 0 1 00 0 0 01 0 0 11 0 1 10 0 0
Z = XQ AQB

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4.B State 0eduction

De inition o Equivalent States
Two or more states of a sequential circuit are equivalent if for the same +alues for the inputs, ha+e e actly the same out"ut and determine the sequential circuit transition to the same ne+t state or to equi+alent states-

8lgorit$m or State 0eduction

.f more 2 or more states are equi+alent, one of them can be substituted with the other one The other states that ha+e transitions to one of the remo+ed states ha+e to ha+e their next states changed into the remaining equivalent state

8dvantages o State 0eduction

/y reducing the num!er of states, it is possi!le that the number of flip-flops and/or amount of combinational circuitry needed to implement the sequential circuit will decrease, reducing the cost of the circuit

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E+am"le o State 0eduction

"et1s assume that there is the following state ta!le:

!resent State 8 ? C D E . C

*e+t State 6<0 8 C 8 E 8 C 8 6<1 ? D D . . . . 6<0 0 0 0 0 0 0 0

Out"ut 6<1 0 0 0 1 1 1 1

States 2 and E are equi+alent 3same ne t states for the

same inputs and same outputs for the same inputs4

State reduction 56 state 2 will !e replaced !y E

!resent State 8 ? C D E .

*e+t State 6<0 8 C 8 E 8 E 6<1 ? D D . . . 6<0 0 0 0 0 0 0

Out"ut 6<1 0 0 0 1 1 1

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States D and 8 are equi+alent State reduction 56 state 8 will !e replaced !y D

!resent State 8 ? C D E

*e+t State 6<0 8 C 8 E 8 6<1 ? D D D D 6<0 0 0 0 0 0

Out"ut 6<1 0 0 0 1 1

/y reducing the num!er of states, the num!er of flip9flops and amount of com!inational circuitry needed to implement this sequential circuit could ha+e decreased, reducing the cost of the circuit :owe+er in this e ample the num!er of flip9flops remains the same-

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4.D State 8ssignment

De inition o State 8ssignment
3$e "rocess o assigning a (inary code to eac$ state

!ossi(ilities or State 8ssignment

3$ere are many "ossi(ilities to assign (inary codes to states 3$e num(er o "ossi(le o"tions increases e+"onentially wit$ t$e num(er o states 3$e cost o t$e com(inational circuit strongly de"ends on t$e state assignment c$osen 8lt$oug$ various State 8ssignment met$ods $ave (een "ro"osed: t$ere is no assignment "rocedure t$at guarantees a minimal cost or t$e resulting com(inational circuit

E+am"les o State 8ssignment

States 8 ? C D E 8ssign. 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 8ssign. 2 0 0 0 0 1 0 0 1 1 1 0 1 1 1 1 8ssign. 7 0 0 0 1 0 0 0 1 0 1 0 1 0 1 1

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4.E Fomewor Faving t$e ollowing state ta(le: design t$e sequential circuit ollowing state assignment 1: 2 and 7: res"ectively. !resent State 8 ? C D E *e+t State 6<0 8 C 8 E 8 6<1 ? D D D D 6<0 0 0 0 0 0 Out"ut 6<1 0 0 0 1 1