Asa Manual 2006

Limited Internal DESCRIPTION
Prepared (also subject responsible if other) No
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ASA210C, General Assembler Instructions

Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 4 4.1 4.2 4.3 4.4 4.5 4.6 Page 5 5 5 5 5 6 6 6 6 7 8 9 10 10 11 11 13 13 14 14 14 15 15 16 18 18 19 19 20 21 22 23 24 25 25 25 26 26 27 27 28
General ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. Revision Information .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. Abstract ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. Implementation ... ... .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. The Assembler Language . ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. Machine Characteristics . .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. Forlopp Support .. ... .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. Instructions for Reading from Store .. ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. RS, Read from Store . ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. RSE, Read from Store Extended . ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. RSI, Read from Store Indexed .. .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. RSII, Read from Store Indexed Indirect .. ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. RSS, Read Subvariable from Store . .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. RDP, Read Dynamic Buffer Pointer . .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. RDB, Read from Dynamic Buffer . ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. RDBI, Read from Dynamic Buffer Indexed . .. ... ... .. ... .. ... ... .. ... .. ... ... .. RCB, Read from Communication Buffer . ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. RCP, Read Communication Buffer Pointer . .. ... ... .. ... .. ... ... .. ... .. ... ... .. RFID, Read Forlopp Identity . ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. Instructions for writing in Store ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. WS, Write in Store .. .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. WSE, Write in Store Extended . .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. WSI, Write in Store Indexed . ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. WSII, Write in Store Indexed Indirect . ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. WSS, Write Subvariable in Store . ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. WHC, Write Halfword Constant . .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. WZ, Write Zeros .. ... .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. WO, Write Ones .. ... .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. FIRSI, File Insert Register to Store Indexed . ... ... .. ... .. ... ... .. ... .. ... ... .. WDB, Write in Dynamic Buffer .. .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. WDBI, Write in Dynamic Buffer Indexed . ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. WCB, Write in Communication Buffer . ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. CCBI, Copy Communication Buffer Indexed . ... ... .. ... .. ... ... .. ... .. ... ... .. WFID, Write Forlopp Identity . ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. Register Instructions ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. LCC, Load Character Constant . .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. LHC, Load Halfword Constant .. .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. LWCD, Load Word Constant Double .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. LHCE, Load Halfword Constant Extended . .. ... ... .. ... .. ... ... .. ... .. ... ... .. LAT, Load Absolute Time .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. MFR, Move from Register . ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... ..
A4 XSEIF R3

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4.7 4.8 4.9 4.10 4.11 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8 8.1
MFRE, Move from Register Extended ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. MTR, Move To Register . .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. TNB , Translate Number to Bit vector . ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. CFID, Clear Forlopp Identity . ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. TFID, Test Forlopp Identity ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. Arithmetic Instructions .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. AR, Add Register to Register ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ARD, Add Register to Register Double .. ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ACC, Add Character Constant To Register . .. ... ... .. ... .. ... ... .. ... .. ... ... .. AWC, Add Word Constant to register . ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. AWCD, Add Word Constant To Register Double ... .. ... .. ... ... .. ... .. ... ... .. AHCS, Add Halfword Constant To Store ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SR, Subtract Register from Register .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SRD, Subtract Register from Register Double .. ... .. ... .. ... ... .. ... .. ... ... .. SCC, Subtract Character Constant from Register . .. ... .. ... ... .. ... .. ... ... .. SWC, Subtract Word Constant from Register ... ... .. ... .. ... ... .. ... .. ... ... .. SWCD, Subtract Word Constant from Register Double .. ... ... .. ... .. ... ... .. SHCS, Subtract Halfword Constant from Store . ... .. ... .. ... ... .. ... .. ... ... .. MR, Multiply Register . ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. DR, Divide Register . .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. Shift and Logical Instructions .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SHL, SHift Left ... ... .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SHLD, SHift Left Double . .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SHR, SHift Right . ... .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SHRD, SHift Right Double ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ROL, ROtate Left . ... .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ROLD, ROtate Left Double ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ROR, ROtate Right . .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. RORD, ROtate Right Double . ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ER, Exclusive or in Register . ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. OR, Logical Or in Register ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. NR, Logical and in Register .. ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. NWC, Logical and with Word Constant .. ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. Local Jump Instructions ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. JLN, Jump Local Normal .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. JLL, Jump Local and Link . ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. JOR, Jump on One in Result Indicator .. ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. JZR, Jump on Zero in Result Indicator .. ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. JEC, Jump on Equality with Character Constant .. .. ... .. ... ... .. ... .. ... ... .. JUC, Jump on Unequality with Character Constant . ... .. ... ... .. ... .. ... ... .. JER, Jump on Equality between Registers . .. ... ... .. ... .. ... ... .. ... .. ... ... .. JUR, Jump on Unequality between Registers .. ... .. ... .. ... ... .. ... .. ... ... .. JGT, Jump on Greater Than . ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. JLT, Jump on Less Than . .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. JTR, Jump on Table Indexed by Register ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. JTS, Jump on Table Indexed by Store ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... ..
29 29 30 30 31 31 31 32 32 33 33 33 34 35 35 36 36 37 37 38 38 38 39 39 40 40 41 41 42 42 43 44 44 45 45 46 46 46 47 47 47 48 48 49 49 50
Signal Transmission Instructions .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. 51 SSN, Send Signal Normal ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. 51

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8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 9 9.1 9.2 10 10.1 10.2 10.3 10.4 10.5 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 11.17
SSIN, Send Signal Indirect Normal . .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSPD, Send Signal from Process Register Direct . .. ... .. ... ... .. ... .. ... ... .. SSL, Send Signal and Link .. ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSIL, Send Signal Indirect and Link .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSPL, Send Signal from Process register Linked . .. ... .. ... ... .. ... .. ... ... .. SSB, Send Signal via Job Buffer . ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSBD, Send Signal via Job Buffer Double . .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSIB, Send Signal Indirect via Job Buffer .. .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSIBD Send Signal Indirect via Job Buffer Double .. ... .. ... ... .. ... .. ... ... .. SCBS, Send Combined Backward Signal .. .. ... ... .. ... .. ... ... .. ... .. ... ... .. RCBS, Retrieve Combined Backward Signal ... ... .. ... .. ... ... .. ... .. ... ... .. SSPB, Send Signal from Process Register via Job Buffer . ... .. ... .. ... ... .. SSPBD Send Signal from Process Registers via Job Buffer Double ... ... .. XSTQ, Send Signal via Time Queue .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. XSTQD Send Signal via Time Queue Double .. ... .. ... .. ... ... .. ... .. ... ... .. SSRP, Send Signal to RP . ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSRPE Send Signal TO RP Extended .. ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSIP, Send Signal to IPNA ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSIPD, Send Signal to IPNA Double .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. XRST, Read from Signal Sending Table . ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. RBD, Receive Bulk Data .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSRPB, Send Bulk Signal to RP ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... ..
51 52 53 53 54 55 55 56 56 57 57 58 59 60 62 64 65 66 68 69 70 71
Miscellaneous Instructions ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. 73 EP, End of Program . .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. 73 SRT , Set Return Time .. .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. 74 Search Instructions . ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. BLO, Bit search for Leftmost One in Register ... ... .. ... .. ... ... .. ... .. ... ... .. BLOD, Bit search for Leftmost One in Register Double .. ... ... .. ... .. ... ... .. CS, Compare String .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. FESR, File search for Equality between Store and Register .. .. ... .. ... ... .. FCZS, File search for Change to Zero in Store . ... .. ... .. ... ... .. ... .. ... ... .. Macro Instructions .. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ADDR, Load Dened Address .. .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. BLNR, Load Block Reference Number .. ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. DUPL, Duplicate Instruction . ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ERD, Exclusive or in Register ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. JECD, Jump on Eq with Char Constant Double ... .. ... .. ... ... .. ... .. ... ... .. JERD, Jump on Equality between Register Double . ... .. ... ... .. ... .. ... ... .. JGETD Jump on Greater Than or Equal Double .. .. ... .. ... ... .. ... .. ... ... .. JGTD, Jump on Greater Than Double ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. JLETD Jump on Less Than or Equal Double ... ... .. ... .. ... ... .. ... .. ... ... .. JLTD, Jump on Less Than Double .. .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. JUCD, Jump on Unequality with Char Const Double ... .. ... ... .. ... .. ... ... .. JURD, Jump on Unequality between Register Double . .. ... ... .. ... .. ... ... .. LBNBA Load Base Address Number . ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. LBNSL, Load Signal Location .. .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. LCCE, Load Character Constant Extended .. ... ... .. ... .. ... ... .. ... .. ... ... .. LWC, Load Word Constant ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. NHC, Logical aNd with Halfword Constant . .. ... ... .. ... .. ... ... .. ... .. ... ... .. 74 74 75 75 76 77 78 78 79 79 80 80 81 81 82 82 82 83 83 84 84 84 85 85

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11.18 11.19 11.20 11.21 11.22 11.23 11.24 11.25
RECEIVE, Receive a Signal . ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SGLOC Signal Group Location . .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSLL, Send Signal Local and Link .. .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. SSLN, Send Signal Local Normal ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. TQINF Time Queue Information .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. TQINFI Time Queue Information Indirect ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. VAL , Load Dened Value . ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. XLLR, Load Location in Register . ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... ..
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1
1.1
General
Revision Information
This Descripttion is based on 13/1551-ANZ 211 60 Rev B. Changes in this document are a Clarication that the registers r4 and r5 are only used and set by the PLEX compiler for the instructions RSII and WSII. When writing the instruction manually nothing should be dened for the registers r4 and r5, only the registers r1, r2 and r3 should be dened.
1.2
Abstract
This paper denes and describes assembler instructions in ASA210C. It is valid for APZ 212 20 and later APZs. The paper describes instructions which are of a general nature only. Instructions which are used by the operating system for special purposes are described in the document ASA210C, Operating System Assembler Instructions. Parameters in the instructions are dened in the document ASA210C, Assembler Instruction Parameters. Binary formats of the machine operations are described in the document Machine Operation Binary Formats.
1.3
Implementation
This document is valid for APZ 212 20 and later APZs. When nothing else is said in the sections implementation below it implies that the machine instruction is implemented for all APZ models.
1.4
The Assembler Language

The assembler language ASA210C is built up of a number of assembler instructions. Assembler instructions are separated by semicolons. Each assembler instruction has its counterpart in one or several machine operations. For instance, the assembler instruction RS, Read from Store, can be compiled to one of the three machine instructions RSA, RSU or RSL depending on length of the a-parameter. The assembler instruction is to be used in source code and when assembler corrections are written. All numbers are treated as positive integers.

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A program label is dened by writing the name followed by a right-hand parenthesis before the keyword to which the reference is to be made in the assembler instruction. The assembler instructions may have parameters which are separated by following characters: a , A comma normally separates the parameters. b A dash between two parameters indicates that data is transferred between the parameters. The transfer is always done from the right-hand to the left-hand parameter. c / A slash separates variables and subvariables or a process register and part of that register.
1.5
Machine Characteristics
APZ 212 is a 32-bit machine. Assembler instructions which work differently on different register lengths have names which end on letter D. That is, the assembler instruction AR, Add Register, will inuence the 16 lower bits in a register whereas the assembler instruction ARD will affect all the 32 bits in a double word.
1.6
Forlopp Support
In order to support the forlopp concept, all buffered signal sending instructions described below also transfer the forlopp identity of the current forlopp as signal data. The current forlopp identity is cleared at the end of a job before a new signal is taken out from the signal buffer. Then, when a new signal is entered, the forlopp identity from that signal is loaded as current forlopp identity.
2
2.1
Instructions for Reading from Store

RS, Read from Store
a Format: RS r-var; b Function:

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Variable var is fetched from the store and stored right-justied in process register r. Variables larger than 32 bits and subvariables can not be read. c Example: RS WR1-CLINK; The contents of variable CLINK is transferred to register WR1. d Implementation: The assembler instruction RS generates one of the machine operations RSA, RSU or RSL.RSA will be generated if the base address of the variable is 1-63, RSU if it is 64-255 and RSL if it is 256-4095.
2.2
RSE, Read from Store Extended

a Format: RSE r-var; b Function: Variable var, which has a length of 2, 4 or 8 16-bit words, is fetched from the store and stored in process register r, r+1, r+2 etc. The rst word in the variable is stored in process register r, the next word in r+1 and so on. The variable may not be a subvariable. c Example: RSE WR6-MESSAGE; Assume that variable MESSAGE with a length of 64 bits is to be stored from and including register WR6. The rst word in MESSAGE is stored in WR6, the second word is stored in WR7, the third word is stored in WR8 and the fourth word is stored in WR9. d Note: Parameter r must not be a temporary variable. e Implementation: The assembler instruction RSE generates one of the machine operations RSEU or RSEL.RSEU will be generated if the base address of var is 1-255, else RSEL will be generated.

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2.3
RSI, Read from Store Indexed

a Format: RSI r1-var, r2, m; b Function: The instruction moves all or part of a variable array from the store to consecutive process registers. (The pointer has a xed value or is not used, the index runs consecutively.) Variables larger than 32 bits and subvariables can not be read. - IR species the index to the rst variable which is to be read. IR is not changed. - r1 species the register for the rst variable. - r2 species a register, which contains the number of variables to be transferred. If the contents of register r2=0 no transfer is carried out. The contents of r2 are always unaffected. - m species the maximum value for the contents of register r2. If the contents are greater than m+1, program error actions will be taken. 0 <= m <= 63. c Example: RSI DR0-DUMPVAR, PR0, 7; (IR=2, PR0=5) The ve variables with index = 2, 3, 4, 5 and 6 in variable array DUMPVAR are transferred to register DR0, DR1, DR2, DR3 and DR4. d Note 1: APS checks that r1s address + m <= 63 to prevent wrap-around. e Note 2: Parameter r1 must not be a temporary variable. f Implementation: The assembler instruction RSI generates one of the machine operations RSIU or RSIL. RSIU will be generated if the base address of var is 1-255, else RSIL will be generated.

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2.4
RSII, Read from Store Indexed Indirect

a Format: RSII r1-r2, r3, r4, r5; b Function: The instruction moves all or part of a variable array from the store to consecutive processor registers. The variable and the register where the rst index is to be loaded is addressed indirectly.The pointer has a xed value or is not used, the index runs consecutively from a given start value. Variables larger than 32 bits and subvariables can not be read. - Processor register r1 species which register that is to be loaded with the rst variable, see Note 2 below. - r2 is the base address number of the variable to read. - r3 is the number of indices to be read. If r3 = 0 then the entire variable will be read. - r4 is the rst used data register in register memory, RM, DR0 - DR23. - r5 is the last used data register in register memory, RM, DR0 - DR23. - IR contains the rst index of the variable to be read. - PR0 contains a valid pointer (if used). The parameters r4 and r5 are only used by the register allocation algorithms within APS. They do not affect the binary format of the instruction, and hence should not be dened when writng this instruction manually. c Example: RSII DR0-WR0,WR1; (WR1=3, IR=2, PR0=5) Three indexes from a variable is read to the processor registers. The base address number of the variable is taken from WR0. d Note 1: It is only possible to read data to data registers (DR0-DR23). e Note 2: The address of the register to be given in register r1 is expressed as the normal register address dened in the document ASA201C, assembler instruction parameters. DR0 has the address 6, DR1 has the address 7 and so on. DR23 has the address 29.

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2.5
RSS, Read Subvariable from Store

a Format: RSS r-var/vln; b Function: A subvariable which is included in the composite variable var is fetched from the store and stored right-justied in process register r. Variable var may not be a subvariable. The subvariable is pointed out with its size in vl and its sequence number in n. The subvariable may be max 32 bits. c Example: RSS WR12-CLINK/H3; The subvariable which corresponds to half-word 3 within the composite variable CLINK is transferred to process register WR12. d Implementation: The assembler instruction RSS generates one of the machine operations RSSU or RSSL. RSSU will be generated if the base address of var is 1-255, else RSSL will be generated.
2.6
RDP, Read Dynamic Buffer Pointer

a Format: RDP r-var; b Function: Buffer variable var is fetched from the store and stored right-justied in process register r b15-b0. Process register r is cleared before the transfer. The trace bit for writing in a variable in the base address table is saved in bit 31 in register r together with the length of the variable, which is stored in bits 16-27. Variable var shall have a length of 16 bits and may not be indexed. c Example : RDP WR0-BUFVAR; Buffer variable BUFVAR is transferred to register WR0 b15-b0. The base address tables bit for writing in a variable and a base address are stored in register r b31-b16.

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2.7
RDB, Read from Dynamic Buffer

a Format: RDB r-vlb, vl; b Function: Transfer of data to process register r from a (sub)-variable in a dynamic buffer. Pointer register PR1 contains a pointer to the buffer. Index register IR contains the index for the relevant variable in the buffer. Parameter vl species the length of the variable. Parameter vlb is used for specifying a subvariable within the indicated variable. c Example: RDB WR3-H0,H; The 8-bit variable which is pointed out by a buffer pointer in process register PR1 and an index in register IR is transferred right-justied to process register WR3, which is cleared before the transfer. d Note: THIS INSTRUCTION MAY NOT BE USED IN ASA SECTORS IN PROGRAMS. e Additional information: Addressing takes place in the following way: The banks absolute address WA is read from the base address whose number is known to the microprogram. The contents of (PR1[bit 0-11])*2 exp(V+Q) are added to WA. This gives the address to the rst word of the buffer. Parameter vl and the contents of register IR are then used to calculate the address within the buffer to the word which contains the relevant variable. This address is added to (WA+(PR1[bit 0-11])*2 exp(V+Q)). Reading can then take place from the data store and the specied subvariable is retrieved. V = 2log (variable length) Q = 2log (number of variables in array of variables)
2.8
RDBI, Read from Dynamic Buffer Indexed

a Format: RDBI r1/vlm-vlb, vl, r2, m; b Function:

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Transport of data to consecutive process registers from a (sub)variable array in a dynamic buffer.If the subvariable and the register variable are less than 16 bit the data are stored packed according to vlm. r1 indicates register for the rst variable. vlm species the length and rst position for the register variable when stored in r1. vlb species subvariable within the variable. vl species the length of the variable. r2 species the number of variables that shall be transferred. If r2=0, the instruction does not execute any action. m species the maximum value for the contents of register r2. If the contents are greater than m+1, software error actions are taken. 0 <= m <= 63. Process register PR1 (bit 0-11) contains pointer to the buffer. Index register IR contains index to the rst buffer variable. If the origin (sub)variable is greater than the register variable the data will be truncated. If the origin (sub)variable is smaller than the register variable the register variable will be lled with zeros from most signicant bit. Parts of bits 0-15 of process registers which are not written with register variables remain unchanged. c d=Example: RDBI DR0/H0-H0, H, AR2, 25; (IR=0,AR2=10) From the buffer pointed to by PR1, with the length 8 bits, 10 variables are read to process registers, the rst variable will be stored in DR0/H0, the second variable in DR0/H1, the third in DR1/H0 an so forth. d Note: THIS INSTRUCTION MAY NOT BE USED IN ASA SECTORS IN PROGRAMS. e Note 1: APS checks that r1s address + m <= 63 to prevent wrap-around.

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Note 2: Parameter r1 must not be a temporary variable.
2.9
RCB, Read from Communication Buffer

a Format: RCB r-var/vlb; b Function: Transfer of data to process register r from a (sub) variable in a Communication Buffer. Parameter var is the base address of the memory bank where the Communication Buffer is allocated. Pointer register PR0 contains a pointer to the buffer. Index register IR contains the index for the relevant variable in the buffer. The Communication Buffer variable size is dened by Base Address Table for memory bank. Default variable size is 16 bits. Larger variables than 16 bits can not be used. Parameter vlb is used for specifying a subvariable within the indicated variable. c Note: THIS INSTRUCTION MAY NOT BE USED IN ASA SECTORS IN PROGRAMS.
2.10
RCP, Read Communication Buffer Pointer

a Format: RCP r-var,h; b Function: Buffer variable var corresponding to a Communication Buffer is fetched from store. Bits 0-23 of the buffer variable contain the individual pointer to the Communication Buffer. Bits 24-31 of the buffer variable contain the base address of the memory bank. If bits 24-31 of variable var are equal to program constant h, the bits 24-31 are cleared to zero before the variable is stored right-justied in register r. If bits 24-31 are not equal to program constant h, software error actions are taken.

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Variable var shall have a length of 32 bits and may not be indexed. The variable may be allocated in a le (addressed by pointer). If the trace bit T for writing in a variable from the base address table is set it is saved in B23 in register r, and B30 in PR1 is set to one. c Note: THIS INSTRUCTION MAY NOT BE USED IN ASA SECTORS IN PROGRAMS.
2.11
RFID, Read Forlopp Identity

a Format: RFID var; b Function: The forlopp identity (FID) is copied from variable var to the register EXECFID. Variable var shall have a length of 32 bits. The variable must not be a subvariable.RFID is intended to be used directly after reception of signals which do not have a FID in the signal header. Such signals are received with the ENTER statement (EXTERN).If the FID is zero, software recovery actions will be taken. c Example: RFID COMMANDFID; The forlopp identity is transferred from the variable COMMANDFID to the register EXECFID.
3
3.1
Instructions for writing in Store

WS, Write in Store
a Format: WS var-r; b Function: The contents of the process register r are stored right-justied in variable var in the store. If the variable is smaller than 32 bits, that part of r which is not contained in the variable is truncated from the left. That part of the variable (if any) which is larger than 16/32 bits is not affected. Subvariables cannot be written. c Example:

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WS CLINK-WR1; Process register WR1 is stored in variable CLINK. d Implementation: The assembler instruction WS generates one of the machine operations WSA, WSU or WSL. WSA will be generated if the base address of the variable is 1-63, WSU if it is 64-255 and WSL if it is 256-4095.
3.2
WSE, Write in Store Extended

a Format: WSE var-r; b Function: Transfer of contents of process register r, r+1 etc. to a variable in the data store. The variable, which must have a size of 2, 4 or 8 words, receives the contents of process register r in the rst word, the contents of process register r+1 in the second word and so on. If the size of the variable is 1 word, WSE will do nothing. The variable may not be a subvariable. c Example: WSE MESSAGE-WR8; Assume that variable MESSAGE with a length of 64 bits is to receive the value of process register WR8, WR9, WR10 and WR11. Transfer of WR8 to word 0 in MESSAGE, of WR9 to word 1 in MESSAGE, of WR10 to word 2 in MESSAGE and of WR11 to word 3 in MESSAGE. d Note: Parameter r must not be a temporary variable. e Implementation: The assembler instruction WSE generates one of the machine operations WSEU or WSEL. WSEU will be generated if the base address of var is 1-255, else WSEL will be generated.
3.3
WSI, Write in Store Indexed

a Format: WSI var-r1, r2, m; b Function:

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This instruction transfers the contents of consecutive process registers to variables in a variable array in the store. (The pointer has a xed value or does not occur, the index runs consecutively). The contents of the process registers are placed right-justied in the variables. If the variables are less than 32 bits, that part of the process registers which cannot be contained in the variables is truncated from the left. In the case of variables larger than 16/32 bits, bit 16/32 and upwards are not affected. Subvariables cannot be written. - IR species an index to the rst receiving variable. - r1 species the rst register which is to be transferred. - r2 species a register, which contains the number of registers to be transferred. If the contents of register r2=0 no transfer is carried out. The contents of r2 are always unaffected. - m species the maximum value for the contents of register r2. If the contents are greater than m+1, program error actions are taken. 0 <= m <= 63. c Example: WSI DUMPVAR - WR22, PR0, 7; (IR=2, PR0=5) Bits 0-7 of process registers WR22, WR23, WR24, WR25 and WR26 are entered in the ve variables with indexes 2, 3, 4, 5 and 6 in variable array DUMPVAR (the variables have a length of 8 bits). d Note 1: APS checks that r1s address + m <= 63 to prevent wrap-around. e Note 2: Parameter r1 must not be a temporary variable. f Note 3: APS does not accept variables larger than 32 bit g Implementation: The assembler instruction WSI generates one of the machine operations WSIU or WSIL. WSIU will be generated if the base address of var is 1-255, else WSIL will be generated.
3.4
WSII, Write in Store Indexed Indirect

a Format: WSII r1-r2, r3, r4, r5;

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Function: This instruction transfers the contents of consecutive process registers to variables in a variable array in the store. Both the variable and the rst register where data is fetched from is addressed indirectly. The pointer has a xed value or is not used, the index runs consecutively from the given start value. Variables larger than 32 bits and subvariables can not be written. - Processor register r1 contains the base address number of the variable to be written. - r2 species the rst register that is to be transferred to the variable, see Note 2 below. - r3 is the number of indices to be transferred. If r3 = 0 then the entire variable will be written. - r4 is the rst used data register in register memory, RM, DR0 - DR23. - r5 is the last used data register in RM, DR0 - DR23 - IR contains the rst index of the variable to be written. - PR0 contains a valid pointer (if used). The parameters r4 and r5 are only used by the register allocation algorithms within APS. They do not affect the binary format of the instruction, and hence should not be dened when writng this instruction manually.
Note: THIS INSTRUCTION MAY NOT BE USED IN ASA SECTORS IN PROGRAMS.
Example: WSII WR0-DR0, WR1; (WR1=5, IR=2, PR0=5) Five consecutive data registers, DR0-DR4 is transferred to ve variables with indexes 2, 3, 4, 5, 6 to a variable array in the store. The base address number of the variable array is taken from WR0. The rst data register to use at the transfer is taken from DR0.
Note 1: It is only possible to transfer data from data registers (DR0-DR23).
Note 2:

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The address of the register to be given in r2 is expressed as the normal register address dened in the document ASA201C, assembler instruction parameters. DR0 has the address 6, DR1 has the address 7 and so on. DR23 has the address 29.
3.5
WSS, Write Subvariable in Store

a Format: WSS var/vln-r; b Function: The contents of process register r are transferred to a subvariable within the composite variable var in the store. The subvariable is pointed out with its size in bit vl and with its sequence number n. The vl right-hand bits in register r are stored in the indicated subvariable. The rest of the contents in the variable remain unchanged. c Example: WSS CLINK/H9-WR5; The 8 least signicant bits in process register WR5 are transferred to the subvariable which corresponds to half-word 9 within the composite variable CLINK. d Implementation: The assembler instruction WSS generates one of the machine operations WSSU or WSSL. WSSU will be generated if the base address of var is 1-255, else WSSL will be generated.
3.6
WHC, Write Halfword Constant

a Format: WHC var-h; b Function: The half-word constant h is transferred right-justied to a variable var in the data store. The variable var is cleared to zero before the transfer. If the variable is less than 8 bits, that part of h which cannot be contained in the variable is truncated from the left.

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Example: WHC TIMER-36; The numeric value 36 is stored in variable TIMER.
Implementation: The assembler instruction WHC generates one of the machine operations WHCU or WHCL. WHCU will be generated if the base address of var is 1-255, else WHCL will be generated.
3.7
WZ, Write Zeros

a Format: WZ var; b Function: Transfer of zeros to variable var in the data store. c Example: WZ ATIME; Variable ATIME is cleared to 0. d Implementation: The assembler instruction WZ generates one of the machine operations WZU or WZL. WZU will be generated if the base address of var is 1-255, else WZL will be generated.
3.8
WO, Write Ones

a Format: WO var; b Function: Transfer of ones to variable var in the data store. c Example: WO BTIME; All bits in variable BTIME are set to 1. d Implementation:

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The assembler instruction WO generates one of the machine operations WOU or WOL. WOU will be generated if the base address of var is 1-255, else WOL will be generated.
3.9
FIRSI, File Insert Register to Store Indexed

a Format: FIRSI var-r1, r2; b Function: The instruction transfers the contents of process register r1 up to r1+3 to variables in a variable array in the store. The pointer has a xed value or is not used and the index runs consecutively. The contents of the process registers are placed right-justied in the variables. If the variables are less than 32 bits, the part of the process register r1 which cannot be contained in the variables is truncated from left. In the case of variables larger than 32 bits, the variable receives the contents of process register r1 in the rst 32-bit word, the contents of process register r1+1 in the second 32-bit word and so on up to the contents of register r1+3. Subvariables cannot be written. - IR species the highest index to receiving variable added by 1. The transfer starts with the value in IR reduced by one. The transfer continues by decrementing the index value in register IR by 1 until the index value is equal to the contents of register r2. - r1 and possibly up to r1+3 species the register contents to be transferred to the variable array of possibly composite variables. The composite variable might have a size of 2, 4 or 8 16-bit words. - r2 species the lowest index to receiving variable. The contents of r2 are always unaffected. If the initial value of the contents of register IR is less than or equal to the contents of register r2, the program continues with the next instruction in sequence with unchanged register values. c Example: FIRSI 7-WR3, WR9; (WR3=0, IR=8, WR9=0) The indexed variable with base address 7 is set to zero (WR3) for indexes 7 down to 0. d Additional information: Instruction is interruptible. If there is an interrupt, the IR register contains the index to the last receiving variable.

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Note: THIS INSTRUCTION MAY NOT BE USED IN ASA SECTORS IN PROGRAMS.
3.10
WDB, Write in Dynamic Buffer

a Format: WDB vlb, vl-r; b Function: Transfer of data from process register r to a (sub) variable in a dynamic buffer. If the (sub)variable is smaller than 16 bits, that part of r which is not contained in the (sub)variable is truncated from the left. Pointer register PR1 contains a pointer to the buffer. Index register IR contains the index for the relevant variable in the buffer. Parameter vl species the length of the variable. Parameter vlb is used for specifying a subvariable within the indicated variable. c Example: WDB C2, W-WR3; The contents of process register WR3 are transferred to character 2 in the 16-bit variable indicated by a buffer pointer in register PR1 and an index in register IR. d Note 1: THIS INSTRUCTION MAY NOT BE USED IN ASA SECTORS IN PROGRAMS. e Note 2: PR1 should be loaded with instruction RDP if the program will only be used in APZ models which have RDP implemented. f Additional information: Addressing takes place as follows: The banks absolute address WA is read from the base address whose number is known to the microprogram. The contents of register(PR1[bit 0-11])*2 exp(V+Q) are added to WA. This provides the address to the rst word in the buffer. The address within the buffer to the word which contains the relevant variable is then calculated with the aid of parameter vl and the contents of register IR. This address is added to (WA+(PR1[bit 0-11])*2 exp(V+Q)). Writing can then take place to the data store. The subvariable which is specied by parameter vlm is masked out and changed according

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to the contents of process register r. The subvariable is then written back into the data store. V = 2log (variable length) Q = 2log (number of variables in array of variables)
3.11
WDBI, Write in Dynamic Buffer Indexed

a Format: WDBI vlb, vl-r1/vlm, r2,m; b Function: Transport of data to a (sub)variable in a dynamic buffer from consecutive process registers.If the register variable is less than 16 bits the data are stored packed in the process registers according to vlm and will be loaded in consecutive index in the variable. - r1 indicates register for the rst variable. - vlm species the length and rst position in the register variable. - vlb species subvariable within the variable. - vl species the length of the variable. - r2 species the number of variables that shall be transferred. If r2=0, the instruction does not execute any action. - m species the maximum number of affected process registers decremented by one. If the contents are greater than m+1, software error actions are taken (0 <= m <= 63). - Process register PR1 (bit 0-11) contains pointer to the buffer. Index register IR contains index to the rst buffer variable. If the register variable is greater than the (sub)variable the data will be truncated. If the register variable is smaller than the (sub)variable the receiving variable will be lled with zeros from most signicant bit. c Example: WDBI H0, H-DR0/H0, AR2, 32; (IR=0,AR2=10)

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To the buffer pointed to by PR1, with the length 8 bits, 10 variables are written from process registers. The rst variable is taken from DR0/H0, the second variable is taken from DR0/H1, the third from DR1/H0 an so forth. d Note 1: THIS INSTRUCTION MAY NOT BE USED IN ASA SECTORS IN PROGRAMS. e Note 2: Parameter r1 must not be a temporary variable. f Note 3: PR1 should be loaded with instruction RDP. g Note 4: APS checks that r1s address + m <= 63 to prevent wrap-around.
3.12
WCB, Write in Communication Buffer

a Format: WCB var/vlb-r; b Function: Transfer of data from process register r to a (sub) variable in a Communication Buffer. Parameter var is the base address of the memory bank where the Communication Buffer is allocated.Pointer register PR0 contains a pointer to the buffer. Index register IR contains the index for the relevant variable in the buffer. If the (sub) variable is smaller than 16 bits, that part of process register r which is not contained in the (sub) variable is truncated from the left. Pointer register PR0 contains a pointer to the buffer. Index register IR contains the index for the relevant variable in the buffer. The Communication Buffer variable size is dened by Base Address Table for memory bank. Default variable size is 16 bits. Larger variables than 16 bits can not be used. Parameter vlb is used for specifying a subvariable within the indicated variable. c Note: THIS INSTRUCTION MAY NOT BE USED IN ASA SECTORS IN PROGRAMS.

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3.13
CCBI, Copy Communication Buffer Indexed

a Format: CCBI hc, t, r; b Function: The instruction transfers a block of data from a communication buffer to the same or different Communication Buffer, or clears a block of data in a Communication Buffer. The indicated pointer register(s) contains a pointer to the buffer(s). The indicated index register(s) contains the start (low) index for the relevant variable in the buffer(s). The data block is copyed or cleared starting at the highest index, index running backwards until CR equals zero. The instruction does not support copying of even-to-odd or odd-to-even indexes. This means that the difference between Index to Copy from and Index to Copy to must be even. The compiler will otherwise generate an RCB/WCB loop. Overlapping indexes are not allowed if copying within a buffer. Register r points to the rst register where the instruction parameters are stored. The Communication Buffer variable size is dened by the Base Address Table for the memory bank. Default variable size is 16 bits. Subvariable is not allowed. hc is a reserved constant which should be set to zero. t t t t = 0 Clear CB = 1 Copy CB = 2 Reserved for Move (NOP in this version) = 3 Reserved for Broadcast (Copy in this version)
CR = Number of W16 to Copy / to Clear. If CR = 0, the instruction is terminated. r = a1 parameter & pointer to Copy to / to Clear r+1 = Index to Copy to / to Clear r+2 = a2 parameter & pointer to Copy from / not used r+3 = Index to Copy from / not used The instruction is interruptable. The data left to be copied is stored in rml[CR]. The other registers are left unchanged.

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Data Structure: Layout of register r and r+2:
31
24 23 22 Pointer
d Note:
a-par
THIS INSTRUCTION MAY NOT BE USED IN ASA SECTORS IN PROGRAMS.
3.14
WFID, Write Forlopp Identity

a Format: WFID var; b Function: The forlopp indentity (FID) is copied from the register EXECFID to variable var.Variable var shall have a length of 32 bits. The variable must not be a subvariable.WFID is intended to be used directly after the RETRIEVE statement. c Example: WFID COMMANDFID; The forlopp indentity is transferred from the register EXECFID to the variable COMMANDFID.
4
4.1
Register Instructions
LCC, Load Character Constant
a Format: LCC r-c; b Function: Program constant c is transferred to process register r. Constant c is placed right-justied in r. The rest of r is cleared to zero.

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Example: LCC WR2-8; Numeric value 8 is stored in process register WR2.
4.2
LHC, Load Halfword Constant

a Format: LHC r/vlp-h; b Function: Halfword constant h is transferred to a variable in process register r. The length and location of the variable within the register is specied by vlp. The storage takes place right-justied in the indicated part of the register. The indicated part of the register is cleared to zero before the transfer. The rest of the contents of process register r remain unchanged with the exception of vlp=H1 and vlp=W0 where r/W1 is cleared to zero. c Example 1: LHC WR0/H0-46; The numeric value 46 is stored in the rst half-word in process register WR0. The rest of WR0 remain unchanged. d Example 2: LHC WR1/W0-46; The numeric value 46 is stored in the rst half-word of process register WR1. The rest of WR1 is cleared to zero.
4.3
LWCD, Load Word Constant Double

a Format: LWCD r/vlr-w; b Function: Word constant w is transferred to process register r. The length and location of the variable within the register is specied by vlr. The storage takes place right-justied in the indicated part of the register. The indicated part of the register is cleared to zero before the transfer. The rest of the contents of process register r remain unchanged.

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Example: LWCD WR6/W0-1025; Numeric value 1025 is stored in process register WR6.
4.4
LHCE, Load Halfword Constant Extended

a Format: LHCE r/vlm-h; b Function: Halfword constant h is transferred to process register r. The length and position within the register are specied by vlm. Storage takes place right-justied in the indicated part of register r. The indicated part of the register is cleared before the transfer. The rest of the contents of the register remain unchanged. If vlm is smaller than 8 bits, truncation takes place from the left of that part of h which cannot be contained in the register. c Example 1: LHCE WR0/C3-12; Number 12 is transferred to character 3 in process register WR0. d Example 2: LHCE WR1/B2-12; Number 0 is transferred to bit 2 in process register WR1.
4.5
LAT, Load Absolute Time

a Format: LAT r1; b Function: Load the current time into process registers. The time values will be loaded as follows: r1 undened r1+1 year

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r1+2 month r1+3 day r1+4 hour r1+5 minute r1+6 second r1+7 decisecond r1+8 undened c Example: LAT WR10; The contents of process registers will be: WR10 = undened value WR11 = year WR12 = month WR13 = day WR14 = hour WR15 = minute WR16 = second WR17 = decisecond d Note: That process register WR10 will be undened.
4.6
MFR, Move from Register

a Format: MFR r1-r2; b Function: Transfer of contents of process register r2 to process register r1. c Example:

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MFR WR3-WR2; The contents of process register WR2 are transferred to process register WR3.
4.7
MFRE, Move from Register Extended

a Format: MFRE r1-r2/vlm; b Function: A variable within process register r2 which is indicated by vlm is fetched and stored right-justied in process register r1. The bits in r1 which are not affected are cleared to zero. c Example: MFRE WR3-WR4/C2; Character 2 within process register WR4 is stored right-justied in process register WR3, see the gure below. C3 WR3 C2 C1 C0
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 >
WR4
0 0 1 1 1 0 1 0 0 1 0 0 0 0 1 0
4.8
MTR, Move To Register

a Format: MTR r1/vlm-r2; b Function: The vl right-hand bits in process register r2 are transferred to a variable in process register r1. The position of the variable within r1 is indicated by vlm. Bits in r1 which are not affected are not changed. c Example: MTR WR1/C2-WR2; The four right-hand bits in process register WR2 are transferred to character 2 in process register WR1. See the gure below.

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C3 WR1
C2
C1
C0
0 0 1 1 1 0 1 0 0 1 0 0 0 0 1 0
<
WR2
0 1 0 0 1 1 1 1 0 1 0 1 1 0 1 0
a Only the 4 least signicant bits in WR2 in the example will be transferred to process register WR1.
4.9
TNB , Translate Number to Bit vector

a Format: TNB r1-r2; b Function: A numeral is fetched from bit 0-4 of register r2. The bit in r1 with that number is set. All other bits in r1 are cleared. c Example: TNB WR7-AR1; register before: WR7=H22FF, AR1=H3401 register after: WR7=H0002, AR1=H3401 Since AR1 B0-B3 have the value 1, B1 is set in WR.
4.10
CFID, Clear Forlopp Identity

a Format: CFID ; b Function: The forlopp identity register (EXECFID) is cleared.CFID is intended to be used by the operating system when the EXECFID register is to be cleared. c Example: CFID ;

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The contents of register EXECFID is cleared.
4.11
TFID, Test Forlopp Identity

a Format: TFID var; b Function: A check is done that the forlopp indentity (FID) which is stored in variable var is the same as in register EXECFID. If it is not, a check is done if the FORLOPP identities are joined (join information is fetched from variables in the FORLOPP changes). If the FORLOPP identities are NOT joined software recovery actions will be taken.TFID is intended to be used directly after ENTER statements in order to insure that received signals are part of the current forlopp. c Example: TFID COMMANDFID; If the contents of variable COMMANDFID and register EXECFID are identical, then normal program execution will continue. If they are not, and they are not joined, software recovery actions will be taken. That is signal PROGERROR will be sent on priority level TRL and the current job may possibly be aborted.
5
5.1
Arithmetic Instructions
AR, Add Register to Register
a Format: AR r1-r2; b Function: The contents of process register r2/W0 are added to the contents of process register r1/W0. If the result of the addition can be contained in r1/W0, result indicator RIR is set to zero. If the result requires a larger eld length, carry is obtained and RIR is then set to one. The result is stored right-justied in register r1/W0. If the result cannot be contained in the register it will be truncated from the left. c Example: AR AR0-AR1;

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The contents of process register AR1/W0 are added to the contents of process register AR0/W0.
5.2
ARD, Add Register to Register Double

a Format: ARD r1-r2; b Function: The contents of process register r2 is added to the contents of process register r1. If the result of the addition can be contained in r1, result indicator RIR is set to zero. If the result requires a larger eld length, carry is obtained and RIR is then set to one. The result is stored right-justied in register r1. If the result cannot be contained in the register it will be truncated from the left. c Example: ARD AR0-AR1; The contents of process register AR1 are added to the contents of process register AR0.
5.3
ACC, Add Character Constant To Register

a Format: ACC r-c; b Function: Program constant c is added to the contents of process register r/W0. r/W1 is set to zero. If the result of the addition can be contained in register r/W0, result indicator RIR is cleared to zero. If, on the other hand, the result requires a larger eld length, carry occurs and RIR is then set to one. The result is stored right-justied in register r/W0. If the result has a larger eld length in r/W0, the result is truncated from the left. c Example: ACC AR0-3; The number 3 is added to the contents of process register AR0/W0.

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5.4
AWC, Add Word Constant to register

a Format: AWC r-w; b Function: Program constant w is added to the contents of process register r/W0. If the result of the addition can be contained in r/W0, result indicator RIR is reset to zero. If the result requires a larger eld length, carry occurs and RIR is set to one. The result is stored right-justied in register r. The 16 most signicant bits are cleared. c Example: AWC AR0-65535; Number 65535 is added to the contents of process register AR0/W0.
5.5
AWCD, Add Word Constant To Register Double

a Format: AWCD r-w; b Function: Program constant w is added to the contents of process register r. If the result of the addition can be contained in register r, result indicator RIR is cleared to zero. If, on the other hand, the result requires a larger eld length, carry occurs and RIR is then set to one. The result is stored right-justied in register r. If the result has a larger eld length in r, the result is truncated from the left. c Example: AWCD AR0-3; The number 3 is added to the contents of process register AR0. 32 bits are affected.
5.6
AHCS, Add Halfword Constant To Store

a Format: AHCS var-h;

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Function: The program constant h is added to a variable var in the store. The instruction is carried out correctly for variables with a maximum eld length of 32 bits. If the variable should have a size exceeding 32 bits, only the 32 least signicant bits of the variable participate in the addition. If the result of the addition can be contained in the variable or in the 32 least signicant bits of the variable, result indicator RIR is cleared to zero. The result is stored right-justied in the variable. If, on the other hand, the result cannot be contained in the variable, carry will occur, in which case RIR is set to one. The result is truncated from the left with a number of bits which cannot be contained in the variable.
Example: AHCS COUNT-136; The number 136 is added to the variable COUNT.
Implementation: The assembler instruction AHCS generates one of the machine operations AHCSU or AHCSL. AHCSU will be generated if the base address of var is 1-255, else AHCSL will be generated.
5.7
SR, Subtract Register from Register

a Format: SR r1-r2; b Function: The contents of process register r2/W0 is subtracted from the contents of process register r1/W0. If the result of the subtraction is greater than or equal to 0, result indicator RIR is cleared to zero. If, on the other hand, the result is smaller than 0, carry will occur and RIR is then set to one. Note that the machine only processes positive integers. A negative result is stored in the form of the two-complement to the numeric value of the result. c Example: SR AR1-AR2; The contents of process register AR2 are subtracted from the contents of process register AR1.

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5.8
SRD, Subtract Register from Register Double

a Format: SRD r1-r2; b Function: The contents of process register r2 is subtracted from the contents of process register r1. If the result of the subtraction is greater than or equal to zero, the result indicator RIR is reset to zero.If, on the other hand, the result is smaller than zero, carry occurs and RIR is set to one. Note that the machine only processes positive integers. A negative result is stored in the form of the two-complement to the numeric value of the result. c Example: SRD AR1-AR2; The contents of process register AR2 are subtracted from the contents of process register AR1.
5.9
SCC, Subtract Character Constant from Register

a Format: SCC r-c; b Function: Program constant c is subtracted from the contents of process register r/W0. r/W1 is set to zero. If the result of the subtraction is greater than or equal to 0, result indicator RIR is cleared to zero. If, on the other hand, the result is smaller than 0 carry will occur and RIR is then set to one. Note that the machine only processes positive integers. A negative result is stored in the form of the two-complement to the numeric value of the result. c Example: SCC AR1-5; The number 5 is subtracted from the contents of process register AR1/W0.

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5.10
SWC, Subtract Word Constant from Register

a Format: SWC r-w; b Function: Program constant w is subtracted from the contents of process register r/W0. If the result of the subtraction is greater than or equal to 0, result indicator RIR is reset to zero. If, on the other hand, the result is smaller than 0, carry occurs and RIR is set to one. The 16 most signicant bits are cleared. Note that the machine only processes positive integers. A negative result is stored in the form of the two-complement to the numeric value of the result with the 16 most signicant bits cleared. c Example: SWC AR1-5; Number 5 is subtracted from the contents of process register AR1/W0.
5.11
SWCD, Subtract Word Constant from Register Double

a Format: SWCD r-w; b Function: Program constant w is subtracted from the contents of process register r. If the result of the subtraction is greater than or equal to 0, result indicator RIR is cleared to zero. If, on the other hand, the result is smaller than 0 carry will occur and RIR is then set to one. Note that the machine only processes positive integers. A negative result is stored in the form of the two-complement to the numeric value of the result. c Example: SWCD AR1-5;

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The number 5 is subtracted from the contents of process register AR1. 32 bits are affected.
5.12
SHCS, Subtract Halfword Constant from Store

a Format: SHCS var-h; b Function: Program constant h is subtracted from a variable var in the store. The instruction is carried out correctly for variables with the maximum eld length of 32 bits. If the variable should have a size exceeding 32 bits, only the 32 least signicant bits of the variable participate in the subtraction. If the result of the subtraction is greater than or equal to 0, result indicator RIR is cleared to zero. If, on the other hand, the result is smaller than 0, carry will occur and RIR is then set to one. Note that the machine only processes positive integers. A negative result is stored in the form of the two-complement to the numeric value of the result. c Example: SHCS COUNT-#8B; The hexadecimal number 8B is subtracted from variable COUNT. d Implementation: The assembler instruction SHCS generates one of the machine operations SHCSU or SHCSL. SHCSU will be generated if the base address of var is 1-255, else SHCSL will be generated.
5.13
MR, Multiply Register

a Format: MR r1-r2; b Function: The contents of process registers r1/W0 and r1+1/W0 are regarded as one 32-bit binary number with the most signicant bits in r1+1. The contents of process registers r2/W0 and r2+1/W0 is regarded as another 32-bit binary number with the most signicant bits in r2+1. These two numbers are

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multiplied and the 32 least signicant bits of the result are stored in r1/W0 and r1+1/W0 with the least signicant bits in r1. r1/W1 and r1+1/W1 are cleared to zero. RIR is cleared to zero if the result can be contained in 32 bits, otherwise RIR is set to one. c Example: MR AR0-AR2; The contents of process registers AR0 and AR1 are multiplied by AR2 and AR3 and the result is stored in AR0 and AR1. Note, r1 and r2 may not be temporary variables.
5.14
DR, Divide Register

a Format: DR r1-r2; b Function: The contents of process registers r1/W0 and r1+1/W0 are regarded as one 32-bit binary number with the most signicant bits in r1+1. The contents of process registers r2/W0 and r2+1/W0 is regarded as another 32-bit binary number with the most signicant bits in r2+1. The contents of r1 and r1+1 are divided by the contents of r2 and r2+1.The result is stored in r1/W0 and r1+1/W0 with the least signicant bits in r1. The remainder (modulo) is stored in r1+2/W0 and r1+3/W0 with the least signicant bits in r1+2. Bits 16-31 of r1, r1+1, r2 and r2+1 are cleared to zero.Program handling error actions are initiated at attempts to divide by zero. c Example: DR AR0-AR3; The contents of process register AR0 and AR1 are divided by the contents of register AR3 and WR0 and the result is stored in AR0 and AR1. The remainder is stored in AR2 and AR3. Note, r1 and r2 may not be temporary variables.
6
6.1
Shift and Logical Instructions

SHL, SHift Left
a Format: SHL r, z;

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Function: A shift of B15-B0 in process register r to the left the number of steps specied by program constant z. Zeroes are entered from the right. B31-B16 do not participate in the operation and are set to zero before the result is stored in r. If z has the value zero, the number of shift steps will be fetched from index register IR, character 0. RIR is set to one if any of bits shifted out from B15 is one. Otherwise RIR is reset to zero.
Example: SHL AR0, 5; The contents of process register AR0 are shifted 5 steps to the left. If the contents were H1FFF before, they become HFFE0 afterwards and RIR=1.
6.2
SHLD, SHift Left Double

a Format: SHLD r, x; b Function: A shift of the contents of the process register r to the left the number of steps specied by x. Zeroes are entered from the right. If x has the value zero, the number of shift steps will be fetched from index register IR B4-B0. RIR is set to one if any of the bits shifted out is one. Otherwise RIR is reset to zero. c Example: SHLD AR1, 24; The contents of process register AR1 are shifted 24 steps to the left. If the contents of AR1 were H1FFFF before, they become HFF00 0000 afterwards and RIR=1.
6.3
SHR, SHift Right

a Format:

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SHR r, z; b Function: Shift B15-B0 in process register r to the right the number of steps specied by program constant z. Zeroes are entered from the left. B31-B16 do not participate in the operation and are set to zero before the result is stored in r. If z has the value zero, the number of shift steps will be fetched from index register IR, character 0. RIR is set to one if any of the bits shifted out from B0 is set to one. Otherwise RIR is reset to zero. c Example: SHR AR0, 3; The contents of process register AR0 are shifted 3 steps to the right. If the contents of AR0 were H1FFF before, they become H3FF afterwards and RIR=1.
6.4
SHRD, SHift Right Double

a Format: SHRD r, x; b Function: A shift of the contents of process register r to the right the number of steps specied by x. Zeroes are entered from the left. If x has the value 0, the number of shift steps will be fetched from index register IR B4-B0. RIR is set to one if any of the bits shifted out is not equal to zero. Otherwise RIR is reset to zero. c Example: SHRD AR0, 12; The contents of process register AR0 are shifted 12 steps to the right. If the contents of AR0 were H1FFF0000 before, they become H0001FFF0 afterwards and RIR=0.
6.5
ROL, ROtate Left

a Format: ROL r, z;

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Function: Rotation of B15-B0 in process register r to the left the number of steps specied by program constant z. B31-B16 do not participate in the operation and are cleared before the result is stored in r. If z has the value zero, the number of shift steps shall be fetched from index register IR, character 0. RIR is set to one if any of the bits which have been shifted out are set to one. Otherwise RIR is reset to zero.
Example: ROL AR0, 4; If AR0 = H1234 before the execution of ROL, AR0 will contain H2341 after the execution of ROL. RIR is set to one.
6.6
ROLD, ROtate Left Double

a Format: ROLD r, x; b Function: Rotation of B31-B0 in process register r to the left the number of steps specied by program constant x. If x has the value 0, the number of shift steps is specied by index register IR B4-B0. RIR is set to one if any of the bits which have been shifted out is set to one. Otherwise RIR is reset to zero. c Example: ROLD AR0, 16; If AR0 = H123400CD before the execution of ROLD, AR0 will contain H00CD1234 after the execution of ROLD. RIR is set to one.
6.7
ROR, ROtate Right

a Format: ROR r, z; b Function:

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Rotation of B15-B0 in process register r to the right the number of steps specied by program constant z. B31-B16 do not participate in the operation and are cleared before the result is stored in r. If z has the value zero, the number of shift steps shall be fetched from index register IR, character 0. RIR is set to one if any of the bits shifted out is set to one. Otherwise RIR is reset to zero. c Example: ROR AR3, 4; If AR3 = HABCD before the execution of ROR, AR3 will contain HDABC after the execution. RIR is set to one.
6.8
RORD, ROtate Right Double

a Format: RORD r, x; b Function: Rotation of B31-B0 in process register r to the right the number of steps specied by program constant x. If x has the value zero, the number of shift steps is specied by index register IR B4-B0. RIR is set to one if any of the bits shifted out is set to one. Otherwise RIR is reset to zero. c Example: RORD AR0, 8; If AR3 = H1234ABCD before RORD is executed, AR3 will contain HCD1234AB after RORD is executed. RIR is set to one.
6.9
ER, Exclusive or in Register

a Format: ER r1-r2; Exclusive OR is carried out between the contents of process registers r1 and r2 and the result is stored in r1. 32 bits are affected. Each bit of r1 is changed in accordance with the following truth table:

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r1 0 1 r2 0 1 0 1 1 0
Result indicator RIR is reset to zero if the result is zero and is set to one if the result is not zero. b Example: ER AR1-AR2; A logical exclusive OR is carried out between the contents of process registers AR1 and AR2. The result is stored in AR1.
6.10
OR, Logical Or in Register

a Format: OR r1-r2; b Function: A logical OR is carried out between the contents of process registers r1 and r2. The result is stored in r1. 32 bits are affected. Each bit of r1 is changed in accordance with the following truth table: r1 0 1 r2 0 1 0 1 1 1
The result indicator RIR is reset to zero if the result is zero and is set to one if the result is not zero. b Example: OR AR2-AR0;

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A logical OR is carried out between the contents of process registers AR2 and AR0. The result is stored in AR2.
6.11
NR, Logical and in Register

a Format: NR r1-r2; b Function: A logical AND is carried out between the contents of process registers r1 and r2. 32 bits are affected. The result is then stored in process register r1. Each bit in r1 is changed in accordance with the following truth table: r1 0 1 r2 0 1 0 0 0 1
Result indicator RIR is reset to zero if the result is zero and is set to one if the result is not zero. b Example: NR AR1-AR3; A logical AND is carried out between the contents of process registers AR1 and AR3. The result is stored in AR1.
6.12
NWC, Logical and with Word Constant

a Format: NWC r-w; b Function: A logical AND is carried out between program constant w and the contents of process register r. The result is stored in the process register. 32 bits are affected. Each bit in r is changed in accordance with the following truth table:

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r 0 1 w 0 1 0 0 0 1
Result indicator RIR is cleared if the result is zero and is set to one if the result is not zero. b Example: NWC AR3-HD4; Logical AND is carried out between hexadecimal number 00D4 and the contents of process register AR3.
Local Jump Instructions

The local jump instructions are implemented with machine operations with parameter n, which species the instruction address at program label l to which the jump is to take place. When the jump takes place, n is entered in the IAR register. In the case of condition jump instructions, if the jump is not to be executed, IAR is stepped to the next instruction. PSA remains unchanged in the case of local jumps. Comparisons in conditional jump instructions are done with 32 bits.
7.1
JLN, Jump Local Normal

a Format: JLN l; b Function: An unconditional jump is done to a program label l within the same software unit. c Example: JLN START; An unconditional jump to program label START.

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7.2
JLL, Jump Local and Link

a Format: JLL l; b Function: The address to the next instruction in sequence is saved in the link register stack. An unconditional jump is then done to a program label l within the same software unit. c Example: JLL INIT; The current program address is pushed to the link register stack and a jump is done to program label INIT.
7.3
JOR, Jump on One in Result Indicator

a Format: JOR l; b Function: If result indicator RIR has the value one, a jump is done to a program label l within the same software unit. Otherwise the execution continues with the next instruction in sequence. c Example: JOR OUT; A jump is done to program label OUT if RIR has the value one.
7.4
JZR, Jump on Zero in Result Indicator

a Format: JZR l; b Function: If result indicator RIR has the value zero, a jump is done to a program label l within the same software unit. Otherwise the execution continues with the next instruction in sequence. c Example:

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JZR in; A jump is done to program label in if RIR has the value zero.
7.5
JEC, Jump on Equality with Character Constant

a Format: JEC r, c, l; b Function: If the contents of process register r are equal to program constant c, a jump is done to a program label l within the same software unit. Otherwise the execution continues with the next instruction in sequence. c Example: JEC WR1,6, TEST; A jump is done to program label TEST if process register WR1 contains the number 6.
7.6
JUC, Jump on Unequality with Character Constant

a Format: JUC r, c, l; b Function: If the contents of process register r and program constant c have different values, a jump is done to a program label l within the same software unit. Otherwise the execution continues with the next instruction in sequence. c Example: JUC WR3, 12, OUT; A jump is done to program label OUT if process register WR3 contains any value other than the number 12.
7.7
JER, Jump on Equality between Registers

a Format: JER r, l; b Function:

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If process registers r and CR contain equal values, a jump is done to a program label l within the same software unit. Otherwise the execution continues with the next instruction in sequence. c Example: JER WR4, EQ; A jump is done to program label EQ if the contents of process registers WR4 and CR are equal.
7.8
JUR, Jump on Unequality between Registers

a Format: JUR r, l; b Function: If the contents of process registers r and CR are unequal, a jump is done to a program label l within the same software unit. Otherwise the execution continues with the next instruction in sequence. c Example: JUR WR0, UQ; A jump is done to program label UQ if the contents of process registers WR4 and CR are not equal.
7.9
JGT, Jump on Greater Than

a Format: JGT r, l; b Function: If the value of process register r is greater than the value of process register CR, a jump is done to a program label l within the same software unit. Otherwise the execution continues with the next instruction in sequence. c Example: JGT WR0, BEGIN; A jump is done to program label BEGIN if the contents of process register WR0 are greater than the contents of CR.

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7.10
JLT, Jump on Less Than

a Format: JLT r, l; b Function: If the value of process register r is less than the value of process register CR, a jump is done to a program label l within the same software unit. Otherwise the execution continues with the next instruction in sequence. c Example: JLT WR9, ROUTINE A jump is done to program label ROUTINE if the contents of process register WR9 are less than the contents of process register CR.
7.11
JTR, Jump on Table Indexed by Register

a Format: JTR r, h; b Function: A jump is done in accordance with the following jump table, in which the relevant position in the table is specied by a jump index in process register r. The instruction is accompanied by an address to an error label and then by a jump table embracing a number of jump addresses. Program constant h species the maximum jump index. The maximum value for h is equal to 255. All jump addresses are supplied by means of macro-instruction ADDR. If the contents of process register r are greater than program constant h, an error exit takes place in accordance with the address which has been stored immediately after the instruction. c Example: JTR WR6, 2;ADDR ERROR;ADDR WHEN_VAL_0;ADDR WHEN_VAL_1;ADDR WHEN_VAL_2; If process register WR6 contains the value 0, a jump takes place to program label WHEN_VAL_0. If WR6 contains the value 1, a jump takes place to program label WHEN_VAL_1.

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If WR6 contains the value 2, a jump takes place to program label WHEN_VAL_2. If WR6 contains a value greater than 2, a jump takes place to program label ERROR.
7.12
JTS, Jump on Table Indexed by Store

a Format: JTS var, h; b Function: A jump is done in accordance with the following jump table in which the relevant position in the table is specied by a jump index in variable var. The instruction is accompanied by an address to an error label and then by a jump table embracing a number of jump addresses. Program constant h species the maximum jump index. The maximum value for h is equal to 255. All jump addresses are supplied by means of macro instruction ADDR. If the contents of variable var are greater than program constant h, an error exit takes place in accordance with the address which has been stored immediately after the instruction. The variable has a maximum length of 32 bits. c Example: JTS COUNT, 2;ADDR ERROR;ADDR WHEN_VAL_0;ADDR WHEN_VAL_1;ADDR WHEN_VAL_2; If the variable COUNT contains the value 0, a jump takes place to program label WHEN_VAL_0. If COUNT contains the value 1, a jump takes place to program label WHEN_VAL_1. If COUNT contains the value 2, a jump takes place to program label WHEN_VAL_2. If COUNT contains a value greater than 2, a jump is done to program label ERROR. d Implementation: The assembler instruction JTS generates one of the machine operations JTSU or JTSL. JTSU will be generated if the base address of var is 1-255, else JTSL will be generated.

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8
8.1
Signal Transmission Instructions

SSN, Send Signal Normal
a Format: SSN sig; b Function: Signal sig is sent to a block and carries a pointer and data. Signal sending pointer (ssp) and data format (f) are specied by sig. Each transferred data is 32 bits. c Example: SSN SEIZE; Signal SEIZE is sent to the receiving block specied in the signal. The signal carries a pointer and data according to the format. d Additional information: - SSN can be used to send signals to active or passive blocks.- The global signal number (gsn) is fetched from the signal sending table (sst) of the sending block. The block number and the local signal number (lsn) of the receiver of the signal is then fetched from the global signal distribution table for unique signal (GSDT-U).- Start of execution in receiving block on address PSA + IA. PSA is fetched from the reference table of the receiving block and IA is fetched from position lsn in the signal distribution table of the receiving block.
8.2
SSIN, Send Signal Indirect Normal

a Format: SSIN r, sig; b Function: Signal sig is sent to a block carrying a pointer and data. The signal sending pointer (ssp) and data format (f) are specied by sig while the block reference is specied in register r. Each transferred data is 32 bits. c Example: SSIN WR1, SEIZE; Signal SEIZE is sent to a block. Register WR1 species the block reference. A pointer and data accompany the signal according to the format.

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Note: SSIN works the same way as SSN with the difference that the block number is calculated from the block reference stored in register r and that the local signal number (lsn) of the receiver is fetched from the global signal distribution table for multiple signals (GSDT-M). The register contents after SSIN are the same as after SSN.
8.3
SSPD, Send Signal from Process Register Direct

a Format: SSPD r; b Function: A signal is sent to a block carrying a pointer and data. The signal header information is fetched from process registers by SSPD. Receiving block is fetched from register r. Local signal number and data format are fetched from register r+1. Transmitting block number is fetched from register r+2. The pointer and the data are stored in the PR0 register and DR registers respectively before SSPD. Each transferred data is 32 bits. Input data to SSPD: 15 12 11 0 lsn 4 3 bn-r f bn-s 0 r r+1 r+2
a Example: SSPD WR7;
A signal in accordance with WR7, WR8 and WR9 is sent to the block specied in WR7. The number of data items is in accordance with the format in WR8/C0. SSPD can be used to send a signals to active or passive blocks. The instruction executes the following: - SR0 and SR1 are loaded with information. - Program execution is started in the receiving block on address PSA+IA. PSA is fetched from the reference table of the receiving block and IA is

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fetched from position LSN in the signal distribution table of the receiving block. b Note: Parameter r must not be a temporary variable.
8.4
SSL, Send Signal and Link

a Format: SSL sig; b Function: The address to the next instruction in sequence is stored together with the current block number in the link register stack. Signal sig is then sent to the destination block carrying a pointer and data. The signal sending pointer (ssp) and data format (f) are specied by sig. Each transferred data is 32 bits. c Example: SSL SEIZE; Signal SEIZE is sent with linkage to the receiver block specied in the signal. A pointer and data accompany the signal according to the format. d Implementation: As for SSN with the addition that the address to the next instruction in sequence is stored in the link register stack. The block number and instruction address are stored. e Note: No process registers (temporary variables) are saved.
8.5
SSIL, Send Signal Indirect and Link

a Format: SSIL r, sig; b Function: The address to the next instruction in sequence is stored in the link register stack together with the current block number.

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Signal sig is then sent to a block in its own processor, carrying a pointer and data. The signal sending pointer (ssp) and data format (f) are specied by sig while the block reference is specied in register r. Each transferred data is 32 bits. c Example: SSIL WR1, SEIZE; Signal SEIZE is sent to a block. Register WR1 species the block reference. A pointer and data accompany the signal in accordance with the format. d Note: No process registers (temporary variables) are saved. e Implementation: SSIL is implemented in the same way as SSL with the difference that the block number is calculated from the block reference in register r and that the local signal number (lsn) of the receiver is fetched from the global signal distribution table for multiple signals (GSDT-M).
8.6
SSPL, Send Signal from Process register Linked

a Format: SSPL r; b Function: The address to the next instruction in sequence is stored together with the current block number in the link register stack. A signal carrying a pointer and data is then sent to a block. The signal header information is fetched from process registers by SSPL. Receiving block is fetched from register r. Local signal number and data format are fetched from register r+1. Transmitting block number is fetched from register r+2. The pointer and the data are stored in the PR0 and DR registers respectively before SSPL. Each transferred data is 32 bits. c Example: SSPL WR20; A signal in accordance with WR20, WR21 and WR22 is sent with linkage to the block specied in WR20. The number of data items is in accordance with the format in WR21/C0. d Note:

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No process registers (temporary variables) are saved. e Implementation: As for SSPD with the addition that the address to the next instruction in sequence is stored in the link register stack (block number and instruction address). Note that process registers (temporary variables) are not saved.
8.7
SSB, Send Signal via Job Buffer

a Format: SSB sig; b Function: A signal message containing signal sig including pointer, data and forlopp identity, is inserted in a job buffer in own processor. The relevant job buffer (jb), signal sending pointer (ssp) and the data format (f) are specied by sig. Pointer and data are fetched from the pointer register PR0 and the data registers DR0- DR23 respectively. The forlopp identity is fetched from register EXECFID. Each transferred data is 16 bits. The current forlopp identity stored in register EXECFID is also transferred in the signal. c Example: SSB IDLE; A signal message is entered in a job buffer. The signal message contains signal IDLE with a pointer and data in accordance with the format. The signal also contains the forlopp identity of the current forlopp.
8.8
SSBD, Send Signal via Job Buffer Double

a Format: SSBD sig; b Function: A signal message containing signal sig including pointer, data and forlopp identity, is inserted in a job buffer in own processor. The relevant job buffer (jb), signal sending pointer (ssp) and the data format (f) are specied by sig. Pointer and data are fetched from the pointer register PR0 and the data registers DR0- DR23 respectively. The forlopp identity is fetched from register EXECFID. Each transferred data is 32 bits. The current forlopp identity stored in register EXECFID is also transferred in the signal. c Example: SSBD IDLE;

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A signal message is entered in a job buffer. The signal message contains signal IDLE with a pointer and data in accordance with the format. The signal also contains the forlopp identity of the current forlopp.
8.9
SSIB, Send Signal Indirect via Job Buffer

a Format: SSIB r, sig; b Function: A signal message containing signal sig including pointer, data and forlopp identity, is inserted in a job buffer in own processor. The relevant job buffer (jb), signal sending pointer (ssp) and data format (f) are specied by sig, while the block reference is specied in register r. Pointer and data are fetched from the pointer register PR0 and the data registers DR0-DR23 respectively. Each transferred data is 16bits. The current forlopp identity stored in register EXECFID is also transferred in the signal. c Example: SSIB WR3, CLEAR; A signal message is entered in a job buffer. The signal message contains signal CLEAR with a pointer and data in accordance with the format. The forlopp identity is also sent in the signal. The block reference of the receiver to the signal is fetched from register WR3. d Implementation: SSIB is implemented in the same way as SSB but with the difference that the block number is calculated from the block reference in register r.
8.10
SSIBD Send Signal Indirect via Job Buffer Double

a Format: SSIBD r, sig; b Function: A signal message containing signal sig including pointer, data and forlopp identity, is inserted in a job buffer in own processor. The relevant job buffer (jb), signal sending pointer (ssp) and data format (f) are specied by sig, while the block reference is specied in register r. Pointer and data are fetched from the pointer register PR0 and the data registers DR0-DR23 respectively. The forlopp identity is fetched from register EXECFID. Each transferred data is 32 bits. The current forlopp identity stored in register EXECFID is also transferred in the signal. c Example:

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SSIBD WR3, CLEAR; A signal message is entered in a job buffer. The signal message contains signal CLEAR with a pointer and data in accordance with the format. The forlopp identity is also sent in the signal. The block reference of the receiver to the signal is fetched from register WR3. d Implementation: SSIBD is implemented in the same way as SSBD but with the difference that the block number is calculated from the block reference in register r.
8.11
SCBS, Send Combined Backward Signal

a Format: SCBS sig; b Function: The address to the next instruction in sequence and the receiving blocks number are taken from the link register stack. Signal sig is then sent to the block in accordance with the link register stack, carrying a pointer and data. A position in SST must be occupied to be able to set the tracebit for this signal. 32 bits are transferred for each data. c Example: SCBS RET1; Signal RET1 is sent back according to a block number and instruction address which are fetched from the link register stack. d Additional information: This instruction has been introduced to permit tracing on combined backward signals. It is implemented in the same way as EP global linked return jump with the addition that a reference is done to the signal sending table. e Note: SCBS is not be generated by APS at present.
8.12
RCBS, Retrieve Combined Backward Signal

a Format:

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RCBS sig; b Function: This instruction has no operative function. It has been included to permit tracing on the reception of a combined backward signal. 32 bits are transferred for each data. c Example: RCBS RET1; The signal RET1 is received. d Note 1: A position in SDT must be occupied to be able to set the tracebit for this signal. e Note 2: RCBS is not generated by APS at present.
8.13
SSPB, Send Signal from Process Register via Job Buffer

a Format: SSPB r; b Function: A signal message with pointer and data is inserted in the job buffer indicated in register r. The entire signal message is fetched from process registers; receiving block from register r+2, local signal number and data format from register r+3, transmitting processor and block from register r+4 and the pointer and data from the PR0 register and DR registers respectively. Each transferred data is 16 bits. The current forlopp identity stored in register EXECFID is also transferred in the signal. Input data to SSPB:

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15 0 not used 0 lsn bn-r f bn-s
0 jb r r+1 r+2 r+3 r+4
a Example: SSPB WR13;
A signal in accordance with WR15, WR16 and WR17 is sent to a block (WR15). The job buffer is specied in WR13 and the number of data items in the signal is indicated by f in WR16/C0. b Note 1: Parameter r must not be a temporary variable. c Note 2: SSPB is the same assembler instruction as the older SIPBO.
8.14
SSPBD Send Signal from Process Registers via Job Buffer Double
a Format: SSPBD r; b Function: A signal message with pointer and data is inserted in the job buffer indicated in register r. The entire signal message is fetched from process registers; receiving block from register r+2, local signal number and data format from register r+3, transmitting processor and block from register r+4 and the pointer and data from the PR0 register and DR registers respectively. Register r+1 is not used. Each transferred data is 32 bits. The current forlopp identity stored in register EXECFID is also transferred in the signal. Input data to SSPBD:

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15 0 not used 0 lsn bn-r f bn-s
0 jb r r+1 r+2 r+3 r+4
a Example: SSPBD WR13;
A signal in accordance with WR15, WR16 and WR17 is sent to a block (WR15). The job buffer is specied in WR13 and the number of data items in the signal is indicated by f in WR16/C0. b Note: Parameter r must not be a temporary variable.
8.15
XSTQ, Send Signal via Time Queue

a Format: XSTQ r; b Function: A signal is entered in a central time queue for a specied time delay. The address to which the signal is sent can either be its own block or another block. Each transferred data is 32 bits. There are four time queues, TQA, TQB, TQC and TQC. TQA is an absolute time queues, the others are relative. The characteristics are: c TQA The month is specied with the gures 0-12. The day is specied with the gures 0-31. If 0 is specied for the month, the signal is delayed until the specied day, hour and minute occurs. The corresponding procedure is adopted if the day = 0. d TQB 100 ms long time intervals.

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TQC 1 s long time intervals.
TQD 60 s long time intervals. Input data for the instruction is fetched from register r and subsequent registers. TQA 15
12 11
9 8 bn-r
4 3 2 1 0 r f tq day minute jb r+1 r+2 r+3 r+4
stype=0 ssp 0 month
hour
TQB, TQC, TQD 15 12 11 stype=0 ssp 0
9 8 bn-r
4 3 1 2 0 r f tq jb r+1 r+2 r+3
number of time intervals
When XRST is used in macro the following applies:bn-r is zero for unique signals.bn-r is not equal to zero for multiple signals. ssp is the position in the signal sending table in the block for the signal to be sent. b Example: TQINF WR0-RMWDEL, 2;LCC WR3-5;XSTQ WR0;

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Signal RMWDEL is sent via the time queue. The macro TQINF is used to load the register WR0 and onwards with required data. Signal RMWDEL is sent with a delay of 5 to 6 seconds. The data to send in the signal is taken from the of DR-registers previously loaded. c Note 1: Parameter r must not be a temporary variable. d Note 2: Registers r, r+1 and r+2 can be loaded with the aid of macros TQINF or TQINFI. e Note 3: The delay in the relative time queues will be at least the nominal time. The maximum delay is the nominal time plus the delay unit of the time queue. E.g. a nominal delay of 5 seconds in TQC will in reality be between 5 and 6 seconds. The maximum delay is 65534 time units. f Note 4: The signal from Time Queue will be executed with a SSPB or SSPBD in block JOB.
8.16
XSTQD Send Signal via Time Queue Double

a Format: XSTQD r; b Function: A signal is entered in a central time queue for a specied time delay. The address to which the signal is sent can either be its own block or another block. Each transferred data is 32 bits. There are four time queues, TQA, TQB, TQC and TQC. TQA is an absolute time queues, the others are relative. The characteristics are: c TQA The month is specied with the gures 0-12. The day is specied with the gures 0-31. If 0 is specied for the month, the signal is delayed until the specied day, hour and minute occurs. The corresponding procedure is adopted if the day = 0. d TQB 100 ms long time intervals.

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TQC 1 s long time intervals.
TQD 60 s long time intervals. Input data for the instruction is fetched from register r and subsequent registers. TQA 15
12 11
9 8 bn-r
4 3 1 2 0 r f tq day minute jb r+1 r+2 r+3 r+4
stype=0 ssp 0 month
hour
TQB, TQC, TQD 15 12 11 stype=0 ssp 0
9 8 bn-r
4 3 1 2
0 r
f tq jb
r+1 r+2 r+3
number of time intervals
When XRST is used in macro the following applies:bn-r is zero for unique signals.bn-r is not equal to zero for multiple signals. ssp is the position in the signal sending table in the block for the signal to be sent. b Note 1: Parameter r must not be a temporary variable. c Note 2:

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Registers r, r+1 and r+2 can be loaded with the aid of macros TQINF or TQINFI. d Note 3: The delay in the relative time queues will be at least the nominal time. The maximum delay is the nominal time plus the delay unit of the time queue. E.g. a nominal delay of 5 seconds in TQC will in reality be between 5 and 6 seconds.
8.17
SSRP, Send Signal to RP

a Format: SSRP var, f, c, r; b Function: This instruction is used for transmitting signals from central to regional device programs included in the same function block. A signal number is specied in process register r. Pointer register PR0 contains the relevant device pointer. Variable var is the distributed RP-table which contains the RP-address and CM-address. If E-bit=1 in distributed RP-table, the RP-table has a second word which contains CME (E=1 indicates signal to EMG). The number of devices per CM is specied by 2exp(c), i.e. c shall have the value 2log(number of devices per CM). Data accompanies the signal according to format f. The data is fetched from the DR-registers and a maximum of 12 data words with a maximum of 8 bits each may be transmitted. c Example: SSRP RPTAB, 4, 2, AR0; A signal with the number specied in AR0 is sent to a device program in RP. The internal address within the RP and the RP-number will be calculated from the contents of PR0 and the distributed RP-table RPTAB. Pointer and four 8-bit data will be sent. There are four devices on each CM. 15 cm-addr 11 10 B E 9 8 7 RP address CME 0

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a B indicates if the CM/RP is blocked. var is addressed with bit c-15of PR0 as a pointer. (c = parameter c). b Note 1: If the RP is blocked, the operating system will take over control. c Implementation: The assembler instruction SSRP generates one of the machine operations SSRPU or SSRPL. SSRPU will be generated if the base address of var is 1-255, else SSRPL will be generated.
8.18
SSRPE Send Signal TO RP Extended

a Format: SSRPE var, f, c, r; b Function: This instruction is used for transmitting signals from central to regional device programs included in the same function block. A signal number is specied in process register r. Pointer register PR0 contains the relevant device pointer. Variable var is the distributed RP-table which contains the RP-address and CM-address. If E-bit=1 in distributed RP-table, the RP-table has a second word which contains CME (E=1 indicates signal to EMG). The number of devices per CM is specied by 2exp(c), i.e. c shall have the value 2log(number of devices per CM). Data accompanies the signal according to format f. The data is fetched from the DR-registers and a maximum of 48 data words with a maximum of 8 bits each may be transmitted. The data are fetched from DR-registers with two bytes in each register. The rst data is in DR0/H0, the second in DR0/H1, the third in DR1/H0 and so forth. c Example: SSRPE RPTAB,10,2,AR0; A signal with the number specied in AR0 is sent to a device program in RP. The internal address within the RP and the RP-number will be calculated from the contents of PR0 and the distributed RP-table RPTAB. Pointer and 32, 8-bit data will be sent. There are four devices on each CM.

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15 cm-addr
11 10 B E
7 RP address CME
B indicates if the CM/RP is blocked. var is addressed with PR0/2exp(c) as a pointer. (c = parameter c). b Note 1: If the RP is blocked, the operating system will take over control. c Note 2: All RP:s can not handle long RP signals. d Implementation: The assembler instruction SSRPE generates one of the machine operations SSRPEU or SSRPEL. SSRPEU will be generated if the base address of var is 1-255, else SSRPEL will be generated.
8.19
SSIP, Send Signal to IPNA

a Format: SSIP var, f, r; b Function: This instruction is used for transmitting signals from central software to software on IPNA included in the same function block. The destination (Logical IPNA Address plus IPNASUP) of the signal is specied by the variable var (the content of which is provided by the O&M owner of IPNA). Pointer register PR0 is used for addressing of variable var. The signal number is specied by register r. The register also species type and priority of the signal. If the type states that a CB/DB is included in the signal, the registers r+1-r+4 will specify the buffer. Data in the buffer are packed bytes, meaning that the data length of the variables in the buffer is 8 bits (byte) and two bytes are packed in a 16 bits word. Both, start index and number of data can be odd or even.

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Data according to format f will be sent with the signal. If a CB/DB is included in the data, rst signal (including the buffer description in r+1-r+4) will be sent to IPNA, then the CB/DB will be sent with softDMA signals to IPNA. 16 bits of data is transferred from each DR register. Note: After a block has sent one signal with CB/DB to IPNA, the same block cannot send the next signal with CB/DB to IPNA on the same priority level until the rst one has been acknowledged. For signals without CB/DB there are no such restriction. Different CP blocks can simultaneously send signals with CB/DB to the same IPNA. Data Structure:
Variable 'var' 15 8 IPNASUP 7 1 0
Logical IPNA address
Logical IPNA address = Bit 0 Subaddress (A/B side) Bit 7-1 Logical IPNA number IPNASUP = IPNA Software Unit Pointer Logical IPNA number = (31 - Logical RPHB address) Registers r, r+1, ..., r+4: 15 14 r r+1 r+2 r+3 r+4 P 11 Type 8 7 Signal Number 0
Number of buffered data / Data Buffer pointer LSW / Data Buffer pointer MSW / Data
Type
Start index in buffer / Data
= 0 1 P(Priority) = 0 1
No DB/CB included DB/CB included Normal High

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8.20
SSIPD, Send Signal to IPNA Double

a Format: SSIPD var, f, r; b Function: This instruction is used for transmitting signals from central software to software on IPNA included in the same function block. The destination (Logical IPNA Address plus IPNASUP) of the signal is specied by the variable var (the content of which is provided by the O&M owner of IPNA). Pointer register PR0 is used for addressing of variable var. The signal number is specied by register r. The register also species type and priority of the signal. If the type states that a CB/DB is included in the signal, the registers r+1-r+4 will specify the buffer. Data in the buffer are packed bytes, meaning that the data length of the variables in the buffer is 8 bits (byte) and two bytes are packed in a 16 bits word. Both, start index and number of data can be odd or even. Data according to format f will be sent with the signal. If a CB/DB is included in the data, rst signal (including the buffer description in r+1-r+4) will be sent to IPNA, then the CB/DB will be sent with softDMA signals to IPNA. 32 bits of data is transferred from each DR register. Note: After a block has sent one signal with CB/DB to IPNA, the same block cannot send the next signal with CB/DB to IPNA on the same priority level until the rst one has been acknowledged. For signals without CB/DB there are no such restriction. Different CP blocks can simultaneously send signals with CB/DB to the same IPNA. Data Structure:

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Variable 'var' 15 8 IPNASUP 7 1 0
Logical IPNA address
Logical IPNA address = Bit 0 Subaddress (A/B side) Bit 7-1 Logical IPNA number IPNASUP = IPNA Software Unit Pointer Logical IPNA number = (31 - Logical RPHB address) Registers r, r+1, ..., r+4: 15 14 r r+1 r+2 r+3 r+4 P 11 Type 8 7 Signal Number 0
Number of buffered data / Data Buffer pointer LSW / Data Buffer pointer MSW / Data
Type
Start index in buffer / Data
= 0 1 P(Priority) = 0 1
No DB/CB included DB/CB included Normal High
8.21
XRST, Read from Signal Sending Table

a Format: XRST r-sig,b; b Function: Transfer of signal sending pointer (ssp) or block number from the Global Sending Distribution Table (GSDT-U) to processor register.If b=0 r is loaded with ssp.If b=1 and the signal type is unique r is loaded with BN-R, otherwise zero is loaded. The instruction forms the input data in register r and r+1 to XSTQ (XSTQD) and the instruction is normally included in the macro TQINF (TQINFI). c Example:

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XRST WRO-SEIZE,1; If signal SEIZE is a unique signal the BN-R for signal SEIZE is read from GSDT-U and stored in register WRO.
8.22
RBD, Receive Bulk Data

a Format: RBD c,r; b Function: This Instruction is used for reception of Bulk Data from RP. The Parameter c species the size of the Communication Buffer that the Bulk Data is copied to. Value of c: 1 2 3 4 5 6 7 8 9 10 11 Size of the Communication Buffer in W16 32 64 128 256 512 1024 2048 4096 8192 16384 32768
The parameter r species the register which contains the pointer to the Communication Buffer where the Bulk Data is stored. The instruction RBD must only be located at the signal entry of the RP-CP signal, directly after the RECEIVE signal, a PROGERROR will be issued if the instruction is found elsewhere. The SDT (Signal Distribution Table) is scanned for Bulk Data signals at Load-Time (Function Change, etc) for Bulk Data signals. The size information is collected and stored In the APZ System tables. The size information is later used at the reception of the Bulk Data signal to allocate a Communication Buffer with the appropriate size where the Bulk Data is copied to.

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Example: RECEIVE BULKSIG; RBD 5, WR9; The signal BULKSIG is received with ordinary signal data registers and bulk data. The pointer to the Communication Buffer where the bulk data is stored is found in the register WR9. The size of the Communication Buffer is 512 W16.
Implementation: This instruction is only available on APZ 212 40 and later.
Note: It is not recommended to use this instruction in a correction.
8.23
SSRPB, Send Bulk Signal to RP

a Format: SSRPB var, f, c, b, r; b Function: This instruction is used for transmitting signals from central to regional device programs included in the same function block using the RPB-E bus. A signal number is specied in process register r. The Pointer register PR0 contains the relevant device pointer. Variable var is the distributed RP-table, which contains the RP-address and CM-address. The register r+1 species the pointer to the Communication Buffer which content will be (fully/partly) transferred to the RP. The compare register CR contains the number of W16 words that must be sent. If the b-bit is set to one only the least signicant W8 of each word of the Communication Buffer is sent, else if b-bit is zero W16 of each word of the Communication Buffer is sent. If CR is zero no bulk data will be sent in the signal. If CR is non-zero and r+1 does not contain a valid Communication Buffer (r+1=0) a PROGERROR occurs. The index register IR contains the index to the rst W16 of the Communication Buffer to be sent.

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A PROGERROR occurs if the content of the index register IR added to the content of CR is greater than the physical size of the Communication Buffer specied by r+1. The E-bit in the distributed RP-table must always be 0 for bulk data signals; a PROGERROR will be issued otherwise. The number of devices per CM is specied by: 2exp(c), i.e. c shall have the value 2log(number of devices per CM). Data accompanies the signal according to format f. The data is fetched from the DR-registers and a maximum of 16 data words with a maximum of 16 bits each may be transmitted. Note: Temporary variable may not be specied instead of r. c Example: SSRPB RPTAB, 4, 2, 0, AR0; A signal with the number specied in AR0 is sent to a device program in RP. The internal address within the RP and the RP-number will be calculated from the contents of PR0 and the distributed RP-table RPTAB. Pointer and four 16-bit data will be sent. There are four devices on each CM. RPTAB 15 cm-addr 11 10 B E 9 8 7 RP address CME 0
B indicates if the CM/RP is blocked. var is addressed with bit c-15 of PR0 as a pointer. (c = parameter c). The Communication Buffer pointed out by AR1 is transferred to the RP starting at IR and CR number of W16 words. d e f Implementation: This instruction is only available on APZ 212 40 and later. Note1: If the RP is blocked, the operating system will take over control. Note2: The ownership of the Communication Buffer pointer is transferred to APZ at this instruction.

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9
9.1
Miscellaneous Instructions
EP, End of Program
a Format: EP; b Function: The EP is used at the following events: - local linked return - combined backward signal - concluding of a job on TRL, THL1, THL2, THL3, BAL1 or BAL2 level. c Implementation: The function of the EP-instruction, is controlled by the contents of the top position of the link register stack (LR): - if BN of LR is equal to the block number of current block a local linked return is performed or a combined backward signal within the block is sent. The program execution will then continue in this block at address according to IA value from LR. - if BN of LR differs from the block number of current block and is not equal to zero, a combined backward signal is sent to this other block. This means that the program execution will continue at address according IA value from LR in the new block. - If BN of LR is equal to zero the current job will be concluded. The continued execution is then controlled in the following way: -- If the concluded job was a TRL-job, a return to the interrupted level with highest priority is executed -- If the concluded job was a job table job (THL1), the job table search will continue if the whole job table has not been searched. If the search is nished a job on THL2 or THL3 is started if there is any waiting, else a return to interrupted job on BAL is executed. -- If the concluded job was a THL2 or a THL3 job, a new THL job is started if there is any waiting, else a return to interrupted job on BAL is executed. -- was the concluded job a BAL1 or a BAL2 job, a new BAL job is started if there is any waiting. d Note:

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When a return to interrupted job is to be performed but there is no interrupted job or when a BAL job is concluded without any new BAL job to start, then an idle-loop is entered.
9.2
SRT , Set Return Time

a Format: SRT w; b Function: A time is set in the job table. This instruction is used in programs which are called from a job table. The instruction sets the counter word of the job table = w. If parameter w = 0, the value is fetched from IR. c Example: SRT 496; The program is called from the job table after 496 primary intervals, i.e. 4960 ms. d Note: SRT must be executed in each job table job before it is ended with instruction EP. If not, software recovery actions are taken.
10
10.1
Search Instructions
BLO, Bit search for Leftmost One in Register
a Format: BLO r, c, l; b Function: A search for a bit set to one from left to right in process register r. The search starts at the bit position specied by character constant c and continues with the next lower signicant bit position. The search is concluded when a bit set to one is encountered or when bit position 0 has been searched. If c = 0, index register IR character 0 indicates where the search is to begin. If a bit set to one is encountered, it is cleared to zero and a bit address is stored right-justied in index register IR. IR is cleared to zero before the storage operation is carried out. A jump is then done to program label l.

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If no bit set to one is encountered, the execution continues with the next instruction in sequence. Index register IR is not affected. c Example: BLO WR2, 9, CONT; A bit set to one is sought from and including bit position 9 in process register WR2. If, for example, WR2 contains the number = H1050, an exit is done to program label CONT with value 6 in IR and H1010 in WR2.
10.2
BLOD, Bit search for Leftmost One in Register Double

a Format: BLOD r, o, l; b Function: As BLO except that bits 16-31 can also be searched. c Example: BLOD WR2, 11, CONT; A bit set to one is sought from and including bit position 31 in process register WR2. If, for example, WR2 contains the number = H1050, an exit is done to program label CONT with value 6 in IR and H1010 in WR2.
10.3
CS, Compare String

a Format: CS var1, r1, var2, r2; b Function: Two strings stored in string variables var1 and var2 are compared. The instruction will search through the strings in var1 and var2 character by character starting at the rst character.The string variables var1 and var2 can both be part of a record. In that case the different pointers are stored in r1 (pointer of variable var1) and in r2 (pointer of variable var2).The result of the comparison is after the instruction found in process register CR according to: - CR = 0 if the string in var1 is less than the string in var2. - CR = 1 if the string in var1 is equal to the string in var2, i.e. if the strings have the same number of characters and all characters are equal. CR = 2 if the string in var1 is larger than the string in var2.

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Example: CS STR1, WR9, STR2, WR10; The two string variables STR1 and STR2 will be compared. If the are stored in a RECORD then WR9 indicates the actual pointer value for STR1 and WR10 indicates the pointer value for STR2. The result of the comparison is found in the CR register.
Note: The comparison between var1 and var2 will be strictly numerical and the micro program will not perform any check whether the compared 8-bit numbers are valid ASCII characters.
10.4
FESR, File search for Equality between Store and Register

a Format: FESR var, l; b Function: To search for similarity between variables and the contents of comparison register CR. The variables belong to the variable block var and have to be addressed by pointer. The search starts with the variable specied by the start pointer value in process register PR0 reduced by 1. The search continues with the next variables with lower pointer values, where upon PR0 is decremented. If the search condition is met, the relevant pointer value is stored in PR0 and a jump takes place to program label l. When the variable which is indicated by PR1 has been scanned without meeting the search condition, the search is concluded and PRO is set equal to PR1. The program then continues with the next instruction in sequence. If PR0 is less than or equal to PR1 from the beginning, the program continues with the next instruction in sequence with unchanged pointer values. c Example: FESR FAELT, INIT; A variable with a value specied in comparison register CR is sought in variable block FAELT. If the value is found, a jump takes place to program label INIT. d Note 1:

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The instruction cannot be used for variables larger than 32 bits or for subvariables or indexed variables. e Note 2: The instruction can be interrupted. This means that the instruction can be temporarily concluded if, for example, a maintenance interrupt signal arrives during the execution of the instruction. When the interrupt sequence has been concluded, the execution of the instruction continues. f Implementation: The assembler instruction FESR generates one of the machine operations FESRU or FESRL. FESRU will be generated if the base address of var is 1-255, else FESRL will be generated.
10.5
FCZS, File search for Change to Zero in Store

a Format: FCZS var, l; b Function: An array of counters in the data store is run through and each counter is decremented by 1. When a counter reaches zero, an exit takes place to label l. Counters whose initial value are zero will not be decremented and in this case the run through shall continue with the next counter unconditionally. Each counter is contained in a variable, addressed by a pointer, in variable block var. The search begins with the variable specied by the start pointer value in process register PR0 reduced by 1. The search continues with the next variables with lower pointer values, where upon PR0 is decremented. If the search condition is met, the relevant pointer value is stored in PR0 and a jump takes place to program label l. When the variable which is indicated by PR1 has been searched without the search condition having been met, the search is concluded and PR0 is set equal to PR1. The program then continues with the next instruction in sequence. If PR0 is less than or equal to PR1 from the beginning, the program continues with the next instruction in sequence with unchanged pointer values. c Example: FCZS IDLE, FOUND;

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Counters in variable block IDLE are run through and each counter is decremented by 1. If any counter is decremented to 0, a jump is done to program label FOUND. d Note 1: The instruction cannot be used for variables larger than 32 bits or subvariables. Unlike FESR, the instruction can be used for indexed variables. e Note 2: No tracing on variables can take place. f Note 3: The instruction can be interrupted. This means that the instruction can be temporarily concluded if, for example, a maintenance interrupt signal arrives during the execution of the instruction. When the interrupt sequence has been concluded, the execution of the instruction continues. g Implementation: The assembler instruction FCZS generates one of the machine operations FCZSU or FCZSL. FCZS will be generated if the base address of var is 1-255, else FCZSL will be generated.
11
Macro Instructions
A macro instruction is a statement which is available to the assembler programmer in source code and which generates assembler instructions.
11.1
ADDR, Load Dened Address

a Format: ADDR l; b Function: The address to program label l within the same program unit will be generated in binary form and with a eld length of 16 bits. Instruction ADDR is mainly used in combination with instructions JTS and JTR. c Example: ADDR START;

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The address to program label START will be included in the sequence of instructions when loading the program unit to the program store. d Code generation: 16-bit binary value
11.2
BLNR, Load Block Reference Number

a Format: BLNR r-blnm; b IMPORTANT: MUST NOT BE USED IN ASSEMBLER PROGRAMS c Function: Reference of own block is loaded in register r. The reference is composed from own block number according to the gure. 15 8 bn bit 0-7 0 3 0 b: 8-11
a Note:
APS does not use the blnm parameter. Own (current) block number is always used. b Example: BLNR WR2-RC; If own block number is H394 WR2 will contain the value H9403 when BLNR is executed, whether own block is RC or not. c Code generation: XRBN r;ROL r, 8;
11.3
DUPL, Duplicate Instruction

a Format: DUPL w; b Function:

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The next instruction in sequence is repeated w times. c Note: If the instruction after DUPL is a macro instruction, only the last instruction in the macros code generation is repeated. d Example: DUPL 3;XSTP H10FF; The generated assembler instructions will be follows: XSTP H10FF; XSTP H10FF; XSTP H10FF;
11.4
ERD, Exclusive or in Register

a Format: ERD r1-r2; Exclusive OR is done between the contents of process registers r1 and r2 and the result is stored in r1. b Example: ERD AR1-AR2; An exclusive OR is done between the contents of process registers AR1 and AR2. The result is stored in AR1. c Code generation: ER r1, r2;
11.5
JECD, Jump on Eq with Char Constant Double

a Format: JECD r, c, l; b Function: If the contents of process register r are equal to program constant c, a jump is done to a program label l. c Example:

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JECD WR1, 6, TEST; A jump is done to program label TEST if process register WR1 contains the number 6. d Code generation: JEC r, c, l;
11.6
JERD, Jump on Equality between Register Double

a Format: JERD r, l; b Function: If process registers r and CR contain equal values, a jump is done to a program label l. c Example: JERD WR4, EQ; The jump is done to program label EQ is the contents of process registers WR4 and CR are equal. d Code generation: JER r, l;
11.7
JGETD Jump on Greater Than or Equal Double

a Format: JGETD r, l; b Function: If the value in process register r is greater than or equal to the value in process register CR, a jump is done to a program label l. c Example: JGETD WR5, END; A jump is done to program label END if the contents of process register WR5 are greater than or equal to the contents of CR. d Code generation: JGET r, l;

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11.8
JGTD, Jump on Greater Than Double

a Format: JGTD r, l; b Function: If the value of process register r is greater than the value of process register CR, a jump is made to a program label l. c Example: JGTD WR0, BEGIN; A jump is done to program label BEGIN if the contents of process register WR0 are greater than the contents of CR. d Code generation: JGT r, l;
11.9
JLETD Jump on Less Than or Equal Double

a Format: JLETD r, l; b Function: If the value in process register r is less than or equal to the value in process register CR, a jump is done to a program label l. c Example: JLETD WR0, PASS; A jump is done to program label PASS if the contents of process register WR0 are less than or equal to the contents of CR. d Code generation: JLET r, l;
11.10
JLTD, Jump on Less Than Double

a Format: JLTD r, l; b Function:

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If the value of process register r is less than the value of process register CR, a jump is made to a program label l. c Example: JLTD WR9, ROUTINE; A jump is done to program label ROUTINE if the contents of process register WR9 are less than the contents of process register CR. d Code generation: JLT r, l;
11.11
JUCD, Jump on Unequality with Char Const Double

a Format: JUCD r, c, l; b Function: If the contents of process register r and program constant c have different values, a jump is done to a program label l. c Example: JUCD WR3, 12, OUT; A jump is done to program label OUT if process register WR3 contains any value other than the number 12. d Code generation: JUC r, c, l;
11.12
JURD, Jump on Unequality between Register Double

a Format: JURD r, l; b Function: If the contents of process register r and CR are unequal, a jump is done to a program label l. c Example: JURD WR0, UQ;

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A jump is done to program label UQ if the contents of process register WR0 and CR are unequal. d Code generation: JUR r, l;
11.13
LBNBA Load Base Address Number

a Format: LBNBA r-var; b Function: Register r is allocated the base address number for specied variable block. c Code generation: LHC r/W0-base address bit 0-7;LHC r/H1-base address bit 8-11; d Note: Early APS versions generated:LHC r/H0-base address bit 0-7;LHC r/H1-base address bit 8-11;
11.14
LBNSL, Load Signal Location

a Format: LBNSL r-sig; b Function: Register r is allocated the signal number of the signal sig in the signal distribution table of the receiving block (=own block). c Code generation: LHC r/W0-signal number bit 0-7;LHC r/H1-signal number bit 8-11; d Note: Early APS versions generated:LHC r/H0-signal number bit 0-7;LHC r/H1-signal number bit 8-11;
11.15
LCCE, Load Character Constant Extended

a Format: LCCE r/vlm-c;

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Function: Character constant c is transferred to a variable in process register r. The length and position of the variable within the register are specied by vlm.
Code generation: LHCE r/vlm-h;
11.16
LWC, Load Word Constant

a Format: LWC r-w; b Function: Word constant w is transferred to process register r. c Example: LWC WR6-1025; Numeric value 1025 is stored in process register WR6. d Code generation: LHC r/W0-w/b0-7;LHC r/H1-w/b8-15;
11.17
NHC, Logical aNd with Halfword Constant

a Format: NHC r-h; b Function: A logical AND is carried out between program constant h and the contents of process register r. The result is stored in the process register.32 bits are affected. Each bit in r is changed in accordance with the following truth table: r 0 1 h 0 1 0 0 0 1

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a Result indicator RIR is cleared if the result is zero and is set to one if the result is not zero. b Example: NHC AR3-HD4; Logical AND is carried out between hexadecimal number 00D4 and the contents of process register AR3. c Code generation: NWC r-w;
11.18
RECEIVE, Receive a Signal

a Format: RECEIVE sig; b Function: The label for receiving a signal is specied with the aid of RECEIVE. c Example: RECEIVE SEIZE; The location of the statement species the relevant address for receiving signal SEIZE. d Code generation: No code, only a denition of the entry label.
11.19
SGLOC Signal Group Location

a Format: SGLOC r-sgn; b Function: Process register r is allocated a signal group position in own blocks signal distribution table. sgn species the signal group name. c Code generation: LHC r/W0-signal group pos bit 0-7LHC r/H1-signal group pos bit 8-11

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Note: Early APS versions generated:LHC r/H0-signal group pos bit 0-7;LHC r/H1-signal group pos bit 8-11;
11.20
SSLL, Send Signal Local and Link

a Format: SSLL sig; b Function: The address to the next instruction in sequence is saved in the link register stack. An unconditional jump is then made to the program label within the same program unit as that dened by signal name sig. c Example: SSLL OK; Signal OK is sent within the program unit. The return address is stored in the link register stack. d Code generation: JLL n; n species the instruction address to the program label to which the jump is to be made.
11.21
SSLN, Send Signal Local Normal

a Format: SSLN sig; b Function: An unconditional jump is done to the program label within the same program unit which is dened by the signal name sig. c Example: SSLN READY; Signal READY is sent within the program unit. d Code generation: JLN n;

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n species the instruction address to the program label to which the jump is to take place.
11.22
TQINF Time Queue Information

a Format: TQINF r-sig, tq; b Function: Allocation of block number in register r, signal number and format in register r+1 and time queue index and job buffer index in register r+2. Signal sending pointer (ssp), data format (f) and job buffer index (jb) are specied by sig. With the aid of ssp block number and signal number are read from the signal sending table of current block. The values received can, together with programmed settings of subsequent registers (see note 1) be used by any of the instructions XSTQ or XSTQD (insertion of signal message in central time queue). Registers r, r+1 and r+2 are allocated values in accordance with the following: 15 stype=0 sn bn-r f tq jb 0 r r r+2
a Note 1:
The subsequent registers, register r+3 and, where applicable, register r+4 shall also be set before the instruction XSTQ can be executed. In the case of time queue TQA, the month and day are allocated in register r+3 in the left-hand and right-hand half-words respectively. The hour and minute are allocated in register r+4 in the left-hand and right-hand half-words respectively. In the case of time queues TQB, TQC and TQD, a delay is specied as a multiple of 100 ms, 1 second and 1 minute respectively in register r+3. b Note 2: Parameter r must not be a temporary variable.

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11.23
TQINFI Time Queue Information Indirect

a Format: TQINFI r1-r2, sig, tq; b Function: Allocation of block number in register r1, signal number and format in register r1+1 and time queue index and job buffer index in register r1+2. Signal sending pointer (ssp), data format (f) and job buffer index (jb) are specied by sig. With the aid of ssp signal number is read from the signal sending table of current block. Block number is stated by the block reference in register r2, which must be loaded with a value before TQINFI. The values received can, together with programmed settings of subsequent registers (see note 1) be used by any of the instructions XSTQ or XSTQD (insertion of signal message in central time queue). Registers r1, r1+1 and r1+2 are allocated values in accordance with the following: 15 stype=0 sn bn-r f tq jb 0 r1 r1+1 r1+2
a Note 1:
The subsequent registers, register r1+3 and, where applicable, register r1+4, shall also be set before the instruction XSTQ can be executed. In the case of time queue TQA, the month and day are allocated in register r1+3/H1 and r1+3/H0 respecitvely. The hour and minute are allocated in register r1+4/H1 and r1+4/H0 respectively. In the case of time queues TQB, TQC and TQD the delay is specied as a multiple of 100 ms, 1 second and 1 minute respectively in register r1+3. b Note 2: Temporary variable may not be specied instead of registers.
11.24
VAL , Load Dened Value

a Format:

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VAL w; b Function: Numeric value w will be generated in binary form and with a eld length of 16 bits. Instruction VAL is used for writing machine instructions in pure machine code and for organizing tables in the program store. c Example: VAL H384B; The hexadecimal value 384B will be included in the sequence of machine operations. d Code generation: 16-bit binary code
11.25
XLLR, Load Location in Register

a Format: XLLR r-l; b Function: The address to program label l within the same program unit is transferred to process register r. c Example: XLLR WR4-TESTLCC; The relative address for TESTLCC is stored in register WR4. d Code generation: LHC r/W0-address/B0-7;LHC r/H1-address/B8-13; e Note: Early APS versions generated:LHC r/H0-address bit 0-7;LHC r/H1-address bit 8-11;

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Limited Internal DESCRIPTION

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ASA210C, General Assembler Instructions

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11.18 11.19 11.20 11.21 11.22 11.23 11.24 11.25

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The Assembler Language

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Instructions for Reading from Store

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RSE, Read from Store Extended

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RSI, Read from Store Indexed

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RSII, Read from Store Indexed Indirect

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RSS, Read Subvariable from Store

RDP, Read Dynamic Buffer Pointer

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RDB, Read from Dynamic Buffer

RDBI, Read from Dynamic Buffer Indexed

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Note 2: Parameter r1 must not be a temporary variable.

RCB, Read from Communication Buffer

RCP, Read Communication Buffer Pointer

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RFID, Read Forlopp Identity

Instructions for writing in Store

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WSE, Write in Store Extended