ASynchronous Sequential Circuits

Asynchronous Sequential Circuits
CHAPTER 4
ASYNCHRONOUS SEQUENTIAL CIRCUITS
4!
INTRO"UCTION
A sequential circuit is specified by a time sequence of inputs, outputs and internal
states. In synchronous sequential circuits, the output changes whenever a clock pulse is applied. The memory elements are clocked flip-flops. Asynchronous sequential circuits do not use clock pulses. The memory elements in asynchronous sequential circuits are either unclocked flip-flops ( atches! or time-delay elements. S No " Synchronous sequential circuits #emory elements are clocked flip-flops The change in input signals can affect $ memory element upon activation of clock signal. The ma&imum operating speed of clock % depends on time delays involved. Therefore synchronous circuits can operate slower than asynchronous. )asier to design Asynchronous sequential circuits #emory elements are either unclocked flip-flops or time delay elements. The change in input signals can affect memory element at any instant of time. 'ecause of the absence of clock, it can operate faster than synchronous circuits. #ore difficult to design
#loc$ %ia&ra' o(
Asynchronous sequential circuits
The block diagram of asynchronous sequential circuit is shown above. It consists of a combinational circuit and delay elements connected to form feedback loops. There are *n+ input variables, *m+ output variables, and *k+ internal states. The delay elements provide short term memory for the sequential circuit. The presentstate and ne&t-state variables in asynchronous sequential circuits are called secondary variables and e&citation variables, respectively. ,hen an input variable changes in value, the *y+ secondary variable does not change instantaneously. It takes a certain amount of time for the signal to propagate from the input terminals through the combinational circuit to the *-+ e&citation variables where the new values are generated for the ne&t state. These values propagate through the delay elements and become the new present state for the secondary variables. In steady-state condition, e&citation and secondary variables are same, but during transition they are different. To ensure proper operation, it is necessary for asynchronous sequential circuits to attain a stable state before the input is changed to a new value. 'ecause of unequal delays in wires and combinational circuits, it is impossible to have two or more input variable change at e&actly same instant. Therefore, simultaneous changes of two or more input variables are avoided. .nly one input variable is allowed to change at any one time and the time between input changes is kept longer than the time it takes the circuit to reach stable state.
.
Ty)es* According to how input variables are to be considered, there are two types /undamental mode circuit 0ulse mode circuit.
/undamental mode circuit assumes that1 The input variables change only when the circuit is stable. .nly one input variable can change at a given time. Inputs are levels (2, "! and not pulses.
0ulse mode circuit assumes that1 The input variables are pulses (True, /alse! instead of levels. The width of the pulses is long enough for the circuit to respond to the input. The pulse width must not be so long that it is still present after the new state is reached.
4+
Analysis o( ,un%a'ental -o%e Circuits

The analysis of asynchronous sequential circuits consists of obtaining a table or a
diagram that describes the sequence of internal states and outputs as a function of changes in the input variables.
4 + ! Analysis )roce%ure
The procedure for obtaining a transition table from the given circuit diagram is as follows. ". 3etermine all feedback loops in the circuit. $. 3esignate the output of each feedback loop with variable -" and its corresponding inputs y", y$,4.yk, where k is the number of feedback loops in the circuit. %. 3erive the 'oolean functions of all -+s as a function of the e&ternal inputs and the y+s.
.
(. 0lot each - function in a map, using y variables for the rows and the e&ternal inputs for the columns. 5. 6ombine all the maps into one table showing the value of -7 -", -$,4.-k inside each square. 8. 6ircle all stable states where -7y. The resulting map is the transition table.
4 + + Pro.le's
". An asynchronous sequential circuit is described by the following e&citation and output function, Y/ 0!0+1 20!10+3 y 4/ Y a! 3raw the logic diagram of the circuit. b! 3erive the transition table, flow table and output map. c! 3escribe the behavior of the circuit. Soln* i! The logic diagram is shown as,
Lo&ic %ia&ra'
ii! y 2 2 2 2 " " " " 0! 2 2 " " 2 2 " " 0+ 2 " 2 " 2 " 2 " 0!0+ 2 2 2 " 2 2 2 " 20!10+3y 2 2 2 2 2 " " " Y/ 0!0+1 20!10+3y 2 2 2 " 2 " " " 4/ Y 2 2 2 " 2 " " "
Transition ta.le*
.
Out)ut 'a)* .utput is mapped for all stable states. /or unstable states output is mapped unspecified.
,lo5 ta.le* Assign a7 29 b7 "
iii! The circuit gives carry output of the full adder circuit. $. 3esign an asynchronous sequential circuit that has two internal states and one output. The e&citation and output function describing the circuit are as follows1 Y!/ 0!0+1 0!y+1 0+y! Y+/ 0+1 0!y!y+1 0!y! 4/ 0+1 y! a! 3raw the logic diagram of the circuit. b! 3erive the transition table, output map and flow table. Soln* i! The logic diagram is shown as,
Lo&ic "ia&ra' ii! 4/ 0+1 y! 2 " 2 " 2 " 2 " " " " " " " " " 0!y!y+ 0!0+ 0!y+ 0+y! 0!y! Y! 2 2 2 " 2 2 " " 2 " 2 " 2 " " " Y+ 2 " 2 " 2 " 2 " 2 " " " 2 " " "
y!
y+
0! 2 2 " " 2 2 " " 2 2 " " 2 2 " "
2 2 2 2 2 2 2 2 " " " " " " " "

.
2 2 2 2 " " " " 2 2 2 2 " " " "
0+ 2 " 2 " 2 " 2 " 2 " 2 " 2 " 2 "
2 2 2 " 2 2 2 " 2 2 2 " 2 2 2 "
2 2 2 2 2 2 " " 2 2 2 2 2 2 " "
2 2 2 2 2 2 2 2 2 " 2 " 2 " 2 "
2 2 2 2 2 2 2 2 2 2 2 2 2 2 " "
2 2 2 2 2 2 2 2 2 2 " " 2 2 " "
Transition ta.le an% Out)ut 'a)
Transition ta.le
Out)ut 'a)
Pri'iti6e ,lo5 ta.le
%. An asynchronous sequential circuit is described by the e&citation and output functions, Y/ 0!0+71 20!10+73 y 4/ Y a! 3raw the logic diagram of the circuit. b! 3erive the transition table, output map and flow table. Soln*
.
Lo&ic %ia&ra'
ii! Y 2 2 2 2 " " " 0! 2 2 " " 2 2 " 0+ 2 " 2 " 2 " 2 " 0+7 " 2 " 2 " 2 " 2 0!0+7 2 2 " 2 2 2 " 2 20!10+73y 2 2 2 2 " 2 " " Y/ 0!0+71 20!10+73y 2 2 " 2 " 2 " " 4/ Y 2 2 " 2 " 2 " "
" " Transition ta.le*
Transition Ta.le
Out)ut 'a)* .utput is mapped for all stable states. /or unstable states output is mapped unspecified.
Out)ut 'a)
,lo5 ta.le* Assign a7 29 b7 "
(. An asynchronous sequential circuit is described by the e&citation and output functions, #/ 2A!7#+3 .1 2A!1#+3 C/ # a! 3raw the logic diagram of the circuit. b! 3erive the transition table, output map and flow table. Soln*
Lo&ic "ia&ra'
ii! # 2 2 2 2 " " " " A! 2 2 " " 2 2 " " #+ 2 " 2 " 2 " 2 " A!7 " " 2 2 " " 2 2 2A!7#+3. 2 2 2 2 2 " 2 2 A!1#+ 2 " " " 2 " " " #/ 2A!7#+3 .1 2A!1#+3 2 " " " 2 " " " C/ # 2 " " " 2 " " "
Transition ta.le
Out)ut 'a) .utput is mapped for all stable states.

.
,lo5 ta.le Assign a7 29 b7 "
5. An asynchronous sequential circuit is described by the e&citation and output functions, 8/ 2Y!4!79+3 0 1 2Y!74!9+73 S/87 a! 3raw the logic diagram of the circuit
b! 3erive the translation table and output map
Soln*
2Y!4!79+3 0
Y!74!9+7
2 2
.
2 2
" "
2 2
" "
2 "
" 2
2 2
2 "
2 "
S/ 87 " 2
9+7
Y!7
9+
4!7
Y!
4!
2 2 2 2 2 2 " " " " " " " "
2 2 " " " " 2 2 2 2 " " " "
" " 2 2 2 2 " " " " 2 2 2 2
" " 2 2 " " 2 2 " " 2 2 " "
2 2 " " 2 2 " " 2 2 " " 2 2
2 " 2 " 2 " 2 " 2 " 2 " 2 "
" 2 " 2 " 2 " 2 " 2 " 2 " 2
2 2 2 2 2 2 2 2 2 2 2 2 " 2
2 2 2 2 2 2 2 " 2 2 2 2 2 2
2 2 2 2 2 2 2 " 2 2 2 2 " 2
" " " " " " " 2 " " " " 2 "
Transition ta.le an% Out)ut 'a)*
Transition ta.le
Out)ut 'a)
4 : Analysis o( Pulse -o%e Circuits

0ulse mode asynchronous sequential circuits rely on the input pulses rather than levels. They allow only one input variable to change at a time. They can be implemented by employing a :; latch. The procedure for analy<ing an asynchronous sequential circuit with :; latches can be summari<ed as follows1 ". abel each latch output with -i and its e&ternal feedback path (if any! with yi for i 7 ",$ ,..,, k. $. 3erive the 'oolean functions for the :i and ;i inputs in each latch. %. 6heck whether SR / ; for each =.; latch or whether S<R< / ; for each =A=3 latch. If either of these condition is not satisfied, there is a possibility that the circuit may not operate properly. (. )valuate Y / S 1 Ry for each =.; latch or Y / S< 1 Ry for each =A=3 latch. 5. 6onstruct a map with the y+s representing the rows and the & inputs representing the columns. 8. 0lot the value of -7 -"-$ 44-k in the map. >. 6ircle all stable states such that Y / y. The resulting map is the transition table. The analysis of a circuit with latches will be demonstrated by means of the below e&ample. ". 3erive the transition table for the pulse mode asynchronous sequential circuit shown below.

E0a')le o( a circuit 5ith SR latches
Soln* There are two inputs &" and &$ and two e&ternal feedback loops giving rise to the secondary variables y" and y$. :tep "1 The 'oolean functions for the : and ; inputs in each latch are1 S!/ 0!y+ R!/ 0!70+7 :tep $1 6heck whether the conditions :;7 2 is satisfied to ensure proper operation of the circuit. S!R!/ 0!y+ 0!70+7 / ; S+R+/ 0!0+ 0+7y! / ; The result is 2 because &"&"+ 7 &$&$+ 7 2 :tep %1 )valuate -" and -$. The e&citation functions are derived from the relation Y/ S1 R7y Y!/ S!1 R!7y! 7 &"y$ ?(&"+&$+!+ y" 7 &"y$ ?(&"? &$! y" 7 &"y$ ?&"y"? &$y" Y+/ S+1 R+7y+ 7 &"&$? (&$+y"!+y$ 7 &"&$? (&$? y"+! y$ 7 &"&$? &$y$? y"+y$ y! 2 2 2 2 2 2 2 2 " " " " " "
.
S+/ 0!0+ R+/ 0+7y!
y+ 2 2 2 2 " " " " 2 2 2 2 " "
0! 2 2 " " 2 2 " " 2 2 " " 2 2
0+ 2 " 2 " 2 " 2 " 2 " 2 " 2 "
0!y+ 2 2 2 2 2 2 " " 2 2 2 2 2 2
0!y! 2 2 2 2 2 2 2 2 2 2 " " 2 2
0+y! 2 2 2 2 2 2 2 2 2 " 2 " 2 "
0!0+ 2 2 2 " 2 2 2 " 2 2 2 " 2 2
0+y+ 2 2 2 2 2 " 2 " 2 2 2 2 2 "
y!7y+ 2 2 2 2 " " " " 2 2 2 2 2 2
Y! 2 2 2 2 2 2 " " 2 " " " 2 "
Y+ 2 2 2 " " " " " 2 2 2 "
" " :tep (1
" "
" "
2 "
" "
" "
2 "
2 "
2 "
2 2
" "
#aps for -" and -$.
:tep 51 Transition table
44
RACES*
A race condition is said to e&ist in an asynchronous sequential circuit when two or
more binary state variables change value in response to a change in an input variable. ;aces are classified as1 i. ii.
.
=on-critical races 6ritical races.
Non=critical races* If the final stable state that the circuit reaches does not depend on the order in which the state variables change, the race is called a non-critical race. If a circuit, whose transition table (a! starts with the total stable state y"y$&7 000 and then change the input from 2 to ". The state variables must then change from 22 to "", which define a race condition. The possible transitions are1 2 2 2 "" 2" "2 "" ""
In all cases, the final state is the same, which results in a non-critical condition. In (a!, the final state is (y"y$&7 """!, and in (b!, it is (y"y$&7 2""!.
E0a')les o( Non=critical Races
Critical races*
A race becomes critical if the correct ne&t state is not reached during a state transition. If it is possible to end up in two or more different stable states, depending on the order in which the state variables change, then it is a critical race. /or proper operation, critical races must be avoided. The below transition table illustrates critical race condition. The transition table (a! starts in stable state (y"y$&7 222!, and then change the input from 2 to ". The state variables must then change from 22 to "". If they change simultaneously, the final total stable state is """. In the transition table (a!, if, because of unequal propagation delay, -$ changes to "
.
before -" does, then the circuit goes to the total stable state 2"" and remains there. If, however, Y1 changes first, the internal state becomes "2 and the circuit will remain in the stable total state "2". @ence, the race is critical because the circuit goes to different stable states, depending on the order in which the state variables change.
E0a')les o( Critical Races
4>
CYCLES
;aces can be avoided by directing the circuit through intermediate unstable states
with a unique state-variable change. ,hen a circuit goes through a unique sequence of unstable states, it is said to have a cycle. Again, we start with y"y$ 7 22 and change the input from 0 to ". The transition table (a! gives a unique sequence that terminates in a total stable state "2". The table in (b! shows that even though the state variables change from 22 to "", the cycle provides a unique transition from 00 to 2" and then to "", 6are must be taken when using a cycle that terminates with a stable state. If a cycle does not terminate with a stable state, the circuit will keep going from one unstable state to another, making the entire circuit unstable. This is demonstrated in the transition table (c!.
E0a')les o( Cycles
"e.ounce Circuit* Input binary information in binary information can be generated manually be means of mechanical switches. .ne position of the switch provides a voltage equivalent to logic ", and the other position provides a second voltage equivalent to logic 2. #echanical switches are also used to start, stop, or reset the digital system. A common characteristic of a mechanical switch is that when the arm is thrown from one position to the other the switch contact vibrates or bounces several times before coming to a final rest. In a typical switch, the contact bounce may take several milliseconds to die out, causing the signal to oscillate between " and 2 because the switch contact is vibrating. A debounce circuit is a circuit which removes the series of pulses that result from a contact bounce and produces a single smooth transition of the binary signal from 0 to " or from " to 2. .ne such circuit consists of a single-pole, double-throw switch connected to an SR latch, as shown below. The center contact is connected to ground that provides a signal equivalent to logic 2. ,hen one of the two contacts, A or B, is not connected to ground through the switch, it behaves like a logic-" signal. ,hen the switch is thrown from position A to position B and back, the outputs of the latch produce a single pulse as shown, negative for Q and positive for Q'. The switch is usually a push button whose contact rests in position A. ,hen the pushbutton is depressed, it goes to position ' and when released, it returns to position A.
"e.ounce Circuit
The operation of the debounce circuit is as follows1 ,hen the switch resets in position A, we have the condition : 7 2, R 7 " and Q 7 ", Q' 7 2. ,hen the switch is moved to position B, the ground connection causes ; to go to 0, while S becomes a " because contact A is open. This condition in turn causes output A to go to 2 and AB to go to ". After the switch makes an initial contact with B, it bounces several times. The output of the latch will be unaffected by the contact bounce because AB remains " (and A remains 0) whether R is equal to 0 (contact with ground! or equal to " (no contact with ground!. ,hen the switch returns to position A, S becomes 0 and Q returns to ". The output again will e&hibit a smooth transition, even if there is a contact bounce in position A.
4?
"ESI@N O, ,UN"A-ENTAL -O"E SEQUENTIAL CIRCUITS

The design of an asynchronous sequential circuit starts from the statement of the
problem and concludes in a logic diagram. There are a number of design steps that must be carried out in order to minimi<e the circuit comple&ity and to produce a stable circuit without critical races. The design steps are as follows1 ". :tate the design specifications. $. .btain a primitive flow table from the given design specifications. %. ;educe the flow table by merging rows in the primitive flow table.
.
(. Assign binary state variables to each row of the reduced flow table to obtain the transition table. The procedure of state assignment eliminates any possible critical races. 5. Assign output values to the dashes associated with the unstable states to obtain the output maps. 8. :implify the 'oolean functions of the e&citation and output variables and draw the logic diagram. ". 3esign a gated latch circuit with inputs, C (gate! and 3 (data!, and one output, A. 'inary information present at the 3 input is transferred to the A output when C is equal to ". The A output will follow the 3 input as long as C7 ". ,hen C goes to 2, the information that was present at the 3 input at the time of transition occurred is retained at the A output. The gated latch is a memory element that accepts the value of 3 when C7 " and retains this value after C goes to 2, a change in 3 does not change the value of the output A. Soln* :tep "1 /rom the design specifications, we know that A7 2 if 3C7 2" and A7 " if 3C7 "" because 3 must be equal to A when C7 ". ,hen C goes to 2, the output depends on the last value of 3. Thus, if the transition is from 2" to 22 to "2, then A must remain 2 because 3 is 2 at the time of the transition from " to 2 in C. If the transition of 3C is from "" to "2 to 22, then A must remain ". This information results in si& different total states, as shown in the table. State a b c d e f :tep $1 In)uts " 2 " 2 " " 2 @ " " 2 2 2 2 Out)ut Q 2 " 2 2 " " Co''ents 37 A because C7 " 37 A because C7 " After state a or d After state c After state b or f After state e
A primitive flow is a flow table with only one stable total state in each row. It
has one row for each state and one column for each input combination.
Pri'iti6e (lo5 ta.le
:tep %1 The primitive flow table has only stable state in each row. The table can be reduced to a smaller number of rows if two or more stable states are placed in the same row of the flow table. The grouping of stable states from separate rows into one common row is called merging.
States that are can%i%ates (or 'er&in&
Thus, the three rows a, c, and d can be merged into one row. The second row of the reduced table results from the merging of rows b, e, and f of the primitive flow table.
Re%uce% ta.le= !
The states c D d are replaced by state a, and states e D f are replaced by state b
Re%uce% ta.le= +
:tep (1 Assign distinct binary value to each state. This assignment converts the flow table into a transition table. A binary state assignment must be made to ensure that the circuit will be free of critical races. Assign 2 to state a, and " to state b in the reduced state table.
Transition ta.le an% out)ut 'a)
Ste) >*
@ate%=Latch Lo&ic %ia&ra'
The diagram can be implemented also by means of an :; latch. .btain the 'oolean function for : and ; inputs. y 2 2 " " Y 2 " 2 " S 2 " 2 E R & 2 " 2
SR Latch e0citation ta.le
/rom the information given in the transition table and from the latch e&citation table conditions, we can obtain the maps for the : and ; inputs of the latch.
-a)s (or S an% R
The logic diagram consists of an :; latch using =.; latch and the gates required to implement the : and ; 'oolean functions. ,ith a =A=3 latch, we must use the complemented values for : and ;. S7 / 2"@37 and R7 / 2"7@37
Lo&ic %ia&ra' 5ith NOR latch
Lo&ic %ia&ra' 5ith NAN" latch
$. 3esign a negative-edge triggered T flip-flop. The circuit has two inputs, T (toggle! and C (clock!, and one output, A. the output state is complemented if T7 " and the clock changes from " to 2 (negative-edge triggering!. .therwise, under any other input condition, the output A remains unchanged. :tep "1 :tarting with the input condition T67 "" and assign it to a. The circuit goes to state b and output A complements from 2 to " when 6 changes from " to 2 while T remains a ". Another change in the output occurs when the circuit changes from state c to state d. In this case, T7", 6 changes from " to 2, and the output A complements from " to 2. The other four states in the table do not change the output, because T is equal to 2. If A is initially 2, it stays at 2, and if initially at ", it stays at " even though the clock input changes. State a b c
.
In)uts T " " " @ " 2 "
Out)ut Q 2 " "
Co''ents Initial output is 2 After state a Initial output is "
d e f g h
" 2 2 2 2
2 2 " 2 "
2 2 2 " "
After state c After state d or f After state e or a After state b or h After state g or c
S)eci(ications o( total states
:tep $* -er&in& o( the (lo5 ta.le The information for the primitive flow table can be obtained directly from the condition listed in the above table. ,e first fill in one square in each row belonging to stable state in that row as listed in the table. Then we enter dashes in those squares whose input differs by two variables from the input corresponding to the stable state. The unstable conditions are then determined by utili<ing the information listed under the comments in the above table.
Ste) :* Co')ati.le )airs The rows in the primitive flow table are merged by first obtaining all compatible pairs of states. This is done by means of the implication table.
I')lication ta.le
The implication table is used to find the compatible states. The only difference is that when comparing rows, we are at liberty to adFust the dashes to fit any desired condition. The two states are compatible if in every column of the corresponding rows in the primitive flow table, there are identical or compatible pairs and if there is no conflict in the output values. A check mark ( ! designates a square whose pair of states is compatible. Those
states that are not compatible are marked with a cross (&!. The remaining squares are recorded with the implied pairs that need further investigation. The squares that contain the check marks define the compatible pairs1 (a, f! (b, g! (b, h! (c, h! (d, e! (d, f! (e, f! (g, h!
Ste) 4* -a0i'al co')ati.les @aving found all the compatible pairs, the ne&t step is to find larger set of states that are compatible. The maximal compatible is a group of compatibles that contain all the possible combinations of compatible states. The ma&imal compatible can be obtained from a merger diagram. The 'er&er %ia&ra' is a graph in which each state is represented by a dot placed along the circumference of a circle. ines are drawn between any two corresponding dots that form a compatible pair. All possible compatibles can be obtained from the merger diagram by observing the geometrical patterns in which states are connected to each other.
.
A line represents a compatible pair A triangle constitutes a compatible with three states An n-state compatible is represented in the merger diagram by an n-sided polygon with all its diagonals connected.
-er&er "ia&ra'
The merger diagram is obtained from the list of compatible pairs derived from the implication table. There are eight straight lines connecting the dots, one for each compatible pair. The lines form a geometrical pattern consisting of two triangles connecting (b, g, h! D (d, e, f! and two lines (a, f! D (c, h!. The ma&imal compatibles are1 2aA (3 2.A &A h3 2cA h3 2%A eA (3
Re%uce% ,lo5 ta.le
The reduced flow table is drawn. The compatible states are merged into one row that retains the original letter symbols of the states. The four compatible set of states are used to merge the flow table into four rows.
,inal Re%uce% ,lo5 ta.le
@ere we assign a common letter symbol to all the stable states in each merged row. Thus, the symbol f is replaced by a9 g D h are replaced by b, and similarly for the other two rows. Ste) >* State Assi&n'ent an% Transition ta.le /ind the race-free binary assignment for the four stable states in the reduced flow table. Assign a7 22, b7 2", c7 "" and d7 "2. :ubstituting the binary assignment into the reduced flow table, the transition table is obtained. The output map is obtained from the reduced flow table. Transition Ta.le an% Out)ut -a)
Transition ta.le
Out)ut 'a) Q/ y+
Lo&ic "ia&ra'*
-a)s (or Latch In)uts
%. 3evelop a state diagram and primitive flow table for a logic system that has two inputs, E and -, and a single output E, which is to behave in the following manner. Initially, both
.
inputs and output are equal to 2. ,henever E7 " and -7 2, the G becomes " and whenever E7 2 and -7 ", the G becomes 2. ,hen inputs are <ero, i.e. E7 -7 2 or inputs are one, i.e. E7 -7 ", the output G does not change9 it remains in the previous state. The logic system has edge triggered inputs without having a clock. The logic system changes state on the rising edges of the two inputs. :tatic input values are not to have any effect in changing the G output. Soln* The conditions given are, Initially both inputs E and - are 2. ,hen E7 ", -7 29 G7 " ,hen E7 2, -7 "9 G7 2 ,hen E7 -7 2 or E7 -7 ", then G does not change, it remains in the previous state.
:tep "1 The above state transitions are represented in the state diagram as,
State %ia&ra'
:tep $1 A primitive flow table is constructed from the state diagram. The primitive flow table has one row for each state and one column for each input combination. .nly one stable state e&ists for each row in the table. The stable state can be easily identified from the state diagram. /or e&ample, state A is stable with output 2 when inputs are 22, state 6 is stable with output " when inputs are "2 and so on.
.
,e know that both inputs are not allowed to change simultaneously, so we can enter dash marks in each row that differs in two or more variables from the input variables associated with the stable state. /or e&ample, the first row in the flow table shows a stable state with an input of 22. :ince only one input can change at any given time, it can change to 2" or "2, but not to "". Therefore we can enter two dashes in the "" column of row A. The remaining places in the primitive flow table can be filled by observing state diagram. /or e&ample, state ' is the ne&t state for present state A when input combination is 2"9 similarly state 6 is the ne&t state for present state A when input combination is "2.
:tep %1 The rows in the primitive flow table are merged by first obtaining all compatible pairs of states. This is done by means of the implication table.
The squares that contain the check marks (
! define the compatible pairs1
(A, '! (A, 3! (A, /! (', 3! (6, )! (6, /! (3, )! (), /!

.
:tep (1 The merger diagram is obtained from the list of compatible pairs derived from the implication table. There are eight straight lines connecting the dots, one for each compatible pair. The lines form a geometrical pattern consisting of two triangles connecting (A, ', 3! D (6, ), /! and two lines (A, /! D (3, )!. The ma&imal compatibles are1 2AA #A "3 2CA EA ,3 2AA ,3 2"A E3
-er&er %ia&ra'
Close% co6erin& con%ition1 The condition that must be satisfied for merging rows is that the set of chosen compatibles must cover all the states and must be closed. The set will cover all the states if it includes all the states of the original state table. The closure condition is satisfied if there are no implied states or if the implied states are included within the set. A closed set of compatibles that covers all the states is called a closed covering. If we remove (A, /) and (3, )!, we are left with a set of two compatibles1 2AA #A "3 2CA EA ,3
All si& states from the primitive flow table are included in this set. Thus, the set satisfies the covering condition. The reduced flow table is drawn as below.
Re%uce% (lo5 ta.le
@ere we assign a common letter symbol to all the stable states in each merged row. Thus, the symbol ' D 3 is replaced by A9 ) D / are replaced by 6.
.
:tep 51 /ind the race-free binary assignment for the four stable states in the reduced flow table. Assign A7 2 and 67 " :ubstituting the binary assignment into the reduced flow table, the transition table is obtained. The output map is obtained from the reduced flow table.
Transition ta.le an% out)ut 'a)
:tep 81
@ate%=Latch Lo&ic %ia&ra'
(. 3esign a circuit with inputs E and - to give an output G7 " when E-7 "" but only if E becomes " before -, by drawing total state diagram, primitive flow table and output map in which transient state is included. Soln* :tep "1 The state diagram can be drawn as,
State ta.le
:tep $1 A primitive flow table is constructed from the state table as,
:tep %1 The rows in the primitive flow table are merged by first obtaining all compatible pairs of states. This is done by means of the implication table.
I')lication ta.le
The squares that contain the check marks (
(A, '! (A, 6! (A, 3! (A, )! (', 3! (6, )! :tep (1 The merger diagram is obtained from the list of compatible pairs derived from the implication table. There are si& straight lines connecting the dots, one for each compatible pair. The lines form a geometrical pattern consisting of one triangle connecting (A, ', 3! D a line (6, )!. The ma&imal compatibles are1 2AA #A "3 2CA E3
-er&er %ia&ra'
The reduced flow table is drawn as below.
Re%uce% (lo5 ta.le
@ere we assign a common letter symbol to all the stable states in each merged row. Thus, the symbol ' D 3 is replaced by A9 ) is replaced by 6.
Transition ta.le
5. 3esign a circuit with primary inputs A and ' to give an output G equal to " when A becomes " if ' is already ". .nce G7 " it will remain so until A goes to 2. 3raw the total state diagram, primitive flow table for designing this circuit. Soln* :tep "1 The state diagram can be drawn as,
State %ia&ra'
8. 3esign an asynchronous sequential circuit that has two inputs E $ and E" and one output G. ,hen E"7 2, the output G is 2. The first change in E $ that occurs while E" is " will cause output G to be ". The output G will remain " until E" returns to 2. Soln* :tep "1 The state diagram can be drawn as,
State %ia&ra'
.
:tep %1 The rows in the primitive flow table are merged by obtaining all compatible pairs of states. This is done by means of the implication table.
I')lication ta.le
The squares that contain the check marks ( (A, '! (A, 6! (6, )! (3, /! :tep (1
The merger diagram is obtained from the list of compatible pairs derived from the implication table. There are four straight lines connecting the dots, one for each compatible pair. It consists of four lines (A, '!, (A, 6!, (6, )! and (3, /!.
-er&er %ia&ra'
The ma&imal compatibles are1 2AA #3 table. The reduced flow table is drawn as below. 2CA E3 2"A ,3 This set of ma&imal compatible covers all the original states resulting in the reduced flow
/lo5 ta.le @ere we assign a common letter symbol to all the stable states in each merged row. Thus, the symbol ' is replaced by A9 ) is replaced by 6 and / is replaced by 3.
Re%uce% ,lo5 ta.le
:tep 51 /ind the race-free binary assignment for the four stable states in the reduced flow table. Assign A7 :2, 67 :" and 37 :$.
.
=ow, if we assign :27 22, :" 7 2" and :$ 7 "2, then we need one more state :%7 "" to prevent critical race during transition of :2 :" :$ and :$ :" are routed through :%. :" or :$ :". 'y introducing :% the transitions
Thus after state assignment the flow table can be given as,
,lo5 ta.le 5ith state assi&n'ent
:ubstituting the binary assignment into the reduced flow table, the transition table is obtained. The output map is obtained from the reduced flow table.
B= -a) si')li(ication1
Lo&ic "ia&ra'1
>. .btain a primitive flow table for a circuit with two inputs &" and &$ and two outputs <" and <$ that satisfies the following four conditions. i. ii. iii. iv.
.
,hen &"&$ 7 22, output <"<$ 7 22. ,hen &"7 " and &$ changes from 2 to ", the output <"<$ 7 2". ,hen &$7 " and &" changes from 2 to ", the output <"<$ 7 "2. .therwise the output does not change.
Soln* The state diagram can be drawn as,
State %ia&ra'
Ste) +* A primitive flow table is constructed from the state table as,
4C
HA4AR"S
@a<ards are unwanted switching transients that may appear at the output of a circuit
because different paths e&hibit different propagation delays. @a<ards occur in combinational circuits, where they may cause a temporary falseoutput value. ,hen this condition occurs in asynchronous sequential circuits, it may result in a transition to a wrong stable state. HaDar%s in Co'.inational Circuits* A ha<ard is a condition where a single variable change produces a momentary output change when no output change should occur. Ty)es o( HaDar%s* :tatic ha<ard 3ynamic ha<ard
4 C ! Static HaDar%
In digital systems, there are only two possible outputs, a *2+ or a *"+. The ha<ard may produce a wrong *2+ or a wrong *"+. 'ased on these observations, there are three types, :tatic- 2 ha<ard, :tatic- " ha<ard,
Static= ; haDar%* When the output of the circuit is to remain at 0, and a momentary 1 output is possible during the transmission between the two inputs, then the hazard is called a static 0 hazard! Static= ! haDar%* When the output of the circuit is to remain at 1, and a momentary 0 output is possible during the transmission between the two inputs, then the hazard is called a static 1 hazard!
The below circuit demonstrates the occurrence of a static "-ha<ard. Assume that all three inputs are initially equal to " i.e., E"E$E%7 """. This causes the output of the gate " to be ", that of gate $ to be 2, and the output of the circuit to be equal to ". =ow consider a change of E$ from " to 2 i.e., E"E$E%7 "2". The output of gate " changes to 2 and that of gate $ changes to ", leaving the output at ". The output may momentarily go to 2 if the propagation delay through the inverter is taken into consideration. The delay in the inverter may cause the output of gate " to change to 2 before the output of gate $ changes to ". In that case, both inputs of gate % are momentarily equal to 2, causing the output to go to 2 for the short interval of time that the input signal from E $ is delayed while it is propagating through the inverter circuit. Thus, a static "-ha<ard e&ists during the transition between the input states E "E$E%7 """ and E"E$E%7 "2".
Circuit 5ith static=! haDar%
=ow consider the below network, and assume that the inverter has an appreciably greater propagation delay time than the other gates. In this case there is a static 2-ha<ard in the transition between the input states E"E$E%7 222 and E"E$E%7 2"2 since it is possible for a logic-" signal to appear at both input terminals of the A=3 gate for a short duration. The delay in the inverter may cause the output of gate " to change to " before the output of gate $ changes to 2. In that case, both inputs of gate % are momentarily equal to 2, causing the output to go to " for the short interval of time that the input signal from E $ is delayed while it is propagating through the inverter circuit.
Thus, a static 2-ha<ard e&ists during the transition between the input states E "E$E%7 222 and E"E$E%7 2"2.
Circuit 5ith static=; haDar%
A ha<ard can be detected by inspection of the map of the particular circuit. To illustrate, consider the map in the circuit with static 2-ha<ard, which is a plot of the function implemented. The change in E$ from 1 to 2 moves the circuit from minterm """ to minterm "2". The ha<ard e&ists because the change in input results in a different product term covering the two minterrns.
-a)s %e'onstratin& a HaDar% an% its Re'o6al
The minterm """ is covered by the product term implemented in gate " and minterm "2" is covered by the product term implemented in gate $. ,henever the circuit must move from one product term to another, there is a possibility of a momentary interval when neither term is equal to ", giving rise to an undesirable 2 output. The remedy for eliminating a ha<ard is to enclose the two minterms in question with another product term that overlaps both groupings. This situation is shown in the free circuit obtained by this combinational is shown below. a! above, where the two terms that causes the ha<ard are combined into one product term. The ha<ard-
HaDar%=(ree Circuit
The e&tra gate in the circuit generates the product term E"E%. The ha<ards in combinational circuits can be removed by covering any two minterms that may produce a ha<ard with a product term common to both. The removal of ha<ards requires the addition of redundant gates to the circuit.
4 C + "yna'ic HaDar%
A dynamic ha<ard is defined as a transient change occurring three or more times at an output terminal of a logic network when the output is supposed to change only once during a transition between two input states differing in the value of one variable. =ow consider the input states E"E$E%7 222 and E"E$E%7 "22. /or the first input state, the steady state output is 29 while for the second input state, the steady state output is ". To facilitate the discussion of the transient behavior of this network, assume there are no propagation delays through gates C% and C5 and that the propagation delays of the other three gates are such that C" can switch faster than C$ and C$ can switch faster than C(.
Circuit 5ith "yna'ic haDar%
,hen E" changes from 2 to ", the change propagates through gate C " before gate C$ with the net effect that the inputs to gate C% are simultaneously " and the network output
.
changes from 2 to ". Then, when E" change propagates through gate C$, the lower input to gate C% becomes 2 and the network output changes back to 2. /inally, when the E"7 " signal propagates through gate C(, the lower input to gate C5 becomes " and the network output again changes to ". It is therefore seen that during the change of E" variable from 2 to " the output undergoes the sequence, 2 " 2 ", which results in three changes when it should have undergone only a single change.
4C:
Essential HaDar%
An essential ha<ard is caused by unequal delays along two or more paths that
originate from the same input. An e&cessive delay through an inverter circuit in comparison to the delay associated with the feedback path may cause such a ha<ard. Essential haDar%s eli'ination* )ssential ha<ards can be eliminated by adFusting the amount of delays in the affected path. To avoid essential ha<ards, each feedback loop must be handled with individual care to ensure that the delay in the feedback path is long enough compared with delays of other signals that originate from the input terminals.
4E
"esi&n O( HaDar% ,ree Circuits

/ (A, ', 6, 3! 7 Hm (", %, 8, >, "%, "5!
". 3esign a ha<ard-free circuit to implement the following function. Soln* a! I-map Implementation and grouping
Asynchronous Sequential Circuits ,/A7#7"1 A7#C1 A#"
b! @a<ard- free reali<ation The first additional product term A+63, overlapping two groups (group " D $! and the second additional product term, '63, overlapping the two groups (group $ D %!.
,/A7#7"1 A7#C1 A#"1 A7C"1 #C"
$. 3esign a ha<ard-free circuit to implement the following function. / (A, ', 6, 3! 7 Hm (2, $, 8, >, J, "2, "$!. Soln* a! I-map Implementation and grouping
,/ #7"71 A7#C1 AC7"7
b! @a<ard- free reali<ation The additional product term, A+63+ overlapping two groups (group " D $! for ha<ard free reali<ation. Croup " and % are already overlapped hence they do not require additional minterm for grouping.
,/ #7"71 A7#C1 AC7"71 A7C"7
%. 3esign a ha<ard-free circuit to implement the following function. / (A, ', 6, 3! 7 Hm (", %, (, 5, 8, >, K, "", "5!. a! I-map Implementation and grouping
,/ C"1 A7#1 #7"
b! @a<ard- free reali<ation The additional product term, A+3 overlapping two groups (group $ D %! for ha<ard free reali<ation. Croup " and $ are already overlapped hence they do not require additional minterm for grouping.
,/ C"1 A7#1 #7"1 A7"
(. 3esign a ha<ard-free circuit to implement the following function. / (A, ', 6, 3! 7 Hm (2, $, (, 5, 8, >, J, "2, "", "5!.
.
Soln* a! I-map Implementation and grouping
,/ #7"71 A7#1 AC"
b! @a<ard- free reali<ation
,/ #7"71 A7#1 AC"1 A7C7"71 #C"1 A#7C
5. 3esign a ha<ard-free circuit to implement the following function. / (A, ', 6, 3! 7 Hm (2, ", 5, 8, >, K, ""!. a! I-map Implementation and grouping
,/ A#7"1 A7#C1 A7#"1 A7#7C7 b!

.
@a<ard- free reali<ation1
,/ A#7"1 A7#C1 A7#"1 A7#7C71 A7C7"1 #7C7"

ASynchronous Sequential Circuits

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ASynchronous Sequential Circuits

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Asynchronous Sequential Circuits