5starts Bernhard Introduction

llf0000ll0 l0 $8l0M0
1.0.K
80f08f0 8l0M8
ff8000l0f l8lll0l0 l0f
ll0f8l00 0lf00ll8
IIS
Fraunhofer
Institut
Integrierte Schaltungen
FhC llS-A, 2001
2
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Fraunhofer
Institut
FhC llS-A, 2001
00(00ll908
This tutorial offers
A short motivation for C based design flow
A brief introduction to the most important SystemC 1.0.x
language elements
A very short overview on refinement for synthesis
A simple example program
This tutorial does not
provide a complete treatment of the SystemC language
cover system level modeling with SystemC 2.0
3
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Fraunhofer
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008
SystemC Introduction 1
Topic Unit
Language Elements of SystemC

2
SystemC and Synthesis 3
Simple Example 4
Resources 5
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Problems:Written specifications are incomplete and inconsistent
Translation to HDL is time consuming and error prone
C/C++ C/C++
1. Conceptualize
2. Simulate in C++
3. Write specification
document
4. Hand over specification document
HDL HDL
5. Understand
6. (Re)Implement in HDL
7. (Re)Verify
8. Synthesize from HDL
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C/C++ C/C++
0 88800 fl0N
1. Conceptualize
2. Simulate in C++
3. Write specification
document
4. Hand over
Executable specification
Testbench
Written specification
C/C++
C/C++ C/C++
5. Understand
6. Refine in C++
7. Verify reusing testbenches
8. Synthesize from C++
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SystemC supports
Hardware style communication
Signals, protocols, etc.
Notion of time
Time sequenced operations.
Concurrency
Hardware and systems are inherently concurrent, i.e. they operate in
parallel.
Reactivity
Hardware is inherently reactive, it responds to stimuli and is in
constant interaction with its environment, which requires handling of
exceptions.
Hardware data types
Bit type, bit-vector type, multi-valued logic type, signed and unsigned
integer types and fixed-point types.
Integrated Simulation Kernel
All these features are not supported by C++ as is
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UTF
UTF
TF
TF
Partition
Behavioral
Behavioral
RTL
RTL
abstract
RTOS
abstract
RTOS
target
code
target
code
Netlist
Netlist
Refine
Refine
Refine
Refine
System/ Architectural Level
not synthesizable
event driven
abstract communication
abstract data types
Behavioral Level
synthesizable
clocked
I/O cycle accurate
algorithmic description
RT Level
synthesizable
clocked
FSM
data path
Software
Hardware
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class library
and
simulation kernel source files for system
and testbenches
your standard
C/C++ development
environment
compiler
linker
debugger
libraries
header files
e
x
e
c
u
t
a
b
l
e

s
p
e
c
i
f
i
c
a
t
i
o
n
.
.
.
.
.
.
.
.
.
.
.
executable = simulator
sim.x
ASIC
IP-Core
Interface
DSP
make
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Module
N000l $lf00l0f0 $8l0M l090l
Algorithm
Channel (implements I/F)
Channel (implements I/F)
Interface
Interface
Port (accesses a channels I/F)
Port (accesses a channels I/F)
Process (reads data from input ports
and writes data to output ports)
SystemC 2.x
o Module
o Port
o Interface
o Channel
o Process
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Algorithm
Hardware signal
Hardware signal
Special ports to access the hardware signal
Special ports to access the hardware signal
Module
SystemC 1.0.x
o Module
o Special Ports
o Hardware Signal
o Process
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main.cpp
main.cpp
stimgen.cpp
stimgen.cpp
stimgen.h
stimgen.h
algo.cpp
algo.cpp
algo.h
algo.h
monitor.cpp
monitor.cpp
monitor.h
monitor.h
DUT
in1
in2
out
Response
Monitor
re
Stimulus
Generator
a1
a2
main.cpp
clk
in1
in2
out
Algorithm
DUT
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VHDL SystemC
Hierarchy entity module
Connection port port
Communication signal signal
Functionality process process
Test Bench object orientation
System Level channel, interface, event
abstract data types
I/O simple file I/O C++ I/O capabilities
13
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FhC llS-A, 2001
008
SystemC Introduction 1
Topic Unit

2
Simple Example 4
Resources 5
14
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FhC llS-A, 2001
008
Topic Unit
Language Elements of SystemC 2
Data Types 2.1
Processes 2.2
Hierarchy 2.3
Modules, Ports and Signals 2.1
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C++ built in data types may be used but are not adequate to
model Hardware.
long, int, short, char, unsigned long, unsigned int,
unsigned short, unsigned char, float, double, long double,
and bool.
SystemC
TM
provides other types that are needed for System
modeling.
Scalar boolean types: sc_logic, sc_bit
Vector boolean types: sc_bv<length>, sc_lv<length>
Integer types: sc_int<length>, sc_uint<length>,
sc_bigint<length>, sc_biguint<length>
Fixed point types: sc_fixed, sc_ufixed
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Hint: You may use a profiling tool, which tells you, how much
time you spent in which function call, to control simulation
speed.
N00 l0 080 N0l00 08l8 108 1
To get fast simulations, you have to choose the right data type
use builtin C/C++ data types as much as possible
use sc_int/sc_uint
integer with up to 64 bits
model arithmetic and logic operations
use sc_bit/sc_bv
arbitrary length bit vector
model logic operations on bit vectors
two valued logic
use sc_logic/sc_lv
4 valued logic vectors
model tri-state behavior
Fastest
Slowest
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Hint: You may use a profiling tool, which tells you, how much
time you spent in which function call, to control simulation
speed.
N00 l0 080 N0l00 08l8 108 Z
To get fast simulations, you have to choose the right data type
use sc_bigint/sc_biguint
integer with arbitrary length
use to model arithmetic operations on large bit vectors
ineffective for logic operations
use sc_fixed/sc_ufixed
arbitrary precision fixed point
use to model fixed point artihmetic
ineffective for logic operations
Fastest
Slowest
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Syntax:
sc_int<length> variable_name ;
sc_uint<length> variable_name ;
sc_bigint<length> variable_name ;
sc_biguint<length> variable_name ;
length:
Specifies the number of elements in the array
Must be greater than 0
Must be compile time constant
Use [] to bit select and range() to part select.
Rightmost is LSB(0), Leftmost is MSB (n-1)
Syntax:
sc_int<length> variable_name ;
sc_uint<length> variable_name ;
sc_bigint<length> variable_name ;
sc_biguint<length> variable_name ;
length:
Specifies the number of elements in the array
Must be greater than 0
Must be compile time constant
Use [] to bit select and range() to part select.
Rightmost is LSB(0), Leftmost is MSB (n-1)
sc_int<5> a; // a is a 5-bit signed integer
sc_uint<44> b; // b is a 44-bit unsigned integer
sc_bigint<5> c;
c = 13; // c gets 01101, c[4] = 0, c[3] = 1, , a[0] = 1
bool d;
d = c[4]; // d gets 0
d = c[3]; // d gets 1
sc_bigint<3> e;
e = c.range(3, 1); // e gets 110 - interpreted as -2
sc_int<5> a; // a is a 5-bit signed integer
sc_uint<44> b; // b is a 44-bit unsigned integer
sc_bigint<5> c;
c = 13; // c gets 01101, c[4] = 0, c[3] = 1, , a[0] = 1
bool d;
d = c[4]; // d gets 0
d = c[3]; // d gets 1
sc_bigint<3> e;
e = c.range(3, 1); // e gets 110 - interpreted as -2
19
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Fraunhofer
Institut
FhC llS-A, 2001
008
Topic Unit
Data Types 2.1
Processes 2.2
Hierarchy 2.3
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N000l0
A module is a container. It is the
basic building block of SystemC
Similar to VHDL entity
Module interface in the header file
(ending .h)
Module functionality in the
implementation file (ending .cpp)
Module contains:
Ports
Internal signal variables
Internal data variables
Processes of different types
Other methods
Instances of other modules
Constructor
main.cpp
main.cpp
stimgen.cpp
stimgen.cpp
stimgen.h
stimgen.h
algo.cpp
algo.cpp
algo.h
algo.h
monitor.cpp
monitor.cpp
monitor.h
monitor.h
DUT
in1
in2
out
Response
Monitor
re
Stimulus
Generator
a1
a2
main.cpp
clk
21
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Syntax:
SC_MODULE(module_name){
// body of module
};
Syntax:
SC_MODULE(module_name){
// body of module
};
EXAMPLE:
SC_MODULE(my_module) {
// body of module
};
EXAMPLE:
SC_MODULE(my_module) {
// body of module
};
Code in header file:
my_module.h
my_module.h
Note: SC_MODULE is a macro for
struct module_name : sc_module
Note the semicolon at the
end of the module definition
Note the semicolon at the
end of the module definition
SC_MODULE
{
o Ports
o Signals
o Variables
o Constructor
o Processes
o Modules
};
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Module
Instance
Module
Instance
Module
Instance
Module
Instance
Process
Process
Other
Method
Other
Method
Signal connecting modules (declared in
module)
Signal connecting modules (declared in
module)
Ports bound directly to
each other (no signal)
Ports bound directly to
each other (no signal)
Ports
Ports
Process can read/write
ports and signals
Process can read/write
ports and signals
Other methods can
read/write ports and signals
Other methods can
read/write ports and signals
MODULE
SC_MODULE
{
o Ports
o Signals
o Variables
o Constructor
o Processes
o Modules
};
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Ports are the external interface of a module
Pass information to and from a module
There are three different kinds of ports
input
output
inout
Ports are always bound to signals
exception: port-to-port binding (explained later)
Ports are members of the module
Each port has a data type
passed as template parameter
DUT
in1
in2
out
Response
Monitor
re
Stimulus
Generator
a1
a2
main.cpp
clk
SC_MODULE
{
Ports
o Signals
o Variables
o Constructor
o Processes
o Modules
};
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Ports have to be declared inside a module
The direction of the port is specified by the port type
input: sc_in<>
output: sc_out<>
inout: sc_inout<>
The data type is passed as template parameter
Declaration as data members of the module:
SC_MODULE(my_mod) {
sc_in<t_data> port_name;
sc_out<t_data> port_name;
sc_inout<t_data> port_name;
};
t_data:
data type of the port
SC_MODULE(my_mod) {
sc_in<t_data> port_name;
sc_out<t_data> port_name;
sc_inout<t_data> port_name;
};
t_data:
data type of the port
SC_MODULE
{
Ports
o Signals
o Variables
o Constructor
o Processes
o Modules
};
25
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Signals are used for communication
Exchange of data in a concurrent execution semantics
between modules
between processes
There is only one kind of signal
Signals always carry a value
Signals need not necessarily be bound to ports
may also be used for communication between processes
Signals may be
members of a module (used for internal communication)
used at top-level to connect the modules
Each signal has a data type
passed as template parameter
SC_MODULE
{
o Ports
Signals
o Variables
o Constructor
o Processes
o Modules
};
DUT
in1
in2
out
Response
Monitor
re
Stimulus
Generator
a1
a2
main.cpp
clk
26
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Signals are declared inside a module or at top level
There is only one type of signal
sc_signal<>
The data type is passed as template parameter
SC_MODULE(my_mod) {
sc_signal<t_data> signal_name;
};
t_data:
data type of the signal
SC_MODULE(my_mod) {
sc_signal<t_data> signal_name;
};
t_data:
data type of the signal
SC_MODULE
{
o Ports
Signals
o Variables
o Constructor
o Processes
o Modules
};
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SC_MODULE(module_name) {
// ports
sc_in<int> a;
sc_out<bool> b;
sc_inout<sc_bit> c;
// signals
sc_signal<int> d;
sc_signal<char> e;
sc_signal<sc_int<10> > f;
// rest
};
SC_MODULE(module_name) {
// ports
sc_in<int> a;
sc_out<bool> b;
sc_inout<sc_bit> c;
// signals
sc_signal<int> d;
sc_signal<char> e;
sc_signal<sc_int<10> > f;
// rest
};
Declaring ports and signals within a module
ports and signals are data members of the module
good style to declare
ports at the beginning of the module
signals after port declaration
Note: a space is
required by the C++
compiler
Note: a space is
required by the C++
compiler
SC_MODULE
{
Ports
Signals
o Variables
o Constructor
o Processes
o Modules
};
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recommended
recommended
F0fl8 80 $l8l8 8080 80 Nfll0
To read a value from a port or signal
use assignment
use the .read() method (recommended)
To write a value to a port or signal
use assignment
use the .write() method (recommended)
The usage of .read() and .write() avoids implicit type conversion,
which is a source of many compile time errors
sc_signal<int> sig;
int a;
...
a = sig;
sig = 10;
sc_signal<int> sig;
int a;
...
a = sig;
sig = 10;
sc_signal<int> sig;
int a;
...
a = sig.read();
sig.write(10);
sc_signal<int> sig;
int a;
...
a = sig.read();
sig.write(10);
SC_MODULE
{
Ports
Signals
o Variables
o Constructor
o Processes
o Modules
};
29
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Example:
SC_MODULE(count) {
// ports & signals not shown
int count_val; // internal data stroage
sc_int<8> mem[512] // array of sc_int
// Body of module not shown
};
Example:
SC_MODULE(count) {
// ports & signals not shown
int count_val; // internal data stroage
sc_int<8> mem[512] // array of sc_int
// Body of module not shown
};
Data variables are member variables of a module
any legal C/C++ and SystemC/user defined data type
internal to the module
should not be used outside of the module
useful to store the internal state of a module
e.g. usage as memory
SC_MODULE
{
o Ports
o Signals
Variables
o Constructor
o Processes
o Modules
};
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Each module has a constructor
Called at the instantiation of the module
initialize internal data structure (e.g. check port-signal
binding)
initialize all data members of the module to a known state
Instance name passed as argument
useful for debugging/error reporting
Processes are registered inside the constructor (more
later)
Sub-modules are instanciated inside the constructor
(more later)
SC_MODULE
{
o Ports
o Signals
o Variables
Constructor
o Processes
o Modules
};
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Example:
SC_MODULE (my_module) {
// Ports, internal signals, processes, other methods
// Constructor
SC_CTOR(my_module) {
// process registration & declarations of sensitivity lists
// module instantiations & port connection declarations
}
};
Example:
SC_MODULE (my_module) {
// Ports, internal signals, processes, other methods
// Constructor
SC_CTOR(my_module) {
// process registration & declarations of sensitivity lists
// module instantiations & port connection declarations
}
};
Note: SC_CTOR is a macro for
typedef name SC_CURRENT_USER_MODULE; \
name(sc_module_name)
module_name.h
module_name.h
SC_MODULE
{
o Ports
o Signals
o Variables
Constructor
o Processes
o Modules
};
32
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008
Topic Unit
Data Types 2.1
Processes 2.2
Hierarchy 2.3
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Functionality of a SystemC model is described in processes.
Processes are member functions of a module. They are registered
to the SystemC simulation kernel.
Processes are called by the simulation kernel, whenever a signal in
their sensitivity list is changing.
Some processes execute when called and return control to the calling
function (behave like a function).
Some processes are called once, and then can suspend themselves
and resume execution later (behave like threads).
Processes are not hierarchical
Cannot have a process inside another process (use module for
hierarchical design)
SC_MODULE
{
o Ports
o Signals
o Variables
o Constructor
Processes
o Modules
};
34
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Processes use signals to communicate with each other.
Dont use global variables - may cause order dependencies in
code (very bad).
Processes use timing control statements to implement
synchronization and writing of signals in processes (explained
later).
Process and signal updates follow the evaluate-update
semantics of SystemC.
Processes are registered to the simulation kernel within the
modules constructor.
SC_MODULE
{
o Ports
o Signals
o Variables
o Constructor
Processes
o Modules
};
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SC_METHOD (sc_async_fprocess)
process executes everything and wakes up at next event
good for modeling combinational logic
synchronous logic is sensitive to clock edge
SC_THREAD (sc_async_tprocess)
execution is suspended on wait() until next event
SC_CTHREAD (sc_sync_tprocess)
execution is suspended on wait() until next active clock edge
within one process can be only registers sensitive to one clock
edge
SC_MODULE
{
o Ports
o Signals
o Variables
o Constructor
Processes
o Modules
};
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Asynchronous Function Process SC_METHOD:
Is sensitive to a set of signals
This set is called sensitivity list
May be sensitive to any change on a signal
May be sensitive to the positive or negative edge of a boolean
signal
Is invoked whenever any of the inputs it is sensitive to changes.
Once an asynchronous function process is invoked:
Entire body of the block is executed.
Instructions are executed infinitely fast (in terms of internal simulation
time).
Instructions are executed in order.
Processes
SC_METHOD
o SC_THREAD
o SC_CTHREAD
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Asynchronous Function Process SC_METHOD:
Model combinational logic
multiplexing, bit extraction, bit manipulation, arith. operations...
Model sequential logic
use a SC_METHOD process sensitive to only on clock edge to update the
registers
use another SC_METHOD process sensitive to all values to be read within
this process to calculate new values
Monitor signals as part of a testbench
Use for RT level modeling
Model event driven systems (architectural level)
Processes
SC_METHOD
o SC_THREAD
o SC_CTHREAD
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To define the sensitivity list for any process type use
sensitive with the () operator
takes a single port or signal as an argument
e.g. sensitive(sig1); sensitive(sig2); sensitive(sig3);
sensitive with stream notation (operator <<)
takes an arbitrary number of arguments
e.g. sensitive << sig1 << sig2 << sig3;
sensitive_pos with either () or << operator
defines sensitivity to positive edge of boolean signal or clock
e.g. sensitive_pos << clk;
sensitive_neg with either () or << operator
defines sensitivity to negative edge of boolean signal or clock
e.g. sensitive_neg << clk;
Processes
SC_METHOD
SC_THREAD
o SC_CTHREAD
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SC_MODULE( my_module ) {
sc_in_clk clk;
sc_in<bool> reset_n;
sc_in<int> in1;
sc_in<int> in2;
sc_out<int> out1;
sc_out<int> out2;
sc_signal<int> sig1;
int _internal;
void proc1();
SC_CTOR( my_module ) {
SC_METHOD( proc1 );
sensitive << in1 << sig1;
}
};
void my_module::proc1()
{
int inc = 5;
inc++;
sig2 = in1.read() + sig1 + inc;
}
State of internal variables not preserved
=> expression evaluates to
sig2 = in1+sig1+6
each time the process is executed.
State of internal variables not preserved
=> expression evaluates to
sig2 = in1+sig1+6
each time the process is executed.
Processes
SC_METHOD
o SC_THREAD
o SC_CTHREAD
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Asynchronous Thread Process SC_THREAD:
Is sensitive to a set of signals
This set is called sensitivity list
May be sensitive to any change on a signal
May be sensitive to the positive or negative edge of a boolean signal
Is reactivated whenever any of the inputs it is sensitive to changes.
Once an asynchronous thread process is reactivated:
Instructions are executed infinitely fast (in terms of internal simulation
time) until the next occurrence of a wait() statement.
Instructions are executed in order.
The next time the process is reactivated execution will continue after the
wait() statement.
Processes
o SC_METHOD
SC_THREAD
o SC_CTHREAD
41
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Asynchronous Thread Process SC_THREAD:
May be used to model synchronous AND asynchronous behavior
(even in the same process).
Most useful at higher levels of abstraction (esp. with SystemC 2.0)
Has to be replaced by asynchronous function or synchronous thread
process during refinement.
May be used in test benches.
Processes
o SC_METHOD
SC_THREAD
o SC_CTHREAD
42
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Institut
FhC llS-A, 2001
1lMl 00lf0l $l8l0M0l8
Implement synchronization and writing of signals in processes.
wait() suspends execution of the process until the process is
invoked again.
If no timing control statement used:
Process executes in zero time.
Outputs are never visible.
To write to an output signal, a process needs to invoke a timing
control statement.
Multiple interacting synchronous processes must have at least
one timing control statement in every path.
Processes
o SC_METHOD
SC_THREAD
SC_CTHREAD
43
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Institut
FhC llS-A, 2001
10f080 Ff0008808. N8llIl f00ll0
wait() may be used in both SC_THREAD and SC_CTHREAD processes
but NOT in an SC_METHOD process (block).
wait() suspends execution of the process until the process is
invoked again.
wait(<pos_int>) may be used to wait for a certain number of
cycles (SC_CTHREAD only).
In Synchronous process (SC_CTHREAD)
Statements before the wait() are executed in one cycle.
Statements after the wait() are executed the next cycle.
In Asynchronous process (SC_THREAD)
Statements before the wait() are executed in last event.
Statements after the wait() are executed the next event.
Examples:
wait() ; // waits 1 cycle in synchronous process
wait(4); // waits 4 cycles in synchronous process
wait(4) ; //ERROR!! in Asynchronous process
Examples:
wait() ; // waits 1 cycle in synchronous process
wait(4); // waits 4 cycles in synchronous process
wait(4) ; //ERROR!! in Asynchronous process
Processes
o SC_METHOD
SC_THREAD
SC_CTHREAD
44
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Institut
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$0_188f0
sc_in_clk clk;
sc_in<int> in1;
sc_in<int> in2;
sc_out<int> out1;
sc_out<int> out2;
int _internal;
void proc2();
SC_THREAD( proc2 );
sensitive << in2 << sig2;
}
};
{
// start-up functionality goes here
int inc = 1;
while(1) {
out1.write(in2.read() + sig2 + inc);
++inc;
wait();
}
}
State of internal variables is preserved =>
the value of inc is incremented by one
each time the process is reactivated.
the value of inc is incremented by one
each time the process is reactivated.
Processes
o SC_METHOD
SC_THREAD
o SC_CTHREAD
45
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Fraunhofer
Institut
FhC llS-A, 2001
$0. 10f080 Ff0008808 008f80l0fl8ll08 1
Synchronous process SC_CTHREAD:
Sensitive only to one edge of one and only one clock
Called the active edge
Special case of a SC_THREAD process
Cannot use multiple clocks with a synchronous process
Triggered only at active edge of its clock
Therefore inputs are sampled only at the active edge.
It is not triggered if inputs other than the clock change.
Models the behavior of unregistered inputs and registered outputs
Processes
o SC_METHOD
o SC_THREAD
SC_CTHREAD
46
IIS
Fraunhofer
Institut
FhC llS-A, 2001
$0. 10f080 Ff0008808 008f80l0fl8ll08 Z
Synchronous process SC_CTHREAD:
Once invoked the statements execute until a wait()
statement is encountered.
At the wait()statement, the process execution is suspended
At the next execution, process execution starts from the
statement after the wait()statement
Local variables defined in the process function are saved
each time the process is suspended.
Tip: Use wait(<pos_int>); to wait for multiple clock cycles.
Processes
o SC_METHOD
o SC_THREAD
SC_CTHREAD
47
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Institut
FhC llS-A, 2001
$00f0008 10f080 Ff00088 . ll0 1lMl
1 35
13 18
14
in1
in2
out
clock
in2
in1
out
while (true) {
out = in1 + in2;
wait( );
}
in1
in2
out
Processes
o SC_METHOD
o SC_THREAD
SC_CTHREAD
1 35
13 18
in1
in2
out
clock
14 53
SystemC 1.0.x
SystemC 2.0
48
IIS
Fraunhofer
Institut
FhC llS-A, 2001
$00f0008 10f080 Ff00088 0880
Synchronous Thread Process SC_CTHREAD:
Useful for high level synthesis.
Modeling of synchronous systems.
Modeling of sequential logic.
Models the behavior of a block with unregistered inputs and
registered outputs.
Useful for modeling drivers in test benches.
Processes
o SC_METHOD
o SC_THREAD
SC_CTHREAD
49
IIS
Fraunhofer
Institut
FhC llS-A, 2001
$0_0188f0
sc_in_clk clk;
sc_in<int> in1;
sc_in<int> in2;
sc_out<int> out1;
sc_out<int> out2;
int _internal;
void proc3();
SC_CTHREAD( proc3, clk.pos() );
}
};
{
// start-up functionality goes here
int inc = 1;
while(1) {
out2.write(inc);
sig2 = sig2 + inc;
++inc;
wait();
}
}
the value of inc is incremented by at each
positive clock edge.
the value of inc is incremented by at each
positive clock edge.
Processes
o SC_METHOD
o SC_THREAD
SC_CTHREAD
50
IIS
Fraunhofer
Institut
FhC llS-A, 2001
008
Topic Unit
Data Types 2.1
Processes 2.2
Hierarchy 2.3
51
IIS
Fraunhofer
Institut
FhC llS-A, 2001
N000ll 8l0f8f00 090f9l0N
Systems are modeled hierarchically
SystemC has to provide a mechanism for hierarchy
Solution
Modules may contain instances of other modules
in
sub_a
top
sub_b
top
sub_a
sub_b
SC_MODULE
{
o Ports
o Signals
o Variables
o Constructor
o Processes
Modules
};
a_in a_out out b_in b_out
sig
52
IIS
Fraunhofer
Institut
FhC llS-A, 2001
N000ll 8l0f8f00 00ll0 ll0f8l $l8l8
SC_MODULE
{
o Ports
o Signals
o Variables
o Constructor
o Processes
Modules
};
SC_MODULE(top)
{
sc_in<int> in;
sc_out<int> out;
sc_signal<int> sig;
sub_a* inst1;
sub_b* inst2;
....
};
SC_MODULE(top)
{
sc_in<int> in;
sc_out<int> out;
sc_signal<int> sig;
sub_a* inst1;
sub_b* inst2;
....
};
Define member variables
for all the internal signals
that are needed to connect
the child modules ports to
each other.
Note: a port of the parent
module is directly bound to
a port of the child module
(no signal needed).
for all the internal signals
that are needed to connect
the child modules ports to
each other.
Note: a port of the parent
module is directly bound to
a port of the child module
(no signal needed).
in
sub_a
top
sub_b
sig
53
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Fraunhofer
Institut
FhC llS-A, 2001
N000ll 8l0f8f00 00ll0 F0ll0f8
SC_MODULE
{
o Ports
o Signals
o Variables
o Constructor
o Processes
Modules
};
SC_MODULE(top)
{
sc_in<int> in;
sc_out<int> out;
sc_signal<int> sig;
sub_a* inst1;
sub_b* inst2;
....
};
SC_MODULE(top)
{
sc_in<int> in;
sc_out<int> out;
sc_signal<int> sig;
sub_a* inst1;
sub_b* inst2;
....
};
that are pointers to the
child modules class for all
instances
that are pointers to the
child modules class for all
instances
in
sub_a
top
sub_b
sig
54
IIS
Fraunhofer
Institut
FhC llS-A, 2001
N000ll 8l0f8f00 0f08l0 l8l8008
SC_MODULE
{
o Ports
o Signals
o Variables
o Constructor
o Processes
Modules
};
SC_CTOR {
inst1 = new sub_a("inst_1");
inst2 = new sub_b("inst_2");
(*inst1).a_out(sig);
(*inst1).a_in(in);
(*inst2)(sig, b_out);
}
SC_CTOR {
(*inst1).a_in(in);
}
Create the child module
instances within the parent
modules constructor using
the C++ keyword new.
An arbitrary name is given
to the module instances. It
is good practice to use the
name of the instance
variable.
Create the child module
instances within the parent
modules constructor using
the C++ keyword new.
An arbitrary name is given
to the module instances. It
is good practice to use the
name of the instance
variable.
in
sub_a
top
sub_b
sig
55
IIS
Fraunhofer
Institut
FhC llS-A, 2001
N000ll 8l0f8f00 0000l F0fl8 80 $l8l8
SC_MODULE
{
o Ports
o Signals
o Variables
o Constructor
o Processes
Modules
};
SC_CTOR {
(*inst1).a_in(in);
}
SC_CTOR {
(*inst1).a_in(in);
}
Connect ports of child
modules to one another with
internal signals.
Connect ports of the parent
module to ports of the child
module using direct port-to-
port connection. A signal
MUST NOT be used.
Connect ports of child
modules to one another with
internal signals.
Connect ports of the parent
module to ports of the child
module using direct port-to-
port connection. A signal
MUST NOT be used.
in
sub_a
top
sub_b
sig
Mapping by name is
recommended.
Mapping by position may also
be used.
Mapping by name is
recommended.
Mapping by position may also
be used.
56
IIS
Fraunhofer
Institut
FhC llS-A, 2001
008
Why C-based Design Flow 1
Topic Unit

2
Simple Example 4
Resources 5
57
IIS
Fraunhofer
Institut
FhC llS-A, 2001
$8l0M0 008l fl0N
UTF
UTF
TF
TF
Partition
Behavioral
Behavioral
RTL
RTL
abstract
RTOS
abstract
RTOS
target
code
target
code
Netlist
Netlist
Refine
Refine
Refine
Refine
System/ Architectural Level
not synthesizable
event driven
abstract communication
abstract data types
Behavioral Level
synthesizable
clocked
I/O cycle accurate
algorithmic description
RT Level
synthesizable
clocked
FSM
data path
Software
Hardware
58
IIS
Fraunhofer
Institut
FhC llS-A, 2001
98ll80l0 f00ll08lll 80 100l8
System/Architectural Level
channels, interfaces, events, master-slave comm. library (all beta)
Behavioral
synthesis to netlist
RTL
synthesis to netlist
Software
abstract RTOS (not yet available)
59
IIS
Fraunhofer
Institut
FhC llS-A, 2001
80ll0M0l l0f $l008l8
Refine Structure
use signals for I/F
partition into synthesizable blocks
restrict to synthesizable language subset
Refine Control
specify throughput/latency
specify I/O protocol
Refine Data
restrict to physically meaningful data
types (no abstract data)
specify bit width
Functional Description
Implementable Description
Structure Control Data
60
IIS
Fraunhofer
Institut
FhC llS-A, 2001
80089l0f8l N000ll $8l0M
CPU
Memory
I/O Board
Disk
Bus
Arbiter
algorithmic
Clk
driven
Bus IF
algorithmic
Clk
driven
Bus IF
Clk
driven
Bus IF
Clk
driven
Bus IF
algorithmic
Clk
driven
Bus IF
algorithmic
61
IIS
Fraunhofer
Institut
FhC llS-A, 2001
80089l0f8l N000ll N000l0
SC_MODULE(fir) {
sc_in_clk clk;
sc_in<bool> reset;
sc_in<T_DATA> in;
sc_in<bool> in_data_valid;
sc_out<T_DATA> out;
sc_out<bool> out_data_valid;
...
SC_CTOR(fir) {
SC_CTHREAD(fir_process, clk.pos());
...
}
};
Interface cycle accurate
ports and signals
synthesizable data types
introduction of a clock
Rest of module
algorithmic
clocked (SC_CTHREAD)
restriction to synthesizable SystemC
subset
Behavioral Code may utilize
functions to reduce code complexity
loops
conditional statements
no abstract data types for
ports/signals
only synthesizable subset of
SystemC
62
IIS
Fraunhofer
Institut
FhC llS-A, 2001
81 l090l N000ll $8l0M
CPU
Memory
I/O Board
Disk
Bus
Arbiter
CLK
driven
CLK
driven
CLK
driven
63
IIS
Fraunhofer
Institut
FhC llS-A, 2001
81 l090l N000ll N000l0
SC_MODULE(fir) {
sc_in_clk clk;
sc_in<bool> reset;
sc_in<T_DATA> in;
sc_in<bool> in_data_valid;
sc_out<T_DATA> out;
sc_out<bool> out_data_valid;
...
sc_signal<T_STATE> state_curr, state_nxt;
...
SC_CTOR(fir) {
SC_METHOD(fir);
sensitive << state_curr << in;
SC_METHOD(fsm);
sensitive << state_curr << data_valid;
SC_METHOD(reg);
sensitive_pos << clk;
sensitive << reset;
...
}
};
Interface cycle accurate
ports and signals
synthesizable data types
introduction of a clock
Rest of module
cycle accurate
sequential and combinational logic
(SC_METHOD)
restriction to synthesizable SystemC
subset
RTL Code may utilize
functions to reduce code complexity
loops
conditional statements
no abstract data types for
ports/signals
only synthesizable subset of
SystemC
64
IIS
Fraunhofer
Institut
FhC llS-A, 2001
008
Topic Unit

2
Simple Example 4
Resources 5
65
IIS
Fraunhofer
Institut
FhC llS-A, 2001
$lMl0 fK8Ml0 090f9l0N
main.cpp
main.cpp
stimgen.cpp
stimgen.cpp
stimgen.h
stimgen.h
adder.cpp
adder.cpp
adder.h
adder.h
monitor.cpp
monitor.cpp
monitor.h
monitor.h
Adder
in1
in2
out
Response
Monitor
re
Stimulus
Generator
a1
a2
main.cpp
clk
+
in1
in2
out
66
IIS
Fraunhofer
Institut
FhC llS-A, 2001
$lMl0 fK8Ml0 $lM0l8ll0 N000l
// header file adder.h
typedef int T_ADD;
SC_MODULE(adder) {
// Input ports
sc_port<sc_fifo_in_if<T_ADD> > in1;
// Output ports
sc_port<sc_fifo_out_if<T_ADD> > in2;
// Constructor
SC_CTOR(adder){
SC_THREAD(main);
}
// Functionality of the process
void main();
};
typedef int T_ADD;
SC_MODULE(adder) {
// Input ports
// Output ports
sc_port<sc_fifo_out_if<T_ADD> > in2;
// Constructor
SC_CTOR(adder){
SC_THREAD(main);
}
void main();
};
main.cpp
main.cpp
stimgen.cpp
stimgen.cpp
adder.cpp
adder.cpp
adder.h
adder.h
monitor.cpp
monitor.cpp
monitor.h
monitor.h
stimgen.h
stimgen.h
Adder
in1
in2
out
Response
Monitor
re
Stimulus
Generator
a1
a2
main.cpp
clk
67
IIS
Fraunhofer
Institut
FhC llS-A, 2001
$lMl0 fK8Ml0 $lM0l8ll0 N000l
// Implementation file adder.cpp
#include systemc.h
#include adder.h
void adder::main()
{
while (true) {
out->write(in1->read() + in2->read());
// assign a run-time to process
wait(10, SC_NS);
}
}
// Implementation file adder.cpp
#include systemc.h
#include adder.h
void adder::main()
{
while (true) {
out->write(in1->read() + in2->read());
// assign a run-time to process
wait(10, SC_NS);
}
}
main.cpp
main.cpp
stimgen.cpp
stimgen.cpp
adder.cpp
adder.cpp
adder.h
adder.h
monitor.cpp
monitor.cpp
monitor.h
monitor.h
stimgen.h
stimgen.h
Adder
in1
in2
out
Response
Monitor
re
Stimulus
Generator
a1
a2
main.cpp
clk
68
IIS
Fraunhofer
Institut
FhC llS-A, 2001
$lMl0 fK8Ml0 80089l0f8l l090l
typedef sc_int<8> T_ADD;
SC_MODULE(adder) {
// Clock introduced
sc_in_clk clk;
// Input ports
sc_in<T_ADD> in1;
sc_in<T_ADD> in2;
// Output port
sc_out<T_ADD> out;
// Constructor
SC_CTOR(adder){
SC_CTHREAD(main, clk.pos());
}
void main();
};
main.cpp
main.cpp
stimgen.cpp
stimgen.cpp
adder.cpp
adder.cpp
adder.h
adder.h
monitor.cpp
monitor.cpp
monitor.h
monitor.h
stimgen.h
stimgen.h
Adder
in1
in2
out
Response
Monitor
re
Stimulus
Generator
a1
a2
main.cpp
clk
69
IIS
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Institut
FhC llS-A, 2001
$lMl0 fK8Ml0 80089l0f8l l090l
// Implementation file adder.cc
#include systemc.h
#include adder.h
void adder::main()
{
// initialization
T_ADD __in1 = 0;
T_ADD __in2 = 0;
T_ADD __out = 0;
out.write(__out);
wait();
// infinite loop
while(1) {
__in1 = in1.read();
__in2 = in2.read();
__out = __in1 + __in2;
out.write(__out);
wait();
}
}
main.cpp
main.cpp
stimgen.cpp
stimgen.cpp
adder.cpp
adder.cpp
adder.h
adder.h
monitor.cpp
monitor.cpp
monitor.h
monitor.h
stimgen.h
stimgen.h
Adder
in1
in2
out
Response
Monitor
re
Stimulus
Generator
a1
a2
main.cpp
clk
70
IIS
Fraunhofer
Institut
FhC llS-A, 2001
$lMl0 fK8Ml0 81 l090l
typedef sc_int<8> T_ADD;
SC_MODULE(adder) {
// Clock introduced
sc_in_clk clk;
// Input ports
sc_in<T_ADD> in1;
sc_in<T_ADD> in2;
// Output port
sc_out<T_ADD> out;
// internal signal
sc_signal<T_ADD> sum;
// Constructor
SC_CTOR(adder){
SC_METHOD(add);
sensitive << in1 << in2;
SC_METHOD(reg);
sensitive_pos << clk;
}
void add();
void reg();
};
main.cpp
main.cpp
stimgen.cpp
stimgen.cpp
adder.cpp
adder.cpp
adder.h
adder.h
monitor.cpp
monitor.cpp
monitor.h
monitor.h
stimgen.h
stimgen.h
Adder
in1
in2
out
Response
Monitor
re
Stimulus
Generator
a1
a2
main.cpp
clk
71
IIS
Fraunhofer
Institut
FhC llS-A, 2001
$lMl0 fK8Ml0 81 l090l
// Implementation file adder.cc
#include systemc.h
#include adder.h
void adder::add()
{
T_ADD __in1 = in1.read();
T_ADD __in2 = in2.read();
sum.write( __in1 + __in2 );
}
void adder::reg()
{
out.write( sum );
}
main.cpp
main.cpp
stimgen.cpp
stimgen.cpp
adder.cpp
adder.cpp
adder.h
adder.h
monitor.cpp
monitor.cpp
monitor.h
monitor.h
stimgen.h
stimgen.h
Adder
in1
in2
out
Response
Monitor
re
Stimulus
Generator
a1
a2
main.cpp
clk
72
IIS
Fraunhofer
Institut
FhC llS-A, 2001
$lMl0 fK8Ml0 $0f00800l
73
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Fraunhofer
Institut
FhC llS-A, 2001
008
Topic Unit

2
Simple Example 4
Resources 5
74
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Institut
FhC llS-A, 2001
$8l0M0 N00 $ll0
www.systemc.org
download
news
forum (mailing list)
FAQs
75
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1f8ll l f0f00
For SystemC training in Munich, Erlangen, or on-site
look at:
http://www.iis.fhg.de/kursbuch/kurse/systemc.html
Next scheduled training: Nov 21-23 in Munich,
Germany
Covers SystemC 2.0

5starts Bernhard Introduction

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