Operating Systems: Internals and Design Principles, 7th Edition

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Chapter 1 Computer Systems Overview

TRUE/FALSE QUESTIONS 1 The processor controls the operation o! the comp"ter and per!orms its data processing !"nctions#

Tr"e $alse % It is not possible !or a comm"nications interr"pt to occ"r &hile a printer interr"pt is being processed# 'ns&er: Tr"e

$alse ( ' system b"s trans!ers data bet&een the comp"ter and its e)ternal en*ironment# 'ns&er: Tr"e

$alse + Cache memory is in*isible to the OS#

Tr"e $alse , -ith interr"pts, the processor can not be engaged in e)ec"ting other instr"ctions &hile an I.O operation is in progress# 'ns&er: Tr"e

$alse / Digital Signal Processors deal &ith streaming signals s"ch as a"dio and *ideo#

Operating Systems: Internals and Design Principles, 7th Edition

Tr"e $alse 7 The !etched instr"ction is loaded into the Program Co"nter# 'ns&er: Tr"e

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$alse 0 Interr"pts are pro*ided primarily as a &ay to impro*e processor "tili1ation#

Tr"e $alse 2 The interr"pt can occ"r at any time and there!ore at any point in the e)ec"tion o! a "ser program#

Tr"e $alse 13 O*er the years memory access speed has consistently increased more rapidly than processor speed# 'ns&er: Tr"e

$alse 11 'n S4P can be de!ined as a stand-alone comp"ter system &ith t&o or more similar processors o! comparable capability#

Tr"e $alse 1% The Program Stat"s -ord contains stat"s in!ormation in the !orm o! condition codes, &hich are bits typically set by the programmer as a res"lt o! program operation# 'ns&er:

Operating Systems: Internals and Design Principles, 7th Edition

Tr"e

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$alse 1( 'n e)ample o! a m"lticore system is the Intel Core i7#

Tr"e $alse 1+ In a t&o-le*el memory hierarchy the 5it 6atio is de!ined as the !raction o! all memory accesses !o"nd in the slo&er memory# 'ns&er: Tr"e

$alse 1, The operating system acts as an inter!ace bet&een the comp"ter hard&are and the h"man "ser#

Tr"e $alse !ULTI"LE C#OICE QUESTIONS 1

Operating Systems: Internals and Design Principles, 7th Edition

The !o"r main str"ct"ral elements o! a comp"ter system are: ' Processor, 4ain 4emory, I.O 4od"les and System 7"s 7 Processor, I.O 4od"les, System 7"s and Secondary 4emory C Processor, 6egisters, 4ain 4emory and System 7"s D Processor, 6egisters, I.O 4od"les and 4ain 4emory ' % The 8888888888 holds the address o! the ne)t instr"ction to be !etched# ' 'cc"m"lator 9'C

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7 Instr"ction 6egister 9I6 C Instr"ction Co"nter 9IC D Program Co"nter 9PC D

( The 8888888888 contains the data to be &ritten into memory and recei*es the data read !rom memory# ' I.O address register 7 memory address register C I.O b"!!er register D memory b"!!er register D + Instr"ction processing consists o! t&o steps:

Operating Systems: Internals and Design Principles, 7th Edition

' !etch and e)ec"te

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7 instr"ction and e)ec"te C instr"ction and halt D !etch and instr"ction ' , The 88888888888 ro"tine determines the nat"re o! the interr"pt and per!orms &hate*er actions are needed# ' interr"pt handler 7 instr"ction signal C program handler D interr"pt signal ' / The "nit o! data e)changed bet&een cache and main memory is 8888888888 # ' block si1e 7 map si1e C cache si1e D slot si1e ' 7 The 888888888 chooses &hich block to replace &hen a ne& block is to be loaded into the cache and the cache already has all slots !illed &ith other blocks# ' memory controller

Operating Systems: Internals and Design Principles, 7th Edition

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mapping !"nction C &rite policy D replacement algorithm D 0 8888888888 is more e!!icient than interr"pt-dri*en or programmed I.O !or a m"ltiple-&ord I.O trans!er# ' Spatial locality 7 Direct memory access C Stack access D Temporal locality 7

2 The 8888888888 is a point-to-point link electrical interconnect speci!ication that enables high-speed comm"nications among connected processor chips# ' :PI 7 DD6( C ;6<' D IS6 '

Operating Systems: Internals and Design Principles, 7th Edition

13 Small, !ast memory located bet&een the processor and main memory is called: ' 7lock memory

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7 Cache memory C Direct memory D -O64 memory 7 11 In a "niprocessor system, m"ltiprogramming increases processor e!!iciency by: ' Taking ad*antage o! time &asted by long &ait interr"pt handling 7 Disabling all interr"pts e)cept those o! highest priority C Eliminating all idle processor cycles D Increasing processor speed ' 1% The t&o basic types o! processor registers are: ' <ser-*isible and "ser-in*isible registers 7 Control and "ser-in*isible registers C Control and Stat"s registers D <ser-*isible and Control.Stat"s registers D 1( -hen an e)ternal de*ice becomes ready to be ser*iced by the processor the de*ice sends a9n 888888888 signal to the processor# ' access 7 halt C

Operating Systems: Internals and Design Principles, 7th Edition

handler

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D

interr"pt D 1+ One mechanism Intel "ses to make its caches more e!!ecti*e is 8888888888 , in &hich the hard&are e)amines memory access patterns and attempts to !ill the caches spec"lati*ely &ith data that is likely to be re="ested soon# ' mapping 7 handling C interconnecting D pre!etching D

1, ' 8888888888 organi1ation has a n"mber o! potential ad*antages o*er a "niprocessor organi1ation incl"ding per!ormance, a*ailability, incremental gro&th, and scaling# ' temporal locality 7 symmetric m"ltiprocessor C direct memory access D processor stat"s &ord 7 S#ORT ANS$ER QUESTIONS 1 The in*ention o! the 888888888 &as the hard&are re*ol"tion that bro"ght abo"t desktop and handheld comp"ting# microprocessor % To satis!y the re="irements o! handheld de*ices, the classic microprocessor is gi*ing &ay to the 888888888 , &here not >"st the CP<s and caches are on the same chip, b"t also many o! the other components o! the system, s"ch as DSPs, ?P<s, I.O de*ices and main

Operating Systems: Internals and Design Principles, 7th Edition

memory# System on a Chip 9SoC ( The processing re="ired !or a single instr"ction is called a9n 8888888888 cycle# instr"ction + The !etched instr"ction is loaded into the 8888888888 # Instr"ction 6egister 9I6

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, -hen an e)ternal de*ice is ready to accept more data !rom the processor, the I.O mod"le !or that e)ternal de*ice sends an 8888888888 signal to the processor# interr"pt re="est / The 8888888888 is a de*ice !or staging the mo*ement o! data bet&een main memory and processor registers to impro*e per!ormance and is not "s"ally *isible to the programmer or processor# cache 7 E)ternal, non*olatile memory is also re!erred to as 8888888888 or a")iliary memory# secondary memory 0 -hen a ne& block o! data is read into the cache the 8888888888 determines &hich cache location the block &ill occ"py# mapping !"nction 2 In a 888888888 m"ltiprocessor all processors can per!orm the same !"nctions so the !ail"re o! a single processor does not halt the machine# symmetric 13 ' 8888888888 comp"ter combines t&o or more processors on a single piece o! silicon# m"lticore 11 ' Control.Stat"s register that contains the address o! the ne)t instr"ction to be !etched is called the 888888888# Program Co"nter 9PC 1% Each location in 4ain 4emory contains a 888888888 *al"e that can be interpreted as either an instr"ction or data#

Operating Systems: Internals and Design Principles, 7th Edition

' n binary n"mber

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1( ' special type o! address register re="ired by a system that implements "ser *isible stack addressing is called a 8888888888 # stack pointer 1+ 6egisters that are "sed by system programs to minimi1e main memory re!erences by optimi1ing register "se are called 8888888888 # "ser-*isible registers 1, The concept o! m"ltiple programs taking t"rns in e)ec"tion is kno&n as 8888888888# m"ltiprogramming