Digital Electronics

http://ptuece.loremate.com/die/node/11 March 7, 2012

Q 40. Draw the logic symbols for T and RS flip-flops. Explain the function of each type of flip-flop. Ans. RS Flip-flop: Its logic symbol is as shown in fig. Its internal structure is as shown: Its functioning can be explained with the help of truth table as shown: Case I. When both the inputs i.e. S = R = 0 The data inside the flip-flop do not change i.e. if 0 was the previous data we get 0 as output data and if 1 was previously stored in flip-flop we get 1 as output data. Hence, no change state. Case II. When the inputs are : S = 0 and R = 1. The flip-flop output is always 0 i.e. if the previously stored data was 0 or 1 we always get 0 output. Hence, Reset condition or state. Case III When the inputs are S = 1 and R = 0 The flip flop output is always 1 i e if the previously stored data was 0 to 1 we always get 1 output Hence set state Case IV When the inputs are S = 1 and R = 1 The flip-flop outputs Q and comes same which is not possible i e Q = . Hence intermediate state. T-flip-flop: T flip-flop is also known as Toggle flip-flop It is a modification of the JK flipflop The T flip flop is obtained from a JK flip flop by connecting both inputs, J and K together When T = 0, both AND gates are disabled and hence these is no change in the output When T = 1 (i.e. J = 1 and K = 1) output toggles i.e. with the

passage of each clock the output changes from 0 to 1 and 1 to 0 i.e. it toggles Its truth table is as shown in fig Q 41. Draw the circuit of an S-R flipflop using NAND gates. Modify it to include clock Derive J-K circuit from S-R flip-flop circuit and explain its truth table Ans. S-R Flip-flop using NAND gates: Case l :When S = 0,R = 0 When any one input of NAND gate is zero, its output is forced to be 1. Now path Q and Q will be forced to become 1, which is not possible. Hence, Race condition or invalid state. Case2: When S = 0,R = 1 When S = 0, it will force Q to be 1 and hence both inputs R and Q become 1 and cause Q to be 0. It is called Reset condition. V Case3: When S = 1, R = 0 When R = 0, it will force Q to be 1. Hence both inputs S and Q will be 1 and cause Q to be 0. It is called set condition. V Case4: When S = 1, R =1 In this case, there will be no change in outputs. S-R Flip-flop including clock: Derive J-K flip-flop from S-R flip-flop The truth table for S-R to J-K conversion is as shown: K-maps Logic diagram: Q 42. Design a J-K counter that goes through states 2, 4, 5, 7, 2, 4 is the

counter-self starting. Ans. K-maps Circuit Q 43. Perform the following conversions T flip-flop to D flip-flop. Ans. T flip-flop to D flip-flop: Truth table for conversion: K-map for T:

Implementation of circuit diagram: Q 44. Twisted ring counter is also known as Johnson counter. It is an application of shift register. Following figure shows the circuit diagram for its operation. Ans. Operation : Initially a short negative pulse is provided to clear all the which resets the data to 000 Q 45. Design a synchronous decade counter to count in the following sequence 1, 0, 2, 3, 4, 8, 7, 6, 5 Ans. The excitation truth table for synchronous decade counter to count the sequence 1, 0, 2, 3, 4, 8, 7, 6, 5 is as shown: Put all others as dont care conditions i.e. 10, 11, 12, 13, 14 and 15 to be dont care. K-map for TA:

K-map for TB:

K-map for TC:

K-map for TD:

Q 46. Write short note on the following: Counter design with state equation and state diagrams. Ans. Counter designing make use of static diagrams and state equations. State Diagram : The graphical representation of different states of a counter is known as state diagram. Let us consider an example of 3 bit Ripple counter (up and down)

The numbers written inside the circles are the state numbers and the arrows shows the direction of counter. In fig. (a) 0 is the initial state i.e. counter starts from 0 and count upto 7 then again 0 and so on. So it is up counter. Similarly, in fig. (b) initial state is 7so it starts from 7 and goes .to 0 then again 7and so on. So it is a down counter. State equation : A state equation is also known as application equation. It is an algebric expression that specifies the conditions for a flipflop state transition. The left side of the equation represents the next state of the

flip-flop and the right side gives a boolean function that specifies the present state conditions that make the next state equal to 1. The state equation can be derived from the state table or logic diagram. Q 47. What is race around condition in JK flip flop? How it is eliminated? Ans. RaceAround Condition : When J and K both inputs are high i.e. J = K = I, the output will keep toggling indefinitely. This multiple toggling in J-K F/F is called Race-Around Condition. It can be eliminated by using master slave J-K flip-flop. 1. Master slave J-K Flip-flop

2. By using RC triggering circuit: Q 48. Write note on: 4 bit binary shift register. Ans. 4 bit binary shift Register: This type of Shift Register allows shifting either to left or right side. Working Fig shows the bidirectional shift register When signal IS High AND gates 1 3, 5, 7 are enabled and it enables the data shifting towards right Whereas when signal is Low AND gates 2, 4 6, 8 are enabled the data shifting is towards left Then the Q states of each flip-flop passes through the A and KA input of each proceeding flip flop When clock pulse arrives the data shift one place to right or left depending on . Q 49. Design a mod 30 synchronous up counter. Ans. From 0 to 29 the states are valid states and 30 and 31 states are

invalid states. Circuit diagram Using T flip flop is as shown in figure MOD 30 Synchronous Counter Q 50. Design a BCD counter using JK flip-flops. Ans. The BCD decade counter counts from 0000 to 1001 as shown in diagram. The invalid states 1010 to 1111 should given next states as 0000 which is done by reset logic connected to clear input of all the flip-flops.

Truth table of BCD counter: Reset logic output for clear. K-map: Q 51. Design an up-down counter using JK Flip-flop to count 0, 2, 3, 6, 4, 0. Ans. Up-down counter counts (0, 2, 3, 6, 4, 0,......). K-maps Circuit diagram Q 52. Design an up-down counter using D-flip-flops to count 0, 3, 2, 6, 4, 0,........ Ans. K-maps Implementation of circuit: