ECE2274 Pre-Lab for MOSFET logic NAND Gate, NOR Gate, and CMOS Inverter 1.

NMOS NAND Gate Use Vdd = 9.0Vdc. For the NMOS NAND gate shown below gate, using the IRF150 MOSFET edit the model such that Vto = 2.0 and RS = 4 in PSpice.The input logic 1 = 9 volt and ground as a logic 0. Make a truth table showing the four possible combinations of Vin1 and Vin2 and the outputs. Choose Rd (drain current limit resistor) such that the drain currents of the NMOS devices will be about 30mA when the Vout is in a low state. Then run a DC Bias Point simulation (use IRF150 in Pspice) on your design with the four possible input combinations for Vin1 and Vin2 to verify your gate. Observe the output voltage value for each input combination. Print your circuit schematic showing voltages for all four input combination.

Vdd

Rd Vout D NMOS G S Q2 G S D NMOS

Vin1

Q1

Vin2

Nmos NAND GATE

2. NMOS NOR Gate Use Vdd = 9.0Vdc. Design an NMOS NOR gate using the IRF150 MOSFET edit the model such that Vto = 2.0 and RS = 4 in Pspice. Limit the drain current total to 30mA with a drain resistor. Show all work for your design and drawing. Then simulate your design in PSpice with DC Bias Point simulations as you did for the NAND gate. Print out your circuit schematic showing voltages for all four input combination. Also, fill in the truth table with all of the Bias Point simulation voltage values. Page 1 of 6 Lab 10 summer 12 Revised: July 16, 2012

3. CMOS Inverter Use VDD = 9.0Vdc. Design a CMOS inverter using a NMOS and PMOS FET. The drain current will be limited by the two 100 source resistors in the lab. Limit the LED current to 10mA thru the LED assume that LED forward voltage drop is 2V. The MOSFETs that we use in the lab both have a VGS threshold voltage of about 2.0Vand RS = 4. Assume that there is a input voltage level 2.0V < Vin < VDD 2.0V that will turn on both FETs at the same time. Edit the MOSFETmodels such that Vto = 2.0 and RS = 4 in Pspice for both.This will cause a large current flow that could damage the two devices. Because there is period of time when both devices on we will use a 1kHz triangle waveform as input so the time the devise send in a high current state will short in pspice. Use PSPICE to plot the input triangle waveform, output voltage waveform, and the current thru the devices. Plot CMOS Transfer charasistic curve DC sweep Vin from 0V to 9V. Plot Vout vs Vin mark on plot VOH , VOL , VIL and VIH.

VDD Vin

9Vdc 1kHz amplitude 0v to 9v Triangle wave Vpluse 0V, 9V Tr=0.5ms Tf=0.5ms Per=1ms Td=0, Pw =1ns Pspice (IRF914) Lab (TP0606) Psice (IRF150) Lab (2N7000) 1 ohm Vto=-2 volts RS = 4 ohms Vto = 2 volts RS = 4 ohms

Q1 PMOS Q2 NMOS shunt Pspice IRF 9140 PMOS

Pspice IRF 150 NMOS

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Schematic Anode V+

PSPICE

DC LED

1.2Vdc Flat 1N4002

Cathode V-

Cathode VAnode V+

Cmos Transfer charasistic.

Required Attachments: NAND Truth table Four schematics with voltages and currents of nodes and branches NOR Truth table Four schematics with voltages and currents of nodes and branches 5. Cmos Transfer charasistic curve Page 4 of 6 Lab 10 summer 12 Revised: July 16, 2012

Laboratory Exercise MOSFET logic NAND GATE, NOR GATE, and CMOS inverter

1. Build the NAND gate, but add a LED. Measure the output voltage levels with and without a LED connected to ground. You will use the LED to verify the NAND gates operation. Try all of the input combinations. 2. Build the NOR gate that you designed in the Pre-Lab. Use VDD = 9.0Vdc Again, use an LED with current limiting resistor in series with it to determine the output states. Verify the truth table for a NOR gate. 3. Build CMOS Inverter with both the 100 drain current limit resistors. Use the DC sweep to plot the Cmos inverter no-load transfer charasistic curve, print the plot and mark the VOH , VOL , VIL and VIH DATA SHEET MOSFET logic NAND GATE, NOR GATE, and COMS Inverter

1. NAND GATE Vin1 0Vdc 0Vdc 9Vdc 9Vdc Vin2 0Vdc 9Vdc 0Vdc 9Vdc Vout Vout with LED

2. NOR GATE Vin1 0Vdc 0Vdc 9Vdc 9Vdc Vin2 0Vdc 9Vdc 0Vdc 9Vdc Page 5 of 6 Lab 10 summer 12 Revised: July 16, 2012 Vout Vout with LED

3. CMOS Inverter

VDD 100 current limit G Q1 S PMOS D

Vin

Q2 G 100 Shunt and current limit

D NMOS S

Vout

Table CMOS inverter no load. Vin 0v 9v

Vout

From DC sweep of no-load CMOS inverter Vout to Vin Mark on plot, include the plot. Name Voltage VOH VOL VIL VIH

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