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In the late 70s as the era of LSI and VLSI began, NMOS became the fabrication technology choice. Later the design flexibility and other advantages of the CMOS were realized, CMOS technology then replaced NMOS at all level of integration. The small transistor size and low power dissipation of CMOS circuits, demonstration principal advantages of CMOS over NMOS circuits.
NMOS Inverter
For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. Once the operation and characterization of an inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.
NMOS Inverter
If VI <VNT, the transistor is in cutoff and iD =0, there is no voltage drop across RD, and the output voltage is Vo=VDD=VDS If VI >VNT, the transistor is on and initially is biased in saturation region, since
+
RD =VDD=VDS
VDS >VGS-VTN. As the input voltage increasesVGS=V (VGS) , the drain to source + voltage (VDS) decreases and the transistor inter into the non saturation region.
RD =VDD=VDS
VDSVGS-VTN.
the Q-point of the transistor moves up the load line. At the transition point, we have
VGS=V
+
VGS=V
+
VGS=V
+
16.9
where Vo, and VI, are the drain-to-source and gate-to-source voltages, respectively, at the transition point. By substituting Equation (16.9) into (16.8), the input voltage at the transition point can be determined as,
which relates the output and input voltages as long as the transistor is biased in the saturation region.
RD =VDD=VDS
VGS=V
+
VTN)2
VGS=V
+
RD =VDD=VDS
Nonsaturation region
iD = Kn[2(vI - VTN)VO Vo2]
The iD versus vDS characteristics are shown in Figure 16.7(b), which indicates that this device acts as a nonlinear resistor.
NMOS Inverter with Enhancement Load/Saturated (driver at the non saturation region))
As the input voltage becomes greater than VIt the driver transistor Q- point continues to move up the load curve and the driver becomes biased in the nonsaturation region. Since the driver and load drain currents are still equal, or iDD = iDL, we now have KD[2(VGSD - VTND)VDSD - VDSD2] = KL(VDSL -VTNL)2 Substituting VGSD=VI and VDSD=VO and VDSL= VDD-VO we get KD[2(vl -VTND) Vo- VO2 ] = KL(VDD - VO - VTNL)2
The ratio KDIKL is the aspect ratio and is related to the width-to-length parameters of the driver and load transistors.
The slope of the VTC curves in the saturation region is known as inverter gain and is given by dVo/dVI= - KD/KL If the inverter gain is greater then unity, the inverter logic gate is belonged to restoring logic family.
VO,max= VOH =VDD-VTNL the output high voltage VO is degraded by the threshold voltage.
The term depletion mode means that a channel exists even with zero gate voltage.
KD(VGSD-VTND) Or
= KL(VGSL-VTNL)2
KD/KL(VI-VTND)=-VTNL Implies that input voltage is constant as the Q-point passes this region. If we further increased the input voltage, the drive is biased in the nosaturation region while load is in saturation region. The Q-point moves between C and D on the load curve. For the input/output characteristics we equate two drain current equation KD[2(VGSD - VTND)VDSD - VDSD2] = KL(VDSL VTNL)2 Which becomes KD/KL[2(VI-VTND)VO-Vo2]=-(-VTNL)2 Implies that input and output voltages are not linear in this region.
VO)-VDD VO)2]
Which relates the input and output voltage as long as the driver is biased in saturation region and
The Figure demonstrate in present configuration more abrupt VTC transition region can be achieved even though the W/L ratio for the output MOSFET is small.
The source of capacitance CT2 and CT3 are the transistor input capacitances and parasitic capacitances due to interconnect lines between the inverter stages.
The constant current over a wide range of VDS provided by the depletion load implies that this type of inverter switch a capacitive load more rapidly than the other two types inverter The rate at configurations.
enhancement load
depletion load
1160W
825W
200W
NMOS NOR gate: Special case when all inputs are at logic 1
When A=B=logic 1 Both driver transistors are switched into nonsaturation region and load transistor is biased in saturation region. We have iDL=iDA+iDB By substituting the values of current equation we can write as,
NMOS NOR gate can be constructed by connecting an additional driver transistor in parallel with a depletion load inverter. The output of a NOR gate is only high when both inputs are at logic 0(low)i.e. If A=B=logic 0, Then both driver transistors MDA and MDB are in cut off mode and V0=VDD (logic 1) For all other possible inputs V0= 0 (logic 0). For example, If A=high (logic1) and B=low (logic0) Then MDB is in cut off mode and remaining circuit behave as depletion load inverter. However, when both driver transistors are in active mode the value of the output voltage logic 0) is changed.
2(K /K )[2(V
D L
2 DD-VTND)V0-VO )
Conclusion: The above equation suggested that when the both the driver are in conducting mode, the effective aspect ratio of the NOR gate is double. This further suggested that output voltage becomes slightly smaller when both inputs are high. Because higher the aspect ratio lower the output.
For the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased.
For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased.
.