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Datapath and control design: You are given two 4-bit unsigned numbers, P and Q. You need to compare them and deposit the smaller in SMALL_REG and the bigger in BIG_REG. Given on the next page is a complete data path. Notice that you can bring either P or Q on bus #1 (B_ONE) or bus #2 (B_TWO). SMALL_REG is only tied to B_ONE where as BIG_REG is only tied to B_TWO.
3.1 3.1.1
PQL
/RESET
START
Load P (from B_ONE) into Small. Load Q (from B_TWO) into BIG.
I
Initial
START
Compare P with Q
CPQ
QPL
Load Q (from B_ONE) into Small. Load P (from B_TWO) into BIG.
on B_ONE on B_TWO
Complete the one-hot implementation of the above 4-state state machine on page 3. Before you produce the outputs, answer the following questions.
Can we say that whenever we put P or Q on one of the two buses, we may put the other on the other bus?
YES / NO
Can we say that, in the initial state, we may drive the buses even though it is not necessary? YES / NO Can we say that we either load both SMALL_REG and BIG_REG or load none? YES / NO
EE457 Homework 1
EE457 Homework 1
EE457 Homework 1
EE457 Homework 1
3.2 3.2.1
The state machine design in 1.1 above is a ___________ (Mealy / Moore) as the outputs generated are not influenced by the inputs. The outputs are completely determined by the current state. Let us now reduce the states by combining CPQ and PQL into CPQL compare and load. The load operation is conditional in the CPQL state as can be seen below. This 3-state state machine is a ___________ (Mealy / Moore). Complete the state diagram below.
/RESET
START
I
Initial
CPQL
START
If appropriate Load P (from B_ONE) into Small. Load Q (from B_TWO) into BIG.
QPL
Load Q (from B_ONE) into Small. Load P (from B_TWO) into BIG.
3.2.2 3.2.3
Complete the one-hot implementation of the 3-state state machine on page 6 . Complete the waveform on page 7 .
EE457 Homework 1
EE457 Homework 1
EE457 Homework 1
ee102_midterm2_Sp2005.fm
The previous two design are again given below with the VDD/GND connections removed. Now again build two non-inverting 2-to-1 muxes with low active enable by completing the designs. You can use additional inverters if you need. Are the two designs functionally identical (meaning one can be used to replace the other)? YES / NO
I0
/I0
Y I1
/I1
/Y
VDD
4 pts 2.1
Example: A7A6A5A4A3A2A1A0 = 00101001 = 41 decimal , B7B6B5B4B3B2B1B0 = 01001011 = 75 decimal . After chopping off the least significant two bits, we have A7A6A5A4A3A2 = 001010 and
EE102L Midterm #2 - Spring 2005 2 / 10
3/29/06
ee102_midterm2_Sp2005.fm
Since A1A0 =/= 0 0, let us increment A7A6A5A4A3A2 by 1 to 001011 and try to see (i) if 001011 exceeded 010010 (ii) if 00101100 (44 decimal) is divisible by 5. We know that 6010 is the smallest number between 4110 and 7510 which is divisible by 2010 .In this example how many different Au00 values are tested to see if they are actually divisible by 510 ? _____ What are they? 44,
B7B6B5B4B3B2 = 010010 .
18 pts 2.2
After reading the datapath and completing the state diagram later in this question, return to this question.
Consider the three cases. Assume that START and ACK are active all the time. (i) A6A5A4A3A2A1A0 = 0001110 = 14 decimal , B6B5B4B3B2B1B0 = 1001011 = 75 decimal (ii) A6A5A4A3A2A1A0 = 0010011 = 19 decimal , B6B5B4B3B2B1B0 = 1001011 = 75 decimal (iii) A6A5A4A3A2A1A0 = 0011110 = 30 decimal , B6B5B4B3B2B1B0 = 0011111 = 31 decimal
Waveforms for item (i) has been completed. You need to complete waveforms for items (ii) and (iii).
Here, we are plotting only the symbolic state, AU&0&0 (Au concatenated with 0 0, and the X. \D means decimal. Each waveform starts with the Initial (I) state and ends with the Initial state (I).
clock_edge 10 clock_edge 12 clock_edge 13 clock_edge 11 clock_edge 14 clock_edge 15 clock_edge 0 clock_edge 1 clock_edge 2 clock_edge 3 clock_edge 4 clock_edge 5 clock_edge 6 clock_edge 7 clock_edge 8 clock_edge 9
SysClk
STATE Au&0&0
CI 12\D
CBUX 16\D
DIV
INC
CBUX
DIV 20\D
FND
16\D
11\D
6\D
1\D
-4\D(124)\D0
20\D
15\D
10\D
5\D
0\D
STATE
CI 16\D
CBUX
Item (ii)
Au&0&0
Item (iii)
STATE Au&0&0
CI 28\D
CBUX
3/29/06
3 / 10
ee102_midterm2_Sp2005.fm
Bu_in
5 Bl_in 2
Incrementer
Bu_Load
I 7
I+1
Y I1 S
I0 Y I1 S
Au_Load
SysClk
N.C.
Bu (B6B5B4B3B2) 2
Al_in (A_lower_in)
2 7
No-Connection
SysClk
5
Bu - Register
Al_Load
X-5
Check A1 A0
A1A0 =/= 0 0 (A1A0 isnt 0 0)
S0
Y SysClk
Au
5
Bu
5
X - Register
Comparator
Au > Bu Au = Bu Au < Bu
5 = 00001012 Subtractor
X>5
5 = 00001012 Comparator
X=5 X< 5
Ain0 A1 A 0
X-5
Given below on the right-side is a portion of the above data-path. Show detailed design of this portion in the left-side box.
D Q A0
A1A0 =/= 0 0
Ain1 Al_Load
Ain0
CLK D Q A1
SysClk
DE CLK
Ain1
CLK
Check A1 A0
A1A0 =/= 0 0 (A1A0 isnt 0 0)
Al_Load
SysClk
3/29/06
X <= X
X_MUX_S1 X_MUX_S0
S1
I3
I2
I1
I0
er) Low _ A Al (
DE SysClk CLK
A1 A0
7 7
Xin
Au (A6A5A4A3A2)
I0
Y I1 S
I0
ee102_midterm2_Sp2005.fm
2.4
Complete the state diagram below for the above design. I CI CBUX DIV INC FND NSN = = = = = = = Initial State Compare A1A0 with 0 0 and Increment Au if needed Compare Au with Bu and Update X with Au&0&0 Divide by 5 by repetitively subtracting 5 Increment Au by 1 Found the number divisible by 2010 No Such Number
All the states and the state transition arrows are in place. Complete the missing state transition conditions. Also fill-in RTL statements such as the following in appropriate states: 18 pts Au <= Au_in; Bu <= Bu_in; Al <= Al_in; Au <= Au + 1; X <= Au&0&0 (Au concatenated with two zeros); X <= X - 5; START I START CI 1 CBUX
RESET
1 DIV INC
FND
NSN
ACK
3/29/06
5 / 10
ee102_midterm2_Sp2005.fm
8 2.5 pts
Complete NSL only for the two flip-flops QDIV and QCBUX below. You do not have to complete for the rest of the Flip-Flops (QI, QCI, QINC, QFND, QNSN).
NSL NSL
QDIV SysClk
QCBUX
16 pts 2.6
Draw OFL to generate all outputs below. Complete the following table which helps in producing X_MUX_S1, X_MUX_S0.
Portion of OFL to help generate X_MUX_S1, X_MUX_S0 QCBUX QDIV State / RTL
X_MUX_S0
1 0 0
0 1 0
CBUX X <= Au&0&0 Divide by 5 X <= X -5 Some other State Dont change X
X_MUX_S1
Au_Inc
( 6 points) 3 min.
Sampling (capturing) ____________________ (asynchronous / synchronous) inputs can cause a D-FF to go into metastability. The probability of conveying a metastable value to the rest of the design can be ______________________ (reduced / increase) by adding a second level sample+hold flip-flop. The sample and hold flip-flop is always clocked by the _____________ (senders clock / receivers clock).
3/29/06
6 / 10
ee102_midterm2_Sp2005.fm
( 8 points)
min.
Design a special down counter which counts down (7, 6, 5, ...). However, it shall always skip 4. So the sequence shall be 7, 6, 5, 3, 2, 1, 0, 7, 6, 5, 3, 2, 1, 0, 7, 6, 5, 3, 2, 1, 0, ...... Use the mux. to skip 4.
Subtracter A0 A1 A2 1 0 0 B0 B1 B2 Mux S0 S1 S2 I00 I01 I02 Y0 Y1 I10 Y2 I11 I12 S
Register
D Q D Q D Q
LSB
Q0 Q1 Q2
SysClk
5
8 pts 5.1
( 8 + 6 + 8 + 6 + 6 = 34 points)
30
min.
Reproduced below is the state diagram for the divider from your classnotes. A student has modified state transition conditions on the two diverging arrows on the "C" state as shown.
~RESET START X>= Y
Note
START
X>Y
I
(INITIAL) START
END
If it works, explain how it is better or worse in performance? If it does not work, state why it does not work.
EN D
X> =Y
X>Y
Note
>= X Y
(DONE)
Classnotes design
6 pts 5.2
~RESET
In light of the above question, can you suggest an improvement to the Moore machine for the divider (reproduced from the classnotes below) by modifying the state transition conditions only?
START 1
I
(INITIAL) START
(COMPARE)
X>= Y
X <== X - Y; Q <== Q + 1;
X> =Y
EN D
END
>= X Y
(DONE)
Classnotes design
3/29/06
7 / 10
ee102_midterm2_Sp2005.fm
8 5.3.1 pts
~RESET
Miss Trojan suggested a better Moore machine for the divider (better than the one in the classnotes and reproduced above) as shown below. Using the example 40 / 2 = 20, R=0, explain START "If" removed X > = Y why this is better than our classnotes design. Note: "+"
I
START (COMPARE and UPDATE) X <== X - Y; Q <== Q + 1;
(INITIAL)
X>=Y
(UNDO)
X <== X + Y; Q <== Q - 1;
END 1
Note: "-"
EN D
(DONE)
6 pts 5.3.2
~RESET
Mr. Trojan says that there is still a little more to improve by playing with the state transition arrows and conditions! Can you guess what is in his mind by completing the design below?
START
Using the example, 40 / 2 = 20, R=0, explain why this is little more better than Miss Trojans design.
I
(INITIAL) START
(UNDO)
X <== X + Y; Q <== Q - 1;
END 1
Note: "-"
EN D
(DONE)
6 pts 5.3.3
Mr. Trojan says that the resulting datapath of Miss Trojans design or his design is a little more expensive. Please explain. ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________
( 6 points) 3 min.
Whether a signal is 3.85V or 4.25V, a/an Clock _______________________ (logic analyzer / oscilloscope) records it as a logic 1. Your lab partner said that the clock signal on the FPGA board has a lot of "ringing" (overshoot and undershoot). To identify this problem, he used a/an ________ ___________________ (logic analyzer/oscilloscope). If you want to measure the OFL (output function logic delay) using a logic analyzer, would you use it timing analyzer mode or state analyzer mode? timing analyzer mode / state analyzer mode
3/29/06 EE102L Midterm #2 - Spring 2005 8 / 10