Ds191 XC7Z030 XC7Z045 Data Sheet

Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics
DS191 (v1.1) August 31, 2012 Advance Product Specification
Introduction
Zynq-7000 All Programmable SoCs are available in -3, -2, and -1 speed grades, with -3 having the highest performance. Zynq-7000 device DC and AC characteristics are specified in commercial, extended, and industrial temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices are available in the extended or industrial temperature ranges. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Zynq-7000 AP SoC (XC7Z030 and XC7Z045) data sheet, part of an overall set of documentation on the Zynq-7000 devices, is available on the Xilinx website at www.xilinx.com/zynq. All specifications are subject to change without notice.
DC Characteristics
Table 1: Absolute Maximum Ratings (1)
Symbol
Processing System (PS) VCCPINT VCCPAUX VCCPLL VCCO_DDR VCCO_MIO(2) VPREF VPIN(3)(4)(5) PS primary logic supply PS auxiliary supply voltage PS PLL supply PS DDR I/O supply PS MIO I/O supply PS input reference voltage PS DDR and MIO I/O input voltage PS DDR and MIO I/O input voltage for VREF and differential I/O standards 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1.1 2.0 2.0 2.0 3.6 2.0 VCCO + 0.5 2.625 V V V V V V V V
Description
Min
Max
Units
Programmable Logic (PL)

VCCINT VCCAUX VCCBRAM VCCO VCCAUX_IO VREF VIN
(3)(4)(5)
Internal supply voltage Auxiliary supply voltage Supply voltage for the block RAM memories Output drivers supply voltage for 3.3V HR I/O banks Output drivers supply voltage for 1.8V HP I/O banks Auxiliary supply voltage Input reference voltage I/O input voltage I/O input voltage for VREF and differential I/O standards
0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5
1.1 2.0 1.1 3.6 2.0 2.06 2.0 VCCO + 0.5 2.625 2.0
V V V V V V V V V V
VCCBATT
Key memory battery backup supply
Copyright 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Zynq, Virtex, Artix, Kintex, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, Cortex-A9, CoreSight, Cortex, PrimeCell, ARM Powered, and ARM Connected Partner are trademarks of ARM Ltd. All other trademarks are the property of their respective owners.
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 1: Absolute Maximum Ratings (1) (Contd)
Symbol GTX Transceiver
VMGTAVCC VMGTAVTT VMGTVCCAUX VMGTREFCLK VMGTAVTTRCAL VIN IDCIN IDCOUT Analog supply voltage for the GTX transmitter and receiver circuits Analog supply voltage for the GTX transmitter and receiver termination circuits Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers GTX transceiver reference clock absolute input voltage Analog supply voltage for the resistor calibration circuit of the GTX transceiver column Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage DC input current for receiver input pins DC coupled VMGTAVTT = 1.2V DC output current for transmitter pins DC coupled VMGTAVTT = 1.2V XADC supply relative to GNDADC XADC reference input relative to GNDADC 0.5 0.5 0.5 0.5 0.5 0.5 1.1 1.32 1.935 1.32 1.32 1.26 14 14 V V V V V V mA mA
Description
Min
Max
Units
XADC
VCCADC VREFP 0.5 0.5 2.0 2.0 V V
Temperature
TSTG TSOL Tj Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. Applies to both MIO supply banks VCCO_MIO0 and VCCO_MIO1. The lower absolute voltage specification always applies. For I/O operation, refer to UG471: 7 Series FPGAs SelectIO Resources User Guide or UG585, Zynq-7000 All Programmable SoC Technical Reference Manual. The maximum limit applied to DC and AC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5. For soldering guidelines and thermal considerations, see UG865, Zynq-7000 All Programmable SoC Packaging and Pinout Specification.
Storage temperature (ambient) Maximum soldering temperature for Pb/Sn component bodies (7) Maximum soldering temperature for Pb-free component bodies Maximum junction temperature(7)
(7)
65
150 +220 +260 +125
C C C C
2. 3. 4. 5. 6. 7.
Table 2: Recommended Operating Conditions (1)

Symbol
PS VCCPINT(2) VCCPAUX VCCPLL VCCO_DDR VCCO_MIO(3) VPIN
(4)
Description
Min
Typ
Max
Units
PS internal supply voltage PS auxiliary supply voltage PS PLL supply voltage PS DDR supply voltage PS supply voltage for MIO banks PS DDR and MIO I/O input voltage PS DDR and MIO I/O input voltage for VREF and differential I/O standards
0.95 1.71 1.71 1.14 1.71 0.20 0.20
1.00 1.80 1.80
1.05 1.89 1.89 1.89
V V V V V V V
3.465 VCCO + 0.20 2.625
PL
VCCINT VCCAUX VCCBRAM Internal supply voltage Auxiliary supply voltage Block RAM supply voltage 0.97 1.71 0.97 1.00 1.80 1.00 1.03 1.89 1.03 V V V
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 2: Recommended Operating Conditions (1) (Contd)
Symbol
VCCO(5)(6) VCCAUX_IO VIN(4) IIN(7) VCCBATT(8)
Description
Supply voltage for 3.3V HR I/O banks Supply voltage for 1.8V HP I/O banks Auxiliary supply voltage when set to 1.8V Auxiliary supply voltage when set to 2.0V I/O input voltage I/O input voltage for VREF and differential I/O standards Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. Battery voltage
Min
1.14 1.14 1.71 1.94 0.20 0.20 1.0
Typ
1.80 2.00
Max
3.465 1.89 1.89 2.06 VCCO + 0.2 2.625 10 1.89
Units
V V V V V
mA V
GTX Transceiver
Analog supply voltage for the GTX transceiver QPLL frequency range 10.3125 GHz(10)(11) Analog supply voltage for the GTX transceiver QPLL frequency range > 10.3125 GHz Analog supply voltage for the GTX transmitter and receiver termination circuits Auxiliary analog QPLL voltage supply for the transceivers Analog supply voltage for the resistor calibration circuit of the GTX transceiver column 0.97 1.02 1.17 1.75 1.17 1.0 1.05 1.2 1.80 1.2 1.08 1.08 1.23 1.85 1.23 V V V V
VMGTAVCC(9)
VMGTAVTT(9) VMGTVCCAUX(9) VMGTAVTTRCAL(9)
XADC
VCCADC VREFP XADC supply relative to GNDADC Externally supplied reference voltage 1.71 1.20 1.80 1.25 1.89 1.30 V V
Temperature
Junction temperature operating range for commercial (C) temperature devices Tj Junction temperature operating range for extended (E) temperature devices Junction temperature operating range for industrial (I) temperature devices Notes:
All voltages are relative to ground. The PL and PS share a common ground. When the processor cores operate FCPU_6X4X_621_MAX at 1 GHz (-3E speed grade), the VCCPINT minimum is 0.97V and the VCCPINT maximum is 1.03V. 3. Applies to both MIO supply banks VCCO_MIO0 and VCCO_MIO1. 4. The lower absolute voltage specification always applies. 5. Configuration data is retained even if VCCO drops to 0V. 6. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. 7. A total of 200 mA per PS or PL bank should not be exceeded. 8. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX. 9. Each voltage listed requires the filter circuit described in UG476: 7 Series FPGAs GTX/GTH Transceivers User Guide. 10. For data rates 10.3125 Gb/s, VMGTAVCC should be 1.0V 3% for lower power consumption. 11. For lower power consumption, VMGTAVCC should be 1.0V 3% over the entire CPLL frequency range. 1. 2.
0 0 40
85 100 100
C C C
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Table 3: DC Characteristics Over Recommended Operating Conditions

Symbol
VDRINT VDRI IREF IL CIN(2)
Description
Data retention VCCINT voltage (below which configuration data might be lost) Data retention VCCAUX voltage (below which configuration data might be lost) VREF leakage current per pin Input or output leakage current per pin (sample-tested) Die input capacitance at the pad Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V
Min
0.75 1.5 90 68 34 23 12 68 45 28
Typ(1)
40
Max
15 15 8 330 250 220 150 120 330 180 25 150 55
Units
V V A A pF A A A A A A A mA nA
IRPU
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V Pad pull-down (when selected) @ VIN = 3.3V Pad pull-down (when selected) @ VIN = 1.8V Analog supply current, analog circuits in powered up state Battery supply current Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_40) for commercial (C), industrial (I), and extended (E) temperature devices
IRPD(3) ICCADC IBATT

(4)
RIN_TERM(5)
Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_50) for commercial (C), industrial (I), and extended (E) temperature devices Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_60) for commercial (C), industrial (I), and extended (E) temperature devices
35
50
65
44
60
83
n r Notes:
1. 2. 3. 4. 5.
Temperature diode ideality factor Temperature diode series resistance
1.010 2
Typical values are specified at nominal voltage, 25C. This measurement represents the die capacitance at the pad, not including the package. The PS MIO pins do not have pull-down resistors. Maximum value specified for worst case process at 25C. Termination resistance to a VCCO/2 level.
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Table 4: Maximum Allowed AC Voltage Overshoot and Undershoot for PS I/O and 3.3V HR I/O Banks(1)
AC Voltage Overshoot
VCCO + 0.40 VCCO + 0.45 VCCO + 0.50 VCCO + 0.55 VCCO + 0.60 VCCO + 0.65 VCCO + 0.70 VCCO + 0.75 VCCO + 0.80 VCCO + 0.85 VCCO + 0.90 VCCO + 0.95 Notes:
1. A total of 200 mA per bank should not be exceeded.
% of UI @40C to 100C
100 100 100 100 46.6 21.2 9.75 4.55 2.15 1.02 0.49 0.24
AC Voltage Undershoot
0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95
100 61.7 25.8 11.0 4.77 2.10 0.94 0.43 0.20 0.09 0.04 0.02
Table 5: Maximum Allowed AC Voltage Overshoot and Undershoot for PL 1.8V HP I/O Banks(1)(2)
AC Voltage Overshoot
VCCO + 0.40 VCCO + 0.45 VCCO + 0.50 VCCO + 0.55 VCCO + 0.60 VCCO + 0.65 VCCO + 0.70 VCCO + 0.75 VCCO + 0.80 VCCO + 0.85 VCCO + 0.90 VCCO + 0.95 Notes:
1. 2. A total of 200 mA per bank should not be exceeded. For UI smaller than 20 s.
100 100 100 100 50.0 50.0 47.0 21.2 9.71 4.51 2.12 1.01
AC Voltage Undershoot
0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95
100 100 100 100 50.0 50.0 50.0 50.0 50.0 28.4 12.7 5.79
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Table 6: Typical Quiescent Supply Current

Symbol Description Device
XC7Z030 XC7Z045 XC7Z030 XC7Z045 XC7Z030 XC7Z045 XC7Z030 XC7Z045 ICCAUXQ PL quiescent VCCAUX supply current XC7Z030 XC7Z045 ICCAUX_IOQ PL quiescent VCCAUX_IO supply current ICCOQ ICCBRAMQ PL quiescent VCCO supply current PL quiescent VCCBRAM supply current XC7Z030 XC7Z045 XC7Z030 XC7Z045 XC7Z030 XC7Z045 Notes:
1. 2. 3. Typical values are specified at nominal voltage, 85C junction temperatures (Tj) with single-ended SelectIO resources. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for conditions other than those specified.
Speed Grade -3
152 152 13 13 2 2 352 873 31 73
-2
152 152 13 13 2 2 352 873 31 73
-1
152 152 13 13 2 2 352 873 31 73
Units
mA mA mA mA mA mA mA mA mA mA mA mA
ICCPINTQ ICCPAUXQ ICCDDRQ ICCINTQ
PS quiescent VCCPINT supply current PS quiescent VCCPAUX supply current PS quiescent VCCO_DDR supply current PL quiescent VCCINT supply current
1 1 11 23
1 1 11 23
1 1 11 23
mA mA mA mA
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PS Power-On/Off Power Supply Requirements

The recommended power-on sequence is VCCPINT, VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCPAUX, VCCPLL and the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) have the same recommended voltage levels, then they can be powered by the same supply and ramped simultaneously. Xilinx recommends powering VCCPLL with the same supply as VCCPAUX, with an optional ferrite bead filter. For VCCO_MIO0 and VCCO_MIO1 voltages of 3.3V: The voltage difference between VCCO_MIO0 /VCCO_MIO1 and VCCPAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels. The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
PS Power-on Reset
The PS provides the power on reset bar (PS_POR_B) input signal which must be held Low until all PS power supplies are stable and within operating limits. Additionally, PS_POR_B must be held Low until PS_CLK is stable for 2,000 clocks.
PL Power-On/Off Power Supply Sequencing

The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the poweron sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels then they can be powered by the same supply and ramped simultaneously. For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0: The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels. The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
The recommended power-on sequence to achieve minimum current draw for the GTX transceivers is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down. When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT VMGTAVCC > 150 mV and VMGTAVCC < 0.7V, the VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down. When VMGTAVTT is powered before VCCINT and VMGTAVTT VCCINT > 150 mV and VCCINT < 0.7V, the VMGTAVTT current draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to 0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.
PSPL Power Sequencing

The PS and PL power supplies are fully independent. There are no sequencing requirements between the PS (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) and PL (VCCINT, VCCBRAM, VCCAUX, VCCO, VCCAUX_IO, VMGTAVCC, VMGTAVTT, VMGTVCCAUX, and VCCADC) power supplies.
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Power Supply and PS Reset Requirements

Table 7 shows the minimum current, in addition to ICCQ, that is required by Zynq-7000 devices for proper power-on and configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies have passed through their power-on reset threshold voltages. The Zynq-7000 device must not be configured until after VCCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on these supplies. Table 7: Power-On Current for Zynq-7000 Devices(1)
Device
XC7Z030
ICCPINTMIN Typ(2)
ICCPAUXMIN Typ(2)
ICCDDRMIN Typ(2)
ICCINTMIN Typ(2)
ICCAUXMIN Typ(2)
ICCOMIN Typ(2)
ICCOQ + 40 mA per bank ICCOQ + 40 mA per bank
ICCAUX_IOMIN Typ(2)
ICCOAUXIOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank
ICCBRAMMIN Typ(2)
Units
mA
XC7Z045
mA
Notes:
1. 2. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents. Typical values are specified at nominal voltage, 25C.
Table 8: Power Supply Ramp Time

Symbol
TVCCPINT TVCCPAUX TVCCO_DDR TVVCO_MIO TVCCINT TVCCO TVCCAUX TVCCAUX_IO TVCCBRAM TVCCO2VCCAUX TMGTAVCC TMGTAVTT TMGTVCCAUX Notes:
1. Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V.
Description
PS internal supply voltage relative to GND PS auxiliary supply voltage relative to GND PS DDR supply voltage relative to GND PS MIO banks supply voltage relative to GND PL ramp time from GND to 90% of VCCINT PL ramp time from GND to 90% of VCCO PL ramp time from GND to 90% of VCCAUX Ramp time from GND to 90% of VCCAUX_IO PL ramp time from GND to 90% of VCCBRAM Allowed time per power cycle for VCCO VCCAUX > 2.625V and VCCO_MIO VCCPAUX > 2.625V Ramp time from GND to 90% of VMGTAVCC Ramp time from GND to 90% of VMGTAVTT Ramp time from GND to 90% of VMGTVCCAUX
Conditions
Min
0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2
Max
50 50 50 50 50 50 50 50 50 500 800 50 50 50
Units
ms ms ms ms ms ms ms ms ms ms ms ms ms
TJ =
100C(1) 85C(1)
0.2 0.2 0.2
TJ =
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DC Input and Output Levels

Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 9: PS Input and Output Levels(1)
Bank I/O Standard
MIO MIO MIO MIO MIO
VIL V, Min V, Max

35% VCCO 0.700 0.800
VIH V, Min
65% VCCO 1.700 2.000
VOL V, Max V, Max

0.450 0.400 0.400 0.400 0.400
VOH V, Min
VCCO_MIO 0.450 VCCO_MIO 0.400 VCCO_MIO 0.400 VCCO_MIO 0.400 2.400
IOL
8 8 8 8 8 8
IOH
8 8 8 8 8 8
mA mA
LVCMOS18(2) 0.300 LVCMOS25(3) 0.300 LVCMOS33(3) 0.300 HSTL_I_18 LVTTL
VCCO_MIO + 0.300 VCCO_MIO + 0.300 3.450
0.300 VPREF 0.100 VPREF + 0.100 VCCO_MIO + 0.300 0.300 0.800 2.000 3.450
DDR SSTL18_I DDR SSTL15 DDR HSUL_12 Notes:

1. 2. 3.
0.300 VPREF 0.125 VPREF + 0.125 VCCO_DDR + 0.300 VCCO_DDR/2 0.470 VCCO_DDR/2 + 0.470 0.300 VPREF 0.130 VPREF + 0.130 VCCO_DDR + 0.300 20% VCCO_DDR 80% VCCO_DDR
0.300 VPREF 0.100 VPREF + 0.100 VCCO_DDR + 0.300 VCCO_DDR/2 0.175 VCCO_DDR/2 + 0.175 13.0 13.0 0.1 0.1
Tested according to relevant specifications. With bank VMODE pin connected to VCCO for the bank. With bank VMODE pin connected to GND for the bank.
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Table 10: SelectIO DC Input and Output Levels(1)(2)

I/O Standard
HSTL_I HSTL_I_12 HSTL_I_18 HSTL_II HSTL_II_18 HSUL_12 LVCMOS12 LVCMOS15, LVDCI_15 LVCMOS18, LVDCI_18 LVCMOS25 LVCMOS33 LVTTL MOBILE_DDR PCI33_3 SSTL12 SSTL135 SSTL135_R SSTL15 SSTL15_R SSTL18_I SSTL18_II Notes:
1. 2. 3. 4. 5. 6. 7. 8. Tested according to relevant specifications. 3.3V and 2.5V standards are only supported in 3.3V I/O banks. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks. Supported drive strengths of 4, 8, 12, or 16 mA Supported drive strengths of 4, 8, 12, 16, or 24 mA For detailed interface specific DC voltage levels, see UG471: 7 Series FPGAs SelectIO Resources User Guide.
VIL V, Min
0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.500 0.300 0.300 0.300 0.300 0.300 0.300 0.300
VIH V, Max V, Min

VREF + 0.100 VREF + 0.080 VREF + 0.100 VREF + 0.100 VREF + 0.100 VREF + 0.130 65% VCCO 65% VCCO 65% VCCO 1.700 2.000 2.000 80% VCCO 50% VCCO VREF + 0.100 VREF + 0.090 VREF + 0.090 VREF + 0.100 VREF + 0.100 VREF + 0.125 VREF + 0.125
VOL V, Max
VCCO + 0.300 VCCO + 0.300 VCCO + 0.300 VCCO + 0.300 VCCO + 0.300 VCCO + 0.300 VCCO + 0.300 VCCO + 0.300 VCCO + 0.300 VCCO + 0.300 3.450 3.450 VCCO + 0.300 VCCO + 0.500
VOH V, Min
VCCO 0.400 75% VCCO VCCO 0.400 VCCO 0.400 VCCO 0.400 80% VCCO VCCO 0.400 75% VCCO VCCO 0.450 VCCO 0.400 VCCO 0.400 2.400 90% VCCO 90% VCCO
IOL mA
8 6.3 8 16 16 0.1 Note 3 Note 4 Note 5 Note 6 Note 6 Note 7 0.1 1.5 14.25 13.0 8.9 13.0 8.9 8 13.4
IOH mA
8 6.3 8 16 16 0.1 Note 3 Note 4 Note 5 Note 6 Note 6 Note 7 0.1 0.5 14.25 13.0 8.9 13.0 8.9 8 13.4
V, Max
0.400 25% VCCO 0.400 0.400 0.400 20% VCCO 0.400 25% VCCO 0.450 0.400 0.400 0.400 10% VCCO 10% VCCO
VREF 0.100 VREF 0.080 VREF 0.100 VREF 0.100 VREF 0.100 VREF 0.130 35% VCCO 35% VCCO 35% VCCO 0.700 0.800 0.800 20% VCCO 30% VCCO VREF 0.100 VREF 0.090 VREF 0.090 VREF 0.100 VREF 0.100 VREF 0.125 VREF 0.125
VCCO + 0.300 VCCO/2 0.150 VCCO/2 + 0.150 VCCO + 0.300 VCCO/2 0.150 VCCO/2 + 0.150 VCCO + 0.300 VCCO/2 0.150 VCCO/2 + 0.150 VCCO + 0.300 VCCO/2 0.175 VCCO/2 + 0.175 VCCO + 0.300 VCCO/2 0.175 VCCO/2 + 0.175 VCCO + 0.300 VCCO/2 0.470 VCCO/2 + 0.470 VCCO + 0.300 VCCO/2 0.600 VCCO/2 + 0.600
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Table 11: Differential SelectIO DC Input and Output Levels

I/O Standard
BLVDS_25
VICM(1) V, Min V, Typ

0.300 1.200 1.200 0.900 0.900 2.965
VID(2) V, Max
1.425 VCCAUX VCCAUX 1.500 3.230
VOCM(3) V, Min
1.000 0.500 1.000
VOD(4) V, Max
1.400 1.400 1.400 0.300 0.100 0.100
V, Min V, Typ V, Max

0.100 0.200 0.100 0.100 0.150 0.400 0.250 0.350 0.675 0.600 0.400 0.600
V, Typ
1.250 1.200 0.950 1.200
V, Min V, Typ V, Max

Note 5 0.450 0.250 0.350 0.600 0.600 0.400 0.600 0.800
MINI_LVDS_25 0.300 PPDS_25 RSDS_25 TMDS_33 Notes:

1. 2. 3. 4. 5. 6. 7.
0.200 0.300 2.700
1.200 VCCO0.405 VCCO0.300 VCCO0.190 0.400
VICM is the input common mode voltage. VID is the input differential voltage (Q Q). VOCM is the output common mode voltage. VOD is the output differential voltage (Q Q). VOD for BLVDS will vary significantly depending on topology and loading. LVDS_25 is specified in Table 13. LVDS is specified in Table 14.
Table 12: Complementary Differential SelectIO DC Input and Output Levels

VICM(1) I/O Standard
DIFF_HSTL_I DIFF_HSTL_I_18 DIFF_HSTL_II DIFF_HSTL_II_18 DIFF_HSUL_12 DIFF_MOBILE_DDR DIFF_SSTL12 DIFF_SSTL135 DIFF_SSTL135_R DIFF_SSTL15 DIFF_SSTL15_R DIFF_SSTL18_I DIFF_SSTL18_II Notes:
1. 2. 3. 4. VICM is the input common mode voltage. VID is the input differential voltage (Q Q). VOL is the single-ended low-output voltage. VOH is the single-ended high-output voltage.
VID(2) V, Max
1.125 1.425 1.125 1.425 0.850 1.425 0.850 1.000 1.000 1.125 1.125 1.425 1.425
VOL(3) V, Max
0.400 0.400 0.400 0.400 20% VCCO 10% VCCO
VOH(4) V, Min
VCCO0.400 VCCO0.400 VCCO0.400 VCCO0.400 80% VCCO 90% VCCO
IOL mA, Max

8.00 8.00 16.00 16.00 0.100 0.100 14.25 13.0 8.9 13.0 8.9 8.00 13.4
IOH mA, Min

8.00 8.00 16.00 16.00 0.100 0.100 14.25 13.0 8.9 13.0 8.9 8.00 13.4
V, Min
0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300 0.300
V, Typ
0.750 0.900 0.750 0.900 0.600 0.900 0.600 0.675 0.675 0.750 0.750 0.900 0.900
V, Min
0.100 0.100 0.100 0.100 0.100 0.100 0.100 0.100 0.100 0.100 0.100 0.100 0.100
V, Max

(VCCO/2) 0.150 (VCCO/2) + 0.150 (VCCO/2) 0.150 (VCCO/2) + 0.150 (VCCO/2) 0.150 (VCCO/2) + 0.150 (VCCO/2) 0.175 (VCCO/2) + 0.175 (VCCO/2) 0.175 (VCCO/2) + 0.175 (VCCO/2) 0.470 (VCCO/2) + 0.470 (VCCO/2) 0.600 (VCCO/2) + 0.600
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LVDS DC Specifications (LVDS_25)

The LVDS_25 standard is available in the HR I/O banks. See UG471: 7 Series FPGAs SelectIO Resources User Guide for more information. Table 13: LVDS_25 DC Specifications
Symbol
VCCO VOH VOL VODIFF VOCM VIDIFF VICM
DC Parameter
Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q Q), Q = High (Q Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q Q), Q = High (Q Q), Q = High Input Common-Mode Voltage
Conditions
RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals
Min
2.375 0.700 247 1.000 100 0.300
Typ
2.500 350 1.250 350 1.200
Max
2.625 1.675 600 1.425 600 1.425
Units
V V V mV V mV V
LVDS DC Specifications (LVDS)

The LVDS standard is available in the HP I/O banks. See UG471: 7 Series FPGAs SelectIO Resources User Guide for more information. Table 14: LVDS DC Specifications
Symbol
VCCO VOH VOL VODIFF VOCM VIDIFF VICM
DC Parameter
Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q Q), Q = High (Q Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q Q), Q = High (Q Q), Q = High Input Common-Mode Voltage
Conditions
RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals Common-mode input voltage = 1.25V Differential input voltage = 350 mV
Min
1.710 0.825 247 1.000 100 0.300
Typ
1.800 350 1.250 350 1.200
Max
1.890 1.675 600 1.425 600 1.425
Units
V V V mV V mV V
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AC Switching Characteristics
All values represented in this data sheet are based on the speed specifications in ISE software 14.2 v1.02 for the -3, -2, and -1 speed grades. Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance Product Specification These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some underreporting might still occur. Preliminary Product Specification These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production Product Specification These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades.
Testing of AC Switching Characteristics

Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Zynq-7000 devices.
Speed Grade Designations

Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 15 correlates the current status of each Zynq-7000 device on a per speed grade basis. Table 15: Zynq-7000 Device Speed Grade Designations
Device
XC7Z030 XC7Z045
Speed Grade Designations Advance

-3, -2, -1 -3, -2, -1
Preliminary
Production
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Production Silicon and ISE Software Status

In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 16 lists the production released Zynq-7000 device, speed grade, and the minimum corresponding supported speed specification version and ISE software revisions. The ISE software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. Table 16: Zynq-7000 Device Production Software and Speed Specification Release
Device
XC7Z030 XC7Z045
Notes:
Speed Grade Designations -3 -2 -1
1.
Blank entries indicate a device and/or speed grade in advance or preliminary status.
www.xilinx.com 14
PS Performance Characteristics
For further design requirement details, refer to UG585, Zynq-7000 All Programmable SoC Technical Reference Manual. Table 17: CPU Clock Domains Performance
Symbol
FCPU_6X4X_621_MAX FCPU_3X2X_621_MAX FCPU_2X_621_MAX FCPU_1X_621_MAX FCPU_6X4X_421_MAX FCPU_3X2X_421_MAX FCPU_2X_421_MAX FCPU_1X_421_MAX 4:2:1 6:2:1
Clock Ratio
Description
Maximum CPU clock frequency Maximum CPU_3X clock frequency Maximum CPU_2X clock frequency Maximum CPU_1X clock frequency Maximum CPU clock frequency Maximum CPU_3X clock frequency Maximum CPU_2X clock frequency Maximum CPU_1X clock frequency
Speed Grade -3
1000 500 333 167 710 355 355 178
-2
-1
667 333 222 111 533 267 267 133
Units
MHz MHz MHz MHz MHz MHz MHz MHz
Table 18: PS DDR Clock Domains Performance

Symbol
FDDR3_MAX FDDR2_MAX FLPDDR2_MAX FDDRCLK_2XMAX
Description
Maximum DDR3 interface performance Maximum DDR2 interface performance Maximum LPDDR2 interface performance Maximum DDR_2X clock frequency
Speed Grade -3
1333 800 800 444
-2
1066 800 800 408
-1
1066 800 800 355
Units
Mb/s Mb/s Mb/s MHz
PS Switching Characteristics
Clocks and Resets
Table 19: PS Reference Clock Input Requirements
Symbol
TJT_PS_CLK TDC_PS_CLK FPS_CLK
Description
PS reference clock jitter tolerance PS reference clock duty cycle PS reference clock frequency
Min
Typ
Max
Units
ps
40 30
60 60
% MHz
Table 20: PS PLL Switching Characteristics

Symbol
TLOCK_PSPLL FPSPLL_MAX FPSPLL_MIN PLL maximum lock time PLL maximum output frequency PLL minimum output frequency
Description
Speed Grade -3
60 2000 780 780
-2
60
-1
60 1600 780
Units
s MHz MHz
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Table 21: PS Reset Requirements

Symbol
TPSPOR_MIN TPSRST_MIN Notes:
1. PS_POR_B needs to be asserted low until PS supply voltages reach minimum levels and the PS_CLK input is stable.
Description
Minimum reference clock cycles at power-on before deassertion of PS_POR_B(1). PS_SRST_B reset minimum assertion period.
Speed Grade -3
2000 2000
-2
2000 2000
-1
2000 2000
Units
Reference Clock Cycles Reference Clock Cycles
Table 22: PS Mode Pins Sampling Timing

Symbol
TPSPORMODE_MIN
Description
Minimum reference clock cycles from PS_POR_B pin deassertion to when the mode pins are sampled.
Speed Grade -3
50
-2
50
-1
50
Units
Reference Clock Cycles
Memory Interfaces
Figure 1 through Figure 4 show the timing parameters specified in Table 23.
X-Ref Target - Figure 1
TONFIWP
NAND_WE_B
TONFICLEWE
NAND_CLE
TONFIWECLE
TONFICSWE
NAND_CE_B
TONFIWECS
TONFIALEWE
NAND_ALE
TONFIWEALE
TONFIIOWE
NAND_IO[15:0]
Command
TONFIWEIO
DS191_01_070212
Figure 1: Command Latch Timing Diagram

TONFIWP
NAND_WE_B
TONFIWH
TONFICLEWE
NAND_CLE
TONFICSWE
NAND_CE_B
TONFIALEWE
NAND_ALE
TONFIWEALE
TONFIIOWE
NAND_IO[15:0]
Address
TONFIWEIO
DS191_02_070212
Figure 2: Address Latch Timing Diagram

DS191 (v1.1) August 31, 2012 Advance Product Specification www.xilinx.com 16
TONFIWC TONFIWP NAND_WE_B TONFIWECLE NAND_CLE TONFIWH
TONFIWECS NAND_CE_B TONFIALEWE NAND_ALE TONFIWEIO TONFIIOWE NAND_IO[15:0]

DIN0
TONFIWEIO
TONFIIOWE
DIN1 DINn
DS191_03_070212
Figure 3: Data Input Cycle Timing Diagram

TONFIRC TONFIRP NAND_RE_B TONFIREH
NAND_CE_B TONFIRR NAND_BUSY TONFIRHZ TONFIREA TONFICEA NAND_IO[15:0]

DOUT0 DOUT1
TONFIRHCH
DOUTn
DS191_04_070212
Figure 4: Data Output Cycle Timing Diagram
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Table 23: ONFI Interface Switching Characteristics(1)(2)(3)

Symbol
TONFICLEWE TONFIWECLE TONFICSWE TONFIWECS TONFIWP TONFIWH TONFIALEWE TONFIWEALE TONFIRC TONFIRR TONFICEA TONFIREA TONFIRHZ TONFIRHCH TONFIWC TONFIRP TONFIREH TONFIIOWE TONFIWEIO Notes:
1. 2. 3. Refer to UG585: Zynq-7000 All Programmable SoC Technical Reference Manual for static memory controller programming information. The static memory controller is compatible with the Open NAND Flash Interface Specification rev 1.0. The static memory controller supports ONFI timing mode 5.
Description
NAND_CLE setup time NAND_CLE hold time NAND_CE_B setup time NAND_CE_B hold time NAND_WE_B pulse width NAND_WE_B high hold time NAND_ALE setup time NAND_ALE hold time Read cycle duration Ready to NAND_RE_B Low NAND_CE_B access time NAND_RE_B access time NAND_RE_B High to Hi-Z NAND_RE_B High to output hold Write cycle duration NAND_RE_B pulse duration NAND_RE_B high hold time NAND_IO setup time NAND_IO hold time
Min
10.0 5.0 15.0 5.0 10.0 7.0 10.0 5.0 20.0 20.0
Max
Units
ns ns ns ns ns ns ns ns ns ns
25.0 16.0 100 15.0 20.0 10.0 7.0 7.0 5.0
ns ns ns ns ns ns ns ns ns
Table 24: Parallel NOR FLASH/SRAM Interface Asynchronous Mode Switching Characteristics
Symbol
TSRAMRC TSRAMOE TSRAMWC TSRAMWP Notes:
1. Refer to UG585: Zynq-7000 All Programmable SoC Technical Reference Manual for static memory controller programming information.
Description
Read cycle duration SRAM/NOR_OE pulse duration Write cycle duration SRAM/NOR_WE_B pulse duration
Min
8 4 8 6.5
Max
100 25 100 30
Units
ns ns ns ns
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QSPI_SCLK_FB_OUT TQSPIDCK# QSPI{0,1}_IO# (input) TQSPICKO# QSPI{0,1}_IO# (output)

DS191_05_080712
TQSPICKD#
Figure 5: Quad-SPI Interface Timing Diagram Table 25: Quad-SPI Interface Switching Characteristics
Symbol
Feedback Clock Enabled TQSPICKO1 TQSPIDCK1 TQSPICKD1 TDCQSPICLK1 FQSPICLK1 TQSPICKO2 TQSPIDCK2 TQSPICKD2 TDCQSPICLK2 FQSPICLK2 FQSPI_REF_CLK Notes:
1. 2. Single and dual stacked Quad-SPI memory configurations only. Requires appropriate component selection/board design
Description
Min
Max
Units
Data and slave select output delay Input data setup time Input data hold time Quad-SPI clock duty cycle Quad-SPI device clock frequency 1.5 1.0 40
3.0
ns ns ns
60 100(1)(2)
% MHz
Feedback Clock Disabled Data and slave select output delay Input data setup time Input data hold time Quad-SPI clock duty cycle Quad-SPI device clock frequency 8.9 1.1 40 60 40(1) 3.0 ns ns ns % MHz
Feedback Clock Enabled or Disabled Quad-SPI reference clock frequency 200 MHz
I/O Peripherals
USB{0,1}_ULPI_CLK
TULPIDCK
USB{0,1}_ULPI_DATA[7:0] (Input)
TULPICKD
TULPIDCK
USB{0,1}_ULPI_DIR, USB{0,1}_ULPI_NXT
TULPICKD
TULPICKO
USB{0,1}_ULPI_STP
TULPICKO
USB{0,1}_ULPI_DATA[7:0] (Output)
DS191_06_072412
Figure 6: ULPI Interface Timing Diagram
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Table 26: ULPI Interface Clock Receiving Mode Switching Characteristics

Symbol
TULPIDCK TULPICKD TULPICKO FULPICLK
Description
Input setup to ULPI clock, all inputs Input hold to ULPI clock, all inputs ULPI clock to output valid, all outputs ULPI reference clock frequency
Min
10.67 1.0
Max
Units
ns ns
8.86 59.97 60.03
ns MHz
RGMII_TX_CLK
TGEMTXCKO
RGMII_TX_D[3:0] RGMII_TX_CTL
RGMII_RX_CLK
TGEMRXDCK
RGMII_RX_D[3:0] RGMII_RX_CTL
TGEMRXCKD
TMDIOCLK
MDIO_CLK
TMDIOCKH
TMDIOCKL
TMDIODCK
MDIO_IO (Input)
TMDIOCKD
TMDIOCKO
MDIO_IO (Output)
DS191_07_072412
Figure 7: RGMII Interface Timing Diagram Table 27: RGMII Interface Switching Characteristics(1)(2)(3)
Symbol
TDCGETXCLK TGEMTXCKO TGEMRXDCK TGEMRXCKD TMDIOCLK TMDIOCKH TMDIOCKL TMDIODCK TMDIOCKD TMDIOCKO FGETXCLK FGERXCLK FENET_REF_CLK Notes:
1. 2. 3. The gigabit Ethernet MAC is compatible with the IEEE 802.3 standard. Values in this table are specified during 1000 Mb/s operation. LVCMOS33 is not supported.
Description
Transmit clock duty cycle RGMII_TX_D[3:0], RGMII_TX_CTL clock to out time RGMII_RX_D[3:0], RGMII_RX_CTL setup time RGMII_RX_D[3:0], RGMII_RX_CTL hold time MDC output clock period MDC clock High time MDC clock Low time MDIO input data setup time MDIO input data hold time MDIO data output delay RGMII_TX_CLK transmit clock frequency RGMII_RX_CLK receive clock frequency Ethernet reference clock frequency
Min
Typ
Max
Units
%
0.5 0.41 0.45 400 160 160 100 0 10 125 125 125
ns ns ns ns ns ns ns ns ns MHz MHz MHz
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SD{0,1}_CLK TSDDCK SD{0,1}_DATA[3:0], SD{0,1}_CMD (Input) TSDCKO SD{0,1}_DATA[3:0], SD{0,1}_CMD (Output)

DS191_08_072412
TSDCKD
Figure 8: SD/SDIO Interface Timing Diagram Table 28: SD/SDIO Interface Full/High Speed Mode Switching Characteristics(1)
Symbol
TDCSDCLK TSDCKO TSDDCK TSDCKD FSDCLK FSDIO_REF_CLK Notes:
1. The SD/SDIO peripheral interface is compliant with the standard SD host controller specification version 2.0 Part A2 standard.
Description
SDIO clock duty cycle SD clock to out time, all outputs Input setup time to SD clock, all inputs Input hold time to SD clock, all inputs SDIO device clock frequency SDIO reference clock frequency
Min
Max
Units
%
12 3 1.05 25 50 125
ns ns ns MHz MHz
TI2CFCKL
TI2CFCKH
I2C{0,1}SCL TI2CFDCK I2C{0,1}SDAI TI2CFCKO I2C{0,1}SDAO

DS191_09_072412
Figure 9: I2C Fast Mode Interface Timing Diagram Table 29: I2C Fast Mode Interface Switching Characteristics(1)
Symbol
TI2CFCKL TI2CFCKH TI2CFCKO TI2CFDCK FI2CFCLK Notes:
1. The I2C peripheral interface is compliant with the I2C-bus specification 2.
Description
I2C{0,1}SCL Low time I2C{0,1}SCL High time I2C{0,1}SDAO clock to out delay I2C{0,1}SDAI setup time I2C{0,1}SCL clock frequency
Min
1.3 0.6
Max
Units
s s
0.9 100 0 400
s ns KHz
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TI2CSCKL
TI2CSCKH
I2C{0,1}SCL TI2CSDCK I2C{0,1}SDAI TI2CSCKO I2C{0,1}SDAO

DS191_10_072412
Figure 10: I2C Standard Mode Interface Timing Diagram Table 30: I2C Standard Mode Interface Switching Characteristics
Symbol
TI2CSCKL TI2CSCKH TI2CSCKO TI2CSDCK FI2CSCLK Notes:
1. The I2C peripheral interface is compliant with the I2C-bus specification 2.
Description
I2C{0,1}SCL Low time I2C{0,1}SCL High time I2C{0,1}SDAO clock to out delay I2C{0,1}SDAI setup time I2C{0,1}SCL clock frequency
Min
4.7 4.0
Max
Units
s s
3.45 250 0 100
s ns KHz
SPI{0,1}_CLK
TMSPIDCK
SPI{0,1}_MI
TMSPICKD
TMSPICKO
SPI{0,1}_MO SPI{0,1}_SS
DS191_11_072412
Figure 11: SPI Master Mode Interface Timing Diagram Table 31: SPI Master Mode Interface Switching Characteristics(1)
Symbol
TDCMSPICLK TMSPIDCK TMSPICKD TMSPICKO FMSPICLK FSPI_REF_CLK Notes:
1. These parameters apply to all SPI controllers in the PS.
Description
SPI master mode clock duty cycle Input setup time for SPI{0,1}_MI Input hold time for SPI{0,1}_MI Output delay for SPI{0,1}_MO and SPI{0,1}_SS SPI master mode device clock frequency SPI reference clock frequency
Min
Max
Units
% ns ns ns
44 200
MHz MHz
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SPI{0,1}_CLK
TSSPIDCK
SPI{0,1}_SI SPI{0,1}_SS
TSSPICKD
TSSPICKO
SPI{0,1}_SO
DS191_12_072412
Figure 12: SPI Slave Mode Interface Timing Diagram Table 32: SPI Slave Mode Interface Switching Characteristics(1)
Symbol
TDCSSPICLK TSSPIDCK TSSPICKD TSSPICKO FSSPICLK FSPI_REF_CLK Notes:
1. These parameters apply to all SPI controllers in the PS.
Description
SPI slave mode clock duty cycle Input setup time for MOSI and SS Input hold time for MOSI and SS Output delay for MISO SPI slave mode device clock frequency SPI reference clock frequency
Min
Max
Units
% ns ns
15.2 25 200
ns MHz MHz
Table 33: CAN Interface Switching Characteristics

Symbol
TPWCANRX TPWCANTX FCAN_REF_CLK Minimum receive pulse width Minimum transmit pulse width CAN reference clock frequency
Description
Min
1 1
Max
100
Units
s s MHz
Table 34: UART Interface Switching Characteristics

Symbol
BAUDTXMAX BAUDRXMAX FUART_REF_CLK Maximum transmit baud rate Maximum receive baud rate UART reference clock frequency
Description
Min

Max
1 1 100
Units
Mb/s Mb/s MHz
Table 35: GPIO Banks Switching Characteristics

Symbol
TPWGPIOHL SRGPIO Notes:
1. Pulse width requirement for interrupt.
Description
Input low/high pulse width(1) Output slew rate
Min
1
Max
Units
s V/s
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Debug and Timer Interfaces

Table 36: Trace Interface Switching Characteristics
Symbol
TTCECKQ TTCECTLCKQ TDCTCECLK FTCECLK Trace databus output delay Trace port control output delay Trace clock duty cycle Trace clock frequency 40 60 109
Description
Min
Max
Units
ns ns % MHz
Table 37: Triple Time Counter Interface Switching Characteristics

Symbol
TDCTTCOCLK TDCTTCICLK FTTCOCLK FTTCICLK
Description
Triple time counter output clock duty cycle Triple time counter input clock duty cycle Triple time counter output clock frequency Triple time counter input clock frequency
Min
40 40
Max
60 60
Units
% % MHz MHz
Table 38: Watchdog Timer Interface Switching Characteristics

Symbol
FWDTCLK
Description
Watchdog timer input clock frequency
Min
Max
Units
MHz
PS-PL Interface
Table 39: EMIO Ethernet Switching Characteristics
Symbol
TEMIOENETDCK TEMIOENETCKD TEMIOENETCKO FEMIOGEMCLK Notes:
1. 2. Reference to EMIOENET#GMIIRXCLK. Reference to EMIOENET#GMIITXCLK.
Description
EMIO Ethernet signals setup time, all inputs(1) EMIO Ethernet signals hold time, all inputs(1) outputs(2)
Speed Grade -3
0.96 0.00 2.11 125
-2
1.11 0.00 2.58 125
-1
1.34 0.00 3.29 125
Units
ns ns ns MHz
EMIO Ethernet signals clock to out time, all EMIO Ethernet maximum MAC frequency
Table 40: EMIO SPI Switching Characteristics

Symbol
TEMIOSPIDCK TEMIOSPIACKD TEMIOSPICKQ FEMIOSPICLK Notes:
1. Reference to EMIOSPI#SCLK.
Description
EMIO SPI signals setup time, all inputs(1) EMIO SPI signals hold time, all inputs(1) EMIO SPI signals clock to out time, all outputs(1) EMIO SPI maximum frequency
Speed Grade -3 -2 -1
Units
ns ns ns
25
25
25
MHz
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Table 41: EMIO SD Switching Characteristics

Symbol
TEMIOSDDCK TEMIOSDACKD TEMIOSDCKQ FEMIOSDCLK Notes:
1. Reference to EMIOSDIO#CLKFB.
Description
EMIO SD signals setup time, all inputs(1) EMIO SD signals hold time, all inputs(1) outputs(1)
Speed Grade -3
0.40 0.12
-2
0.46 0.29
-1
0.55 0.54
Units
ns ns ns
EMIO SD signals clock to out time, all EMIO SD maximum frequency
25
25
25
MHz
Table 42: EMIO JTAG Switching Characteristics

Symbol
TEMIOJTAGDCK TEMIOJTAGCKD TEMIOJTAGCKO FEMIOJTAGCLK Notes:
1. Reference to EMIOPJTAGTCK.
Description
EMIO JTAG signals setup time, all inputs(1) EMIO JTAG signals hold time, all inputs(1) outputs(1)
Speed Grade -3
2.02 0.00 5.01 50
-2
2.36 0.00 5.85 50
-1
2.87 0.00 7.12 50
Units
ns ns ns MHz
EMIO JTAG signals clock to out time, all EMIO JTAG maximum frequency
Table 43: EMIO Trace Packet Output Switching Characteristics

Symbol
TEMIOTRACECKO FEMIOTRACECLK Notes:
1. Reference to EMIOTRACECLK.
Description
EMIO trace clock to out time, all outputs(1) EMIO trace maximum frequency
Speed Grade -3
1.16 125
-2
1.43 125
-1
1.84 125
Units
ns MHz
Table 44: Fabric Trace Monitor Switching Characteristics

Symbol
TFTMDCK TFTMCKD FFTMCLK Notes:
1. Reference to FTMDTRACEINCLOCK.
Description
Fabric trace monitor setup time(1) Fabric trace monitor hold time(1)
Speed Grade -3
0.58 0.00 125
-2
0.72 0.00 125
-1
0.92 0.02 125
Units
ns ns MHz
Fabric trace monitor maximum frequency
Table 45: DMA Peripheral Request Interface Switching Characteristics

Symbol
TEMIODMADCK TEMIODMACKD TEMIODMACKO
Description
DMA peripheral request interface signals setup time, all inputs(1) DMA peripheral request interface signals hold time, all inputs(1) DMA peripheral request interface signals clock to out time, all outputs(1)
Speed Grade -3
0.42 0.00 1.40
-2
0.55 0.02 1.74
-1
0.74 0.14 2.27
Units
ns ns ns
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 45: DMA Peripheral Request Interface Switching Characteristics (Contd)
Symbol
FEMIODMACLK Notes:
1. Reference to DMA#ACLK.
Description
DMA maximum frequency
Speed Grade -3
100
-2
100
-1
100
Units
MHz
AXI Interconnects
The typical clock frequencies for the AXI interconnects in Table 46 through Table 49 are based on a default system. The PL resources utilized in a system are: 70% LUT/flip-flop 70% block RAM 80% I/Os.
Table 46: Master AXI General Purpose Interfaces Switching Characteristics

Symbol
TMAXIGPDCK TMAXIGPCKD TMAXIGPCKO FMAXIGPCLK Notes:
1. Reference to M_AXI_GP#_ACLK.
Description
Master AXI general purpose port signals setup time(1) Master AXI general purpose port signals hold time(1) time(1)
Speed Grade -3
0.50 0.00 1.11
-2
0.64 0.10 1.37
-1
0.84 0.26 1.76 150
Units
ns ns ns MHz
Master AXI general purpose port signals clock to out Master AXI general purpose port typical frequency
Table 47: Slave AXI General Purpose Interfaces Switching Characteristics

Symbol
TSAXIGPDCK TSAXIGPCKD TSAXIGPCKO FSAXIGPCLK Notes:
1. Reference to S_AXI_GP#_ACLK.
Description
Slave AXI general purpose port signals setup time(1) Slave AXI general purpose port signals hold time(1) time(1)
Speed Grade -3
0.65 0.00 1.32
-2
0.83 0.01 1.61
-1
1.09 0.19 2.04 150
Units
ns ns ns MHz
Slave AXI general purpose port signals clock to out Slave AXI general purpose port typical frequency
Table 48: Accelerator Coherency Port Slave AXI Interfaces Switching Characteristics
Symbol
TSAXIACPDCK TSAXIACPCKD TSAXIACPCKO FSAXIACPCLK Notes:
1. Reference to S_AXI_ACP_ACLK.
Description
Slave ACP port signals setup time(1) Slave ACP port signals hold time(1) Slave ACP port signals clock to out time(1) Slave ACP port typical frequency
Speed Grade -3
0.57 0.00 1.10
-2
0.68 0.07 1.37
-1
0.85 0.27 1.79
Units
ns ns ns MHz
www.xilinx.com 26
Table 49: High-Performance Slave AXI Interfaces Switching Characteristics

Symbol
TSAXIHPDCK TSAXIHPCKD TSAXIHPCKO FSAXIHPCLK Notes:
1. Reference to S_AXI_HP#_ACLK.
Description
Slave AXI high-performance port signals setup time(1) Slave AXI high-performance port signals hold time(1) time(1)
Speed Grade -3
0.61 0.00 1.07
-2
0.79 0.10 1.34
-1
1.05 0.31 1.73 150
Units
ns ns ns MHz
Slave AXI high-performance port signals clock to out Slave AXI high-performance port typical frequency
PL Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in the PL. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the AC Switching Characteristics, page 13. In each table, the I/O bank type is either High Performance (HP) or High Range (HR). Table 50: PL Networking Applications Interface Performances
Description
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)
I/O Bank Type

HR HP
Speed Grade -3
710 710 1250 1600 710 710 1250 1600
-2
710 710 1250 1400 710 710 1250 1400
-1
625 625 950 1250 625 625 950 1250
Units
Mb/s Mb/s Mb/s Mb/s Mb/s Mb/s Mb/s Mb/s
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) SDR LVDS receiver (SFI-4.1)(1) DDR LVDS receiver (SPI-4.2)(1)
HR HP HR HP HR HP
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance.
www.xilinx.com 27
Table 51: Maximum Physical Interface (PHY) Rate for Memory Interfaces (FFG Packages)(1)(2)
Memory Standard I/O Bank Type VCCAUX_IO Speed Grade -3 -2 -1 Units
4:1 Memory Controllers

HP DDR3 HP HR HP DDR3L HP HR HP DDR2 HP HR HP RLDRAM III(3) HP HR 2.0V 1.8V N/A 2.0V 1.8V N/A 2.0V 1.8V N/A 2.0V 1.8V N/A 1866 1600 1066 1600 1333 800 800 800 800 800 550 1866 1333 1066 1600 1066 800 800 800 800 667 500 N/A 1600 1066 800 1333 800 667 800 800 800 667 450 Mb/s Mb/s Mb/s Mb/s Mb/s Mb/s Mb/s Mb/s Mb/s MHz MHz

HP DDR3 HP HR HP DDR3L HP HR HP DDR2 HP HR HP QDR II+(4) HP HR HP RLDRAM II HP HR HP LPDDR2(3) HP HR Notes:
1. 2. 3. 4. VREF tracking is required. For more information, see UG586, 7 Series FPGAs Memory Interface Solutions User Guide. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz). RLDRAM III (BL = 4, BL = 8) and LPDDR2 specifications have not been validated with memory IP. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations are limited to 333 MHz for all speed grades and I/O bank types.
2.0V 1.8V N/A 2.0V 1.8V N/A 2.0V 1.8V N/A 2.0V 1.8V N/A 2.0V 1.8V N/A 2.0V 1.8V N/A
1066 1066 1066 1066 1066 800
1066 1066 1066 1066 1066 800
800 800 800 800 800 667
Mb/s Mb/s Mb/s Mb/s Mb/s Mb/s
800
800
800
Mb/s
550 500
500 450
450 400
MHz MHz
533
500
450
MHz
800 800 800
800 800 667
800 800 667
Mb/s Mb/s Mb/s
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Table 52: Maximum Physical Interface (PHY) Rate for Memory Interfaces (FBG Packages)(1)(2)
Memory Standard I/O Bank Type VCCAUX_IO(3) Speed Grade -3 -2 -1 Units

DDR3 HP HR HP HR HP HR HP HR N/A N/A N/A N/A N/A N/A N/A N/A 1333 1066 1066 800 800 800 550 1066 800 800 800 800 667 500 N/A 800 800 667 667 800 667 450 Mb/s Mb/s Mb/s Mb/s Mb/s Mb/s MHz
DDR3L
DDR2 RLDRAM III(4)

DDR3 HP HR HP HR HP HR HP HR HP HR HP HR N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 1066 1066 1066 800 800 800 550 450 533 667 667 1066 800 800 800 800 667 500 400 500 667 667 800 800 667 667 800 667 450 350 450 667 533 Mb/s Mb/s Mb/s Mb/s Mb/s Mb/s MHz MHz MHz Mb/s Mb/s
DDR3L
DDR2 QDR II+(5)
RLDRAM II LPDDR2(4) Notes:

1. 2. 3. 4. 5.
VREF tracking is required. For more information, see UG586, 7 Series FPGAs Memory Interface Solutions User Guide. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz). FBG packages do not have separate VCCAUX_IO supply pins to adjust the pre-driver voltage of the HP I/O banks. RLDRAM III (BL = 4, BL = 8) and LPDDR2 specifications have not been validated with memory IP. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations are limited to 333 MHz for all speed grades and I/O bank types.
www.xilinx.com 29
PL Switching Characteristics
IOB Pad Input/Output/3-State
Table 53 (3.3V high-range IOB (HR)) and Table 54 (1.8V high-performance IOB (HP)) summarizes the values of standardspecific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI termination turn-on time is always faster than TIOTP when the DCITERMDISABLE pin is used. In HR I/O banks, the IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used.
TIOPI I/O Standard -3
LVTTL_S4 LVTTL_S8 LVTTL_S12 LVTTL_S16 LVTTL_S24 LVTTL_F4 LVTTL_F8 LVTTL_F12 LVTTL_F16 LVTTL_F24 LVDS_25(1) MINI_LVDS_25 BLVDS_25(1) RSDS_25 (point to PPDS_25(1) TMDS_33(1) PCI33_3(1) HSUL_12 DIFF_HSUL_12 HSTL_I_S HSTL_II_S HSTL_I_18_S HSTL_II_18_S DIFF_HSTL_I_S DIFF_HSTL_II_S DIFF_HSTL_I_18_S point)(1) 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 0.64 0.68 0.65 0.63 0.65 0.72 1.28 0.63 0.58 0.61 0.61 0.64 0.64 0.63 0.63 0.65
Table 53: 3.3V IOB High Range (HR) Switching Characteristics

TIOOP Speed Grade -1
1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 0.80 0.79 0.80 0.79 0.80 0.86 1.65 0.71 0.70 0.73 0.73 0.76 0.76 0.77 0.77 0.78
TIOTP Speed Grade -1

6.05 5.30 5.29 4.40 4.51 5.29 4.56 4.56 3.15 2.89 1.55 1.55 2.20 1.55 1.58 1.60 3.52 2.59 2.26 1.80 1.43 1.45 1.40 1.61 1.27 1.43
Speed Grade -2
1.42 1.42 1.42 1.42 1.42 1.42 1.42 1.42 1.42 1.42 0.68 0.70 0.69 0.68 0.69 0.76 1.41 0.64 0.61 0.64 0.64 0.67 0.67 0.67 0.67 0.69
Units -1
7.04 6.29 6.28 5.39 5.50 6.28 5.55 5.55 4.14 3.88 2.54 2.54 3.19 2.54 2.57 2.59 4.51 3.58 3.25 2.79 2.42 2.44 2.39 2.60 2.26 2.42 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-3
5.27 4.45 4.45 3.47 3.58 4.70 3.66 3.66 2.57 2.41 1.36 1.36 1.83 1.36 1.36 1.43 2.71 2.06 1.83 1.55 1.21 1.28 1.18 1.42 1.15 1.27
-2
5.63 4.83 4.83 3.88 3.99 4.98 4.06 4.06 2.85 2.64 1.47 1.47 2.02 1.48 1.49 1.54 3.08 2.31 2.04 1.69 1.34 1.39 1.31 1.54 1.24 1.38
-3
6.03 5.21 5.21 4.23 4.34 5.46 4.42 4.42 3.33 3.17 2.12 2.12 2.59 2.12 2.12 2.19 3.47 2.82 2.59 2.31 1.97 2.04 1.94 2.18 1.91 2.03
-2
6.49 5.69 5.69 4.74 4.85 5.84 4.92 4.92 3.71 3.50 2.33 2.33 2.88 2.34 2.35 2.40 3.94 3.17 2.90 2.55 2.20 2.25 2.17 2.40 2.10 2.24
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 53: 3.3V IOB High Range (HR) Switching Characteristics (Contd)
DIFF_HSTL_II_18_S HSTL_I_F HSTL_II_F HSTL_I_18_F HSTL_II_18_F DIFF_HSTL_I_F DIFF_HSTL_II_F DIFF_HSTL_I_18_F DIFF_HSTL_II_18_F LVCMOS33_S4 LVCMOS33_S8 LVCMOS33_S12 LVCMOS33_S16 LVCMOS33_F4 LVCMOS33_F8 LVCMOS33_F12 LVCMOS33_F16 LVCMOS25_S4 LVCMOS25_S8 LVCMOS25_S12 LVCMOS25_S16 LVCMOS25_F4 LVCMOS25_F8 LVCMOS25_F12 LVCMOS25_F16 LVCMOS18_S4 LVCMOS18_S8 LVCMOS18_S12 LVCMOS18_S16 LVCMOS18_S24(1) LVCMOS18_F4 LVCMOS18_F8 LVCMOS18_F12 LVCMOS18_F16 LVCMOS18_F24(1) LVCMOS15_S4 LVCMOS15_S8 LVCMOS15_S12 0.65 0.61 0.61 0.64 0.64 0.63 0.63 0.65 0.65 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.08 1.08 1.08 1.08 1.08 1.08 1.08 1.08 0.64 0.64 0.64 0.64 0.64 0.64 0.64 0.64 0.64 0.64 0.66 0.66 0.66

0.78 0.73 0.73 0.76 0.76 0.77 0.77 0.78 0.78 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.32 1.32 1.32 1.32 1.32 1.32 1.32 1.32 0.74 0.74 0.74 0.74 0.74 0.74 0.74 0.74 0.74 0.74 0.81 0.81 0.81

1.26 1.23 1.28 1.28 1.23 1.22 1.14 1.21 1.13 6.09 5.33 4.42 3.88 5.36 4.56 3.15 2.96 5.16 4.49 3.49 4.09 4.72 3.42 3.13 2.45 3.66 3.31 3.31 2.24 2.08 3.49 2.36 2.36 1.81 1.55 4.03 3.01 2.23
Speed Grade -2
0.69 0.64 0.64 0.67 0.67 0.67 0.67 0.69 0.69 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.16 1.16 1.16 1.16 1.16 1.16 1.16 1.16 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.69 0.69 0.69
Units -1
2.25 2.22 2.27 2.27 2.22 2.21 2.13 2.20 2.12 7.08 6.32 5.41 4.87 6.35 5.55 4.14 3.95 6.15 5.48 4.48 5.08 5.71 4.41 4.12 3.44 4.65 4.30 4.30 3.23 3.07 4.48 3.35 3.35 2.80 2.54 5.02 4.00 3.22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-3
1.14 1.10 1.05 1.05 1.03 1.09 1.02 1.08 1.01 5.23 4.46 3.46 3.06 4.70 3.62 2.57 2.44 4.49 3.66 2.77 3.24 3.96 2.43 2.23 1.92 3.24 2.58 2.58 1.82 1.74 3.12 1.91 1.91 1.52 1.34 3.48 2.37 1.83
-2
1.23 1.19 1.18 1.18 1.14 1.18 1.11 1.17 1.10 5.61 4.85 3.89 3.43 5.01 4.04 2.85 2.69 4.80 4.04 3.10 3.62 4.31 2.87 2.63 2.17 3.45 2.91 2.91 2.03 1.92 3.31 2.13 2.13 1.68 1.46 3.74 2.67 2.03
-3
1.90 1.86 1.81 1.81 1.79 1.85 1.78 1.84 1.77 5.99 5.22 4.22 3.82 5.46 4.38 3.33 3.20 5.25 4.42 3.53 4.00 4.72 3.19 2.99 2.68 4.00 3.34 3.34 2.58 2.50 3.88 2.67 2.67 2.28 2.10 4.24 3.13 2.59
-2
2.09 2.05 2.04 2.04 2.00 2.04 1.97 2.03 1.96 6.47 5.71 4.75 4.29 5.87 4.90 3.71 3.55 5.66 4.90 3.96 4.48 5.17 3.73 3.49 3.03 4.31 3.77 3.77 2.89 2.78 4.17 2.99 2.99 2.54 2.32 4.60 3.53 2.89
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 53: 3.3V IOB High Range (HR) Switching Characteristics (Contd)
LVCMOS15_S16 LVCMOS15_F4 LVCMOS15_F8 LVCMOS15_F12 LVCMOS15_F16 LVCMOS12_S4 LVCMOS12_S8 LVCMOS12_S12(1) LVCMOS12_F4 LVCMOS12_F8 LVCMOS12_F12(1) SSTL135_S SSTL15_S SSTL18_I_S SSTL18_II_S DIFF_SSTL135_S DIFF_SSTL15_S DIFF_SSTL18_I_S DIFF_SSTL18_II_S SSTL135_F SSTL15_F SSTL18_I_F SSTL18_II_F DIFF_SSTL135_F DIFF_SSTL15_F DIFF_SSTL18_I_F DIFF_SSTL18_II_F Notes:
1. This I/O standard is only available in the 3.3V high-range (HR) banks.

0.81 0.81 0.81 0.81 0.81 1.00 1.00 1.00 1.00 1.00 1.00 0.73 0.73 0.76 0.76 0.73 0.77 0.78 0.78 0.73 0.73 0.76 0.76 0.73 0.77 0.78 0.78

2.13 3.80 2.18 1.65 1.61 4.69 3.52 2.59 4.06 2.40 1.87 1.50 1.47 1.85 1.50 1.50 1.47 1.72 1.25 1.26 1.26 1.26 1.28 1.26 1.26 1.23 1.14
Speed Grade -2
0.69 0.69 0.69 0.69 0.69 0.91 0.91 0.91 0.91 0.91 0.91 0.64 0.64 0.67 0.67 0.61 0.67 0.69 0.69 0.64 0.64 0.67 0.67 0.61 0.67 0.69 0.69
Units -1
3.12 4.79 3.17 2.64 2.60 5.68 4.51 3.58 5.05 3.39 2.86 2.49 2.46 2.84 2.49 2.49 2.46 2.71 2.24 2.25 2.25 2.25 2.27 2.25 2.25 2.22 2.13 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-3
1.76 3.39 1.79 1.40 1.37 3.85 2.52 2.06 3.44 1.72 1.54 1.27 1.24 1.59 1.27 1.27 1.24 1.50 1.13 1.04 1.04 1.12 1.05 1.04 1.04 1.10 1.02
-2
1.95 3.60 1.99 1.54 1.51 4.22 2.96 2.31 3.73 2.04 1.71 1.40 1.37 1.74 1.40 1.40 1.37 1.63 1.22 1.17 1.17 1.22 1.18 1.17 1.17 1.19 1.10
-3
2.52 4.15 2.55 2.16 2.13 4.61 3.28 2.82 4.20 2.48 2.30 2.03 2.00 2.35 2.03 2.03 2.00 2.26 1.89 1.80 1.80 1.88 1.81 1.80 1.80 1.86 1.78
-2
2.81 4.46 2.85 2.40 2.37 5.08 3.82 3.17 4.59 2.90 2.57 2.26 2.23 2.60 2.26 2.26 2.23 2.49 2.08 2.03 2.03 2.08 2.04 2.03 2.03 2.05 1.96
0.66 0.66 0.66 0.66 0.66 0.88 0.88 0.88 0.88 0.88 0.88 0.61 0.61 0.64 0.64 0.59 0.63 0.65 0.65 0.61 0.61 0.64 0.64 0.59 0.63 0.65 0.65
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Table 54: 1.8V IOB High Performance (HP) Switching Characteristics

LVDS HSUL_12 DIFF_HSUL_12 HSTL_I_S HSTL_II_S HSTL_I_18_S HSTL_II_18_S HSTL_I_12_S HSTL_I_DCI_S HSTL_II_DCI_S HSTL_II_T_DCI_S HSTL_I_DCI_18_S HSTL_II_DCI_18_S HSTL_II _T_DCI_18_S DIFF_HSTL_I_S DIFF_HSTL_II_S DIFF_HSTL_I_DCI_S DIFF_HSTL_II_DCI_S DIFF_HSTL_I_18_S DIFF_HSTL_II_18_S DIFF_HSTL_I_DCI_18_S DIFF_HSTL_II_DCI_18_S DIFF_HSTL_II _T_DCI_18_S HSTL_I_F HSTL_II_F HSTL_I_18_F HSTL_II_18_F HSTL_I_12_F HSTL_I_DCI_F HSTL_II_DCI_F HSTL_II_T_DCI_F HSTL_I_DCI_18_F HSTL_II_DCI_18_F HSTL_II _T_DCI_18_F DIFF_HSTL_I_F DIFF_HSTL_II_F DIFF_HSTL_I_DCI_F DIFF_HSTL_II_DCI_F 0.75 0.69 0.69 0.68 0.68 0.70 0.70 0.68 0.68 0.68 0.70 0.70 0.70 0.70 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.68 0.68 0.70 0.70 0.68 0.68 0.68 0.70 0.70 0.70 0.70 0.75 0.75 0.75 0.75

0.92 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.92 0.92 0.92 0.92 0.92 0.92 0.92 0.92 0.92 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.92 0.92 0.92 0.92

1.24 2.05 2.05 1.38 1.26 1.34 1.26 1.37 1.33 1.26 1.38 1.33 1.24 1.33 1.38 1.26 1.38 1.26 1.34 1.26 1.33 1.24 1.33 1.22 1.15 1.24 1.16 1.21 1.24 1.15 1.22 1.24 1.16 1.24 1.22 1.15 1.22 1.15
Speed Grade -2
0.79 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.79 0.79 0.79 0.79 0.79 0.79 0.79 0.79 0.79 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.79 0.79 0.79 0.79
Units -1
-3
1.05 1.65 1.65 1.15 1.05 1.12 1.06 1.14 1.11 1.05 1.15 1.11 1.05 1.11 1.15 1.05 1.15 1.05 1.12 1.06 1.11 1.05 1.11 1.02 0.97 1.04 0.98 1.02 1.04 0.97 1.02 1.04 0.98 1.04 1.02 0.97 1.02 0.97
-2
1.17 1.84 1.84 1.28 1.17 1.24 1.18 1.27 1.23 1.17 1.28 1.23 1.16 1.23 1.28 1.17 1.28 1.17 1.24 1.18 1.23 1.16 1.23 1.14 1.08 1.16 1.09 1.13 1.16 1.08 1.14 1.16 1.09 1.16 1.14 1.08 1.14 1.08
-3
1.68 2.29 2.29 1.79 1.69 1.75 1.70 1.78 1.74 1.69 1.78 1.74 1.69 1.74 1.79 1.69 1.78 1.69 1.75 1.70 1.74 1.69 1.74 1.66 1.61 1.68 1.62 1.65 1.67 1.61 1.66 1.67 1.61 1.67 1.66 1.61 1.66 1.61
-2
1.92 2.59 2.59 2.03 1.93 2.00 1.94 2.02 1.99 1.93 2.03 1.99 1.92 1.99 2.03 1.93 2.03 1.93 2.00 1.94 1.99 1.92 1.99 1.90 1.84 1.91 1.85 1.88 1.91 1.84 1.90 1.91 1.85 1.91 1.90 1.84 1.90 1.84
www.xilinx.com 33
Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 54: 1.8V IOB High Performance (HP) Switching Characteristics (Contd)
DIFF_HSTL_I_18_F DIFF_HSTL_II_18_F DIFF_HSTL_I_DCI_18_F DIFF_HSTL_II_DCI_18_F DIFF_HSTL_II _T_DCI_18_F LVCMOS18_S2 LVCMOS18_S4 LVCMOS18_S6 LVCMOS18_S8 LVCMOS18_S12 LVCMOS18_S16 LVCMOS18_F2 LVCMOS18_F4 LVCMOS18_F6 LVCMOS18_F8 LVCMOS18_F12 LVCMOS18_F16 LVCMOS15_S2 LVCMOS15_S4 LVCMOS15_S6 LVCMOS15_S8 LVCMOS15_S12 LVCMOS15_S16 LVCMOS15_F2 LVCMOS15_F4 LVCMOS15_F6 LVCMOS15_F8 LVCMOS15_F12 LVCMOS15_F16 LVCMOS12_S2 LVCMOS12_S4 LVCMOS12_S6 LVCMOS12_S8 LVCMOS12_F2 LVCMOS12_F4 LVCMOS12_F6 LVCMOS12_F8 LVDCI_18 0.75 0.75 0.75 0.75 0.75 0.47 0.47 0.47 0.47 0.47 0.47 0.47 0.47 0.47 0.47 0.47 0.47 0.59 0.59 0.59 0.59 0.59 0.59 0.59 0.59 0.59 0.59 0.59 0.59 0.64 0.64 0.64 0.64 0.64 0.64 0.64 0.64 0.47

0.92 0.92 0.92 0.92 0.92 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.78 0.78 0.78 0.78 0.78 0.78 0.78 0.78 0.60

1.24 1.16 1.24 1.16 1.24 4.85 3.43 2.72 2.52 2.17 1.97 4.48 2.87 2.26 2.04 1.53 1.44 4.45 3.06 2.88 2.49 2.23 2.02 4.18 2.44 2.09 1.61 1.45 1.41 4.48 3.43 2.72 2.51 3.62 2.44 1.70 1.55 2.35
Speed Grade -2
0.79 0.79 0.79 0.79 0.79 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.50
Units -1
-3
1.04 0.98 1.04 0.98 1.04 3.95 2.67 2.14 1.98 1.70 1.57 3.50 2.23 1.80 1.46 1.26 1.19 3.55 2.45 2.24 1.91 1.77 1.62 3.38 2.04 1.47 1.31 1.21 1.18 3.38 2.62 2.05 1.94 2.84 1.97 1.33 1.27 1.99
-2
1.16 1.09 1.16 1.09 1.16 4.28 2.98 2.38 2.21 1.91 1.75 3.87 2.50 2.00 1.72 1.40 1.33 3.89 2.70 2.51 2.16 1.98 1.81 3.69 2.21 1.74 1.46 1.34 1.31 3.80 2.94 2.33 2.18 3.15 2.18 1.51 1.42 2.15
-3
1.68 1.62 1.67 1.61 1.67 4.59 3.31 2.77 2.61 2.34 2.20 4.14 2.87 2.43 2.10 1.89 1.83 4.19 3.08 2.88 2.55 2.41 2.26 4.02 2.68 2.10 1.95 1.84 1.82 4.02 3.26 2.69 2.58 3.48 2.61 1.96 1.91 2.62
-2
1.91 1.85 1.91 1.85 1.91 5.04 3.73 3.14 2.97 2.67 2.51 4.63 3.25 2.76 2.47 2.16 2.08 4.65 3.45 3.26 2.91 2.73 2.56 4.44 2.97 2.50 2.22 2.10 2.07 4.55 3.70 3.08 2.94 3.90 2.93 2.26 2.18 2.91
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LVDCI_15 LVDCI_DV2_18 LVDCI_DV2_15 HSLVDCI_18 HSLVDCI_15 SSTL18_I_S SSTL18_II_S SSTL18_I_DCI_S SSTL18_II_DCI_S SSTL18_II_T_DCI_S SSTL15_S SSTL15_DCI_S SSTL15_T_DCI_S SSTL135_S SSTL135_DCI_S SSTL135_T_DCI_S SSTL12_S SSTL12_DCI_S SSTL12_T_DCI_S DIFF_SSTL18_I_S DIFF_SSTL18_II_S DIFF_SSTL18_I_DCI_S DIFF_SSTL18_II_DCI_S DIFF_SSTL18_II_T_DCI_S DIFF_SSTL15_S DIFF_SSTL15_DCI_S DIFF_SSTL15_T_DCI_S DIFF_SSTL135_S DIFF_SSTL135_DCI_S DIFF_SSTL135_T_DCI_S DIFF_SSTL12_S DIFF_SSTL12_DCI_S DIFF_SSTL12_T_DCI_S SSTL18_I_F SSTL18_II_F SSTL18_I_DCI_F SSTL18_II_DCI_F SSTL18_II_T_DCI_F 0.59 0.47 0.59 0.68 0.68 0.68 0.68 0.68 0.68 0.68 0.68 0.68 0.68 0.69 0.69 0.69 0.69 0.69 0.69 0.75 0.75 0.75 0.75 0.75 0.68 0.68 0.68 0.69 0.69 0.69 0.69 0.69 0.69 0.68 0.68 0.68 0.68 0.68

0.73 0.60 0.73 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.92 0.92 0.92 0.92 0.92 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82

2.58 2.34 2.58 2.35 2.58 1.24 1.37 1.17 1.08 1.17 1.15 1.15 1.15 1.19 1.19 1.19 1.18 1.27 1.27 1.24 1.37 1.17 1.08 1.17 1.15 1.15 1.15 1.19 1.19 1.19 1.18 1.27 1.27 1.15 1.16 1.10 1.10 1.10
Speed Grade -2
0.62 0.50 0.62 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.79 0.79 0.79 0.79 0.79 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72
Units -1
-3
1.98 1.99 1.98 1.99 1.98 1.02 1.17 0.92 0.88 0.92 0.94 0.94 0.94 0.97 0.97 0.97 0.96 1.03 1.03 1.02 1.17 0.92 0.88 0.92 0.94 0.94 0.94 0.97 0.97 0.97 0.96 1.03 1.03 0.94 0.97 0.89 0.89 0.89
-2
2.23 2.15 2.23 2.15 2.23 1.15 1.29 1.06 0.98 1.06 1.06 1.06 1.06 1.10 1.09 1.09 1.09 1.17 1.17 1.15 1.29 1.06 0.98 1.06 1.06 1.06 1.06 1.10 1.09 1.09 1.09 1.17 1.17 1.06 1.09 1.02 1.02 1.02
-3
2.62 2.62 2.62 2.62 2.62 1.66 1.81 1.56 1.51 1.56 1.58 1.57 1.57 1.60 1.60 1.60 1.60 1.66 1.66 1.66 1.81 1.56 1.51 1.56 1.58 1.57 1.57 1.60 1.60 1.60 1.60 1.66 1.66 1.58 1.61 1.53 1.53 1.53
-2
2.99 2.90 2.99 2.91 2.99 1.90 2.05 1.82 1.74 1.82 1.82 1.82 1.82 1.85 1.85 1.85 1.84 1.92 1.92 1.90 2.05 1.82 1.74 1.82 1.82 1.82 1.82 1.85 1.85 1.85 1.84 1.92 1.92 1.82 1.84 1.77 1.77 1.77
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SSTL15_F SSTL15_DCI_F SSTL15_T_DCI_F SSTL135_F SSTL135_DCI_F SSTL135_T_DCI_F SSTL12_F SSTL12_DCI_F SSTL12_T_DCI_F DIFF_SSTL18_I_F DIFF_SSTL18_II_F DIFF_SSTL18_I_DCI_F DIFF_SSTL18_II_DCI_F DIFF_SSTL18_II_T_DCI_F DIFF_SSTL15_F DIFF_SSTL15_DCI_F DIFF_SSTL15_T_DCI_F DIFF_SSTL135_F DIFF_SSTL135_DCI_F DIFF_SSTL135_T_DCI_F DIFF_SSTL12_F DIFF_SSTL12_DCI_F DIFF_SSTL12_T_DCI_F Notes:
1. This I/O standard is only available in the 1.8V high-performance (HP) banks.

0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.92 0.92 0.92 0.92 0.92 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82

1.09 1.09 1.09 1.08 1.08 1.08 1.08 1.11 1.11 1.15 1.16 1.10 1.10 1.10 1.09 1.09 1.09 1.08 1.08 1.08 1.08 1.11 1.11
Speed Grade -2
0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.79 0.79 0.79 0.79 0.79 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72
Units -1
1.91 1.91 1.91 1.90 1.90 1.90 1.90 1.93 1.93 1.97 1.99 1.92 1.92 1.92 1.91 1.91 1.91 1.90 1.90 1.90 1.90 1.93 1.93 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-3
0.89 0.89 0.89 0.88 0.89 0.89 0.88 0.91 0.91 0.94 0.97 0.89 0.89 0.89 0.89 0.89 0.89 0.88 0.89 0.89 0.88 0.91 0.91
-2
1.01 1.01 1.01 1.00 1.00 1.00 1.00 1.03 1.03 1.06 1.09 1.02 1.02 1.02 1.01 1.01 1.01 1.00 1.00 1.00 1.00 1.03 1.03
-3
1.53 1.53 1.53 1.52 1.52 1.52 1.52 1.54 1.54 1.58 1.61 1.53 1.53 1.53 1.53 1.53 1.53 1.52 1.52 1.52 1.52 1.54 1.54
-2
1.77 1.77 1.77 1.76 1.76 1.76 1.76 1.79 1.79 1.82 1.84 1.77 1.77 1.77 1.77 1.77 1.77 1.76 1.76 1.76 1.76 1.79 1.79
0.68 0.68 0.68 0.69 0.69 0.69 0.69 0.69 0.69 0.75 0.75 0.75 0.75 0.75 0.68 0.68 0.68 0.69 0.69 0.69 0.69 0.69 0.69
Table 55 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster than TIOTPHZ when the DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than TIOTPHZ when the INTERMDISABLE pin is used. Table 55: IOB 3-state Output Switching Characteristics
Symbol
TIOTPHZ TIOIBUFDISABLE_HR TIOIBUFDISABLE_HP
Description
T input to pad high-impedance IBUF turn-on time from IBUFDISABLE to O output for HR I/O banks IBUF turn-on time from IBUFDISABLE to O output for HP I/O banks
Speed Grade -3
0.76 1.72 1.31
-2
0.86 1.89 1.46
-1
0.99 2.14 1.76
Units
ns ns ns
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Input/Output Logic Switching Characteristics

Table 56: ILOGIC Switching Characteristics
Symbol
Setup/Hold TICE1CK/TICKCE1 TISRCK/TICKSR TIDOCKE2/TIOCKDE2 CE1 pin setup/hold with respect to CLK SR pin setup/hold with respect to CLK D pin setup/hold with respect to CLK without delay (HP I/O banks only) 0.42/0.00 0.53/0.01 0.01/0.27 0.01/0.27 0.01/0.27 0.01/0.27 0.48/0.00 0.61/0.01 0.01/0.29 0.02/0.29 0.01/0.29 0.02/0.29 0.67/0.00 0.99/0.01 0.01/0.34 0.02/0.34 0.01/0.34 0.02/0.34 ns ns ns ns ns ns
Description
Units
TIDOCKDE2/TIOCKDDE2 DDLY pin setup/hold with respect to CLK (using IDELAY) (HP I/O banks only) TIDOCKE3/TIOCKDE3 D pin setup/hold with respect to CLK without delay (HR I/O banks only)
TIDOCKDE3/TIOCKDDE3 DDLY pin setup/hold with respect to CLK (using IDELAY) (HR I/O banks only) Combinatorial TIDIE2 TIDIDE2 TIDIE3 TIDIDE3 Sequential Delays TIDLOE2 TIDLODE2 TIDLOE3 TIDLODE3 TICKQ TRQ_ILOGICE2 TGSRQ_ILOGICE2 TRQ_ILOGICE3 TGSRQ_ILOGICE3 Set/Reset TRPW_ILOGICE2 TRPW_ILOGICE3 Minimum pulse width, SR inputs (HP I/O banks only) Minimum pulse width, SR inputs (HR I/O banks only) D pin to Q1 pin using flip-flop as a latch without delay (HP I/O banks only) DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY) (HP I/O banks only) D pin to Q1 pin using flip-flop as a latch without delay (HR I/O banks only) DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY) (HR I/O banks only) CLK to Q outputs SR pin to OQ/TQ out (HP I/O banks only) Global set/reset to Q outputs (HP I/O banks only) SR pin to OQ/TQ out (HR I/O banks only) Global set/reset to Q outputs (HR I/O banks only) D pin to O pin propagation delay, no delay (HP I/O banks only) DDLY pin to O pin propagation delay (using IDELAY) (HP I/O banks only) D pin to O pin propagation delay, no delay (HR I/O banks only) DDLY pin to O pin propagation delay (using IDELAY) (HR I/O banks only)
0.09 0.10 0.09 0.10
0.10 0.11 0.10 0.11
0.12 0.13 0.12 0.13
ns ns ns ns
0.36 0.36 0.36 0.36 0.47 0.84 7.60 0.84 7.60
0.39 0.39 0.39 0.39 0.50 0.94 7.60 0.94 7.60
0.45 0.45 0.45 0.45 0.58 1.16 10.51 1.16 10.51
ns ns ns ns ns ns ns ns ns
0.54 0.54
0.63 0.63
0.63 0.63
ns, Min ns, Min
www.xilinx.com 37
Table 57: OLOGIC Switching Characteristics

Symbol Setup/Hold
TODCK/TOCKD TOOCECK/TOCKOCE TOSRCK/TOCKSR TOTCK/TOCKT TOTCECK/TOCKTCE D1/D2 pins setup/hold with respect to CLK OCE pin setup/hold with respect to CLK SR pin setup/hold with respect to CLK T1/T2 pins setup/hold with respect to CLK TCE pin setup/hold with respect to CLK 0.59/0.13 0.28/0.03 0.32/0.18 0.60/0.16 0.28/0.01 0.62/0.13 0.29/0.03 0.38/0.18 0.64/0.16 0.30/0.01 0.74/0.13 0.45/0.03 0.70/0.18 0.78/0.16 0.45/0.01 ns ns ns ns ns
Description
Units
Combinatorial
TODQ D1 to OQ out or T1 to TQ out 0.73 0.81 0.97 ns
Sequential Delays
TOCKQ TRQ_OLOGICE2 TGSRQ_OLOGICE2 TRQ_OLOGICE3 TGSRQ_OLOGICE3 CLK to OQ/TQ out SR pin to OQ/TQ out (HP I/O banks only) Global set/reset to Q outputs (HP I/O banks only) SR pin to OQ/TQ out (HR I/O banks only) Global set/reset to Q outputs (HR I/O banks only) 0.41 0.63 7.60 0.63 7.60 0.43 0.70 7.60 0.70 7.60 0.49 0.83 10.51 0.83 10.51 ns ns ns ns ns
Set/Reset
TRPW_OLOGICE2 TRPW_OLOGICE3 Minimum pulse width, SR inputs (HP I/O banks only) Minimum pulse width, SR inputs (HR I/O banks only) 0.54 0.54 0.54 0.54 0.63 0.63 ns, Min ns, Min
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Input Serializer/Deserializer Switching Characteristics

Table 58: ISERDES Switching Characteristics
Symbol Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP TISCCK_CE / TISCKC_CE TISCCK_CE2 /
(2)
Description
Units
BITSLIP pin setup/hold with respect to CLKDIV CE pin setup/hold with respect to CLK (for CE1) CE pin setup/hold with respect to CLKDIV (for CE2)
0.01/0.12 0.39/0.02 0.12/0.29
0.02/0.13 0.44/0.02 0.12/0.31
0.02/0.15 0.63/0.02 0.12/0.35
ns ns ns
TISCKC_CE2(2)
Setup/Hold for Data Lines

TISDCK_D /TISCKD_D TISDCK_DDLY /TISCKD_DDLY TISDCK_D_DDR /TISCKD_D_DDR TISDCK_DDLY_DDR/ TISCKD_DDLY_DDR D pin setup/hold with respect to CLK DDLY pin setup/hold with respect to CLK (using IDELAY)(1) D pin setup/hold with respect to CLK at DDR mode D pin setup/hold with respect to CLK at DDR mode (using IDELAY)(1) 0.02/0.11 0.02/0.11 0.02/0.11 0.11/0.11 0.02/0.12 0.02/0.12 0.02/0.12 0.12/0.12 0.02/0.15 0.02/0.15 0.02/0.15 0.15/0.15 ns ns ns ns
Sequential Delays
TISCKO_Q CLKDIV to out at Q pin 0.46 0.47 0.58 ns
Propagation Delays
TISDO_DO Notes:
1. 2. Recorded at 0 tap value. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in TRACE report.
D input to DO output pin
0.09
0.10
0.12
ns
Output Serializer/Deserializer Switching Characteristics

Table 59: OSERDES Switching Characteristics
Symbol
Setup/Hold TOSDCK_D/TOSCKD_D TOSDCK_T/TOSCKD_T(1) TOSDCK_T2/TOSCKD_T2 TOSCCK_S TOSCCK_TCE/TOSCKC_TCE Sequential Delays TOSCKO_OQ TOSCKO_TQ Combinatorial TOSDO_TTQ Notes:
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in TRACE report.
(1)
Description
Units
D input setup/hold with respect to CLKDIV T input setup/hold with respect to CLK T input setup/hold with respect to CLKDIV OCE input setup/hold with respect to CLK SR (reset) input setup with respect to CLKDIV TCE input setup/hold with respect to CLK
0.37/0.02 0.60/0.15 0.27/0.15 0.28/0.03 0.41 0.28/0.01
0.40/0.02 0.64/0.15 0.30/0.15 0.29/0.03 0.46 0.30/0.01
0.55/0.02 0.77/0.15 0.34/0.15 0.45/0.03 0.75 0.45/0.01
ns ns ns ns ns ns
TOSCCK_OCE/TOSCKC_OCE
Clock to out from CLK to OQ Clock to out from CLK to TQ
0.35 0.41
0.37 0.43
0.42 0.49
ns ns
T input to TQ out
0.73
0.81
0.97
ns
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Input/Output Delay Switching Characteristics

Table 60: Input/Output Delay Switching Characteristics
Symbol
IDELAYCTRL TDLYCCO_RDY FIDELAYCTRL_REF
IDELAYCTRL_REF_PRECISION
Description
Units
Reset to ready for IDELAYCTRL Attribute REFCLK frequency = Attribute REFCLK frequency = REFCLK precision Minimum reset pulse width 200.0(1) 300.0(1)
3.22 200 300 10 52.00
3.22 200 300 10 52.00
3.22 200 N/A 10 52.00
s MHz MHz MHz ns
TIDELAYCTRL_RPW IDELAY/ODELAY TIDELAYRESOLUTION
IDELAY/ODELAY chain delay resolution Pattern dependent period jitter in delay chain for clock pattern.(2) 0 5 9 800
1/(32 x 2 x FREF) 0 5 9 800 0.14/0.12 0.16/0.04 0.12/0.16 0.12/0.08 0.14/0.10 0.19/0.06 Note 5 Note 5 0 5 9 710 0.18/0.14 0.19/0.05 0.14/0.20 0.13/0.09 0.16/0.12 0.24/0.08 Note 5 Note 5
ps ps per tap ps per tap ps per tap MHz ns ns ns ns ns ns ps ps
TIDELAYPAT_JIT and TODELAYPAT_JIT
Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)(3) Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)(4)
TIDELAY_CLK_MAX/TODELAY_CLK_MAX TIDCCK_CE / TIDCKC_CE TODCCK_CE / TODCKC_CE TIDCCK_INC/ TIDCKC_INC TODCCK_INC/ TODCKC_INC TIDCCK_RST/ TIDCKC_RST TODCCK_RST/ TODCKC_RST TIDDO_IDATAIN TODDO_ODATAIN Notes:
1. 2. 3. 4. 5.
Maximum frequency of CLK input to IDELAY/ODELAY CE pin setup/hold with respect to C for IDELAY CE pin setup/hold with respect to C for ODELAY INC pin setup/hold with respect to C for IDELAY INC pin setup/hold with respect to C for ODELAY RST pin setup/hold with respect to C for IDELAY RST pin setup/hold with respect to C for ODELAY Propagation delay through IDELAY Propagation delay through ODELAY
0.11/0.10 0.14/0.03 0.10/0.14 0.10/0.07 0.13/0.08 0.16/0.04 Note 5 Note 5
Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps. When HIGH_PERFORMANCE mode is set to TRUE or FALSE. When HIGH_PERFORMANCE mode is set to TRUE. When HIGH_PERFORMANCE mode is set to FALSE. Delay depends on IDELAY/ODELAY tap setting. See TRACE report for actual values.
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Table 61: IO_FIFO Switching Characteristics

Symbol
IO_FIFO Clock to Out Delays TOFFCKO_DO TCKO_FLAGS Setup/Hold TCCK_D/TCKC_D TIFFCCK_WREN /TIFFCKC_WREN TOFFCCK_RDEN/TOFFCKC_RDEN Minimum Pulse Width TPWH_IO_FIFO TPWL_IO_FIFO Maximum Frequency FMAX RDCLK and WRCLK 533 470 400 MHz RESET, RDCLK, WRCLK RESET, RDCLK, WRCLK 0.81 0.81 0.92 0.92 1.08 1.08 ns ns D inputs to WRCLK WREN to WRCLK RDEN to RDCLK 0.43/0.01 0.39/0.01 0.49/0.01 0.47/0.01 0.43/0.01 0.53/0.02 0.53/0.01 0.50/0.01 0.61/0.02 ns ns ns RDCLK to Q outputs Clock to IO_FIFO flags 0.51 0.59 0.56 0.62 0.63 0.81 ns ns
Description
Units
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CLB Switching Characteristics

Table 62: CLB Switching Characteristics
Symbol
Combinatorial Delays TILO TILO_2 TILO_3 TITO TAXA TAXB TAXC TAXD TBXB TBXD TCXC TCXD TDXD Sequential Delays TCKO TSHCKO TAS/TAH TDICK/TCKDI Clock to AQ DQ outputs Clock to AMUX DMUX outputs 0.26 0.32 0.27 0.32 0.32 0.39 ns, Max ns, Max An Dn LUT address to A An Dn LUT address to AMUX/CMUX An Dn LUT address to BMUX_A An Dn inputs to A D Q outputs AX inputs to AMUX output AX inputs to BMUX output AX inputs to CMUX output AX inputs to DMUX output BX inputs to BMUX output BX inputs to DMUX output CX inputs to CMUX output CX inputs to DMUX output DX inputs to DMUX output 0.05 0.15 0.24 0.58 0.38 0.40 0.39 0.43 0.31 0.38 0.27 0.33 0.32 0.05 0.16 0.25 0.61 0.40 0.42 0.41 0.44 0.33 0.39 0.28 0.34 0.33 0.06 0.19 0.30 0.74 0.49 0.52 0.50 0.52 0.40 0.47 0.34 0.41 0.40 ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
Description
Units
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK AN DN input to CLK on A D flip-flops AX DX input to CLK on A D flip-flops AX DX input through MUXs and/or carry logic to CLK on A D flip-flops TCECK_CLB/TCKCE_CLB TSRCK/TCKSR Set/Reset TSRMIN TRQ TCEO FTOG SR input minimum pulse width Delay from SR input to AQ DQ flip-flops Delay from CE input to AQ DQ flip-flops Toggle frequency (for export control) 0.52 0.38 0.34 1818 0.78 0.38 0.35 1818 1.04 0.46 0.43 1818 ns, Min ns, Max ns, Max MHz CE input to CLK on A D flip-flops SR input to CLK on A D flip-flops 0.01/0.12 0.04/0.14 0.36/0.10 0.19/0.05 0.30/0.05 0.02/0.13 0.04/0.14 0.37/0.11 0.20/0.05 0.31/0.07 0.03/0.18 0.05/0.20 0.46/0.16 0.25/0.05 0.37/0.09 ns, Min ns, Min ns, Min ns, Min ns, Min
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CLB Distributed RAM Switching Characteristics (SLICEM Only)

Table 63: CLB Distributed RAM Switching Characteristics
Symbol
Sequential Delays TSHCKO TSHCKO_1 TDS_LRAM/TDH_LRAM TAS_LRAM/TAH_LRAM TWS_LRAM/TWH_LRAM Clock CLK TMPW_LRAM TMCP Notes:
1. 2. A Zero 0 hold time listing indicates no hold time or a negative hold time. TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
Description
Units
Clock to A B outputs Clock to AMUX BMUX outputs
0.68 0.91
0.70 0.95
0.85 1.15
ns, Max ns, Max
Setup and Hold Times Before/After Clock CLK A D inputs to CLK Address An inputs to clock 0.45/0.23 0.13/0.50 0.45/0.24 0.14/0.50 0.42/0.17 0.30/0.09 0.30/0.09 0.54/0.27 0.17/0.58 0.52/0.23 0.36/0.09 0.37/0.09 ns, Min ns, Min ns, Min ns, Min ns, Min
Address An inputs through MUXs and/or carry logic to clock 0.40/0.16 WE input to clock 0.29/0.09 0.29/0.09
TCECK_LRAM/TCKCE_LRAM CE input to CLK Minimum pulse width Minimum clock period
0.68 1.35
0.77 1.54
0.91 1.82
ns, Min ns, Min
CLB Shift Register Switching Characteristics (SLICEM Only)

Table 64: CLB Shift Register Switching Characteristics
Symbol
Sequential Delays TREG TREG_MUX TREG_M31 TWS_SHFREG/TWH_SHFREG TCECK_SHFREG/TCKCE_SHFREG TDS_SHFREG/TDH_SHFREG Clock CLK TMPW_SHFREG Notes:
1. A Zero 0 hold time listing indicates no hold time or a negative hold time.
Description
Units
Clock to A D outputs Clock to AMUX DMUX output Clock to DMUX output via M31 output
0.96 1.19 0.89
0.98 1.23 0.91
1.20 1.50 1.10
ns, Max ns, Max ns, Max
Setup and Hold Times Before/After Clock CLK WE input CE input to CLK A D inputs to CLK 0.26/0.09 0.27/0.09 0.28/0.26 0.27/0.09 0.28/0.09 0.28/0.26 0.33/0.09 0.33/0.09 0.33/0.30 ns, Min ns, Min ns, Min
Minimum pulse width
0.55
0.65
0.78
ns, Min
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Block RAM and FIFO Switching Characteristics

Table 65: Block RAM and FIFO Switching Characteristics
Symbol
Block RAM and FIFO Clock-to-Out Delays TRCKO_DO and TRCKO_DO_REG(1) Clock CLK to DOUT output (without output register)(2)(3) Clock CLK to DOUT output (with output register)(4)(5) TRCKO_DO_ECC and TRCKO_DO_ECC_REG Clock CLK to DOUT output with ECC (without output register)(2)(3) Clock CLK to DOUT output with ECC (with output register)(4)(5) TRCKO_DO_CASCOUT and TRCKO_DO_CASCOUT_REG Clock CLK to DOUT output with Cascade (without output register)(2) Clock CLK to DOUT output with Cascade (with output register)(4) TRCKO_FLAGS TRCKO_POINTERS TRCKO_PARITY_ECC TRCKO_SDBIT_ECC and TRCKO_SDBIT_ECC_REG TRCKO_RDADDR_ECC and TRCKO_RDADDR_ECC_REG Clock CLK to FIFO flags outputs(6) Clock CLK to FIFO pointers outputs(7) 1.78 0.54 2.35 0.62 2.21 0.98 0.65 0.79 0.66 2.17 0.57 0.64 0.71 1.80 0.63 2.58 0.69 2.45 1.08 0.74 0.87 0.72 2.38 0.65 0.74 0.79 2.08 0.75 3.26 0.80 2.80 1.24 0.89 0.98 0.80 3.01 0.76 0.90 0.92 ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
Description
Units
Clock CLK to ECCPARITY in ECC encode only mode Clock CLK to BITERR (without output register) Clock CLK to BITERR (with output register) Clock CLK to RDADDR output with ECC (without output register) Clock CLK to RDADDR output with ECC (with output register)
Setup and Hold Times Before/After Clock CLK TRCCK_ADDRA/TRCKC_ADDRA TRDCK_DI_WF_NC/ TRCKD_DI_WF_NC TRDCK_DI_RF/TRCKD_DI_RF TRDCK_DI_ECC/TRCKD_DI_ECC TRDCK_DI_ECCW/TRCKD_DI_ECCW TRDCK_DI_ECC_FIFO/ TRCKD_DI_ECC_FIFO TRCCK_INJECTBITERR/ TRCKC_INJECTBITERR TRCCK_EN/TRCKC_EN TRCCK_REGCE/TRCKC_REGCE TRCCK_RSTREG/TRCKC_RSTREG TRCCK_RSTRAM/TRCKC_RSTRAM TRCCK_WEA/TRCKC_WEA TRCCK_WREN/TRCKC_WREN TRCCK_RDEN/TRCKC_RDEN DS191 (v1.1) August 31, 2012 Advance Product Specification ADDR inputs(8) Data input setup/hold time when block RAM is configured in WRITE_FIRST or NO_CHANGE mode(9) Data input setup/hold time when block RAM is configured in READ_FIRST mode(9) DIN inputs with block RAM ECC in standard mode(9) DIN inputs with block RAM ECC encode only(9) DIN inputs with FIFO ECC in standard mode(9) Inject single/double bit error in ECC mode Block RAM Enable (EN) input CE input of output register Synchronous RSTREG input Synchronous RSTRAM input Write Enable (WE) input (Block RAM only) WREN FIFO inputs RDEN FIFO inputs 0.38/0.27 0.49/0.51 0.42/0.28 0.55/0.53 0.48/0.31 0.63/0.57 ns, Min ns, Min
0.17/0.25 0.42/0.37 0.79/0.37 0.89/0.47 0.49/0.30 0.30/0.17 0.21/0.13 0.25/0.06 0.27/0.35 0.38/0.15 0.39/0.25 0.36/0.26
0.19/0.29 0.47/0.39 0.87/0.39 0.98/0.50 0.55/0.31 0.33/0.18 0.25/0.13 0.27/0.06 0.29/0.37 0.41/0.16 0.39/0.30 0.36/0.30
0.21/0.35 0.53/0.43 0.99/0.43 1.12/0.54 0.63/0.34 0.38/0.20 0.31/0.14 0.29/0.06 0.31/0.39 0.46/0.17 0.40/0.37 0.37/0.37
ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 65: Block RAM and FIFO Switching Characteristics (Contd)
Symbol
Reset Delays TRCO_FLAGS TRREC_RST/TRREM_RST Maximum Frequency FMAX_BRAM_WF_NC FMAX_BRAM_RF_PERFORMANCE Block RAM (Write first and No change modes) When not in SDP RF mode Block RAM (Read first, Performance mode) When in SDP RF mode but no address overlap between port A and port B Block RAM (Read first, Delayed_write mode) When in SDP RF mode and there is possibility of overlap between port A and port B addresses Block RAM Cascade (Write first, No change mode) When cascade but not in RF mode Block RAM Cascade (Read first, Performance mode) When in cascade with RF mode and no possibility of address overlap/one port is disabled When in cascade RF mode and there is a possibility of address overlap between port A and port B FIFO in all modes without ECC Block RAM and FIFO in ECC configuration 601 601 543 543 458 458 MHz MHz Reset RST to FIFO flags/pointers(10) FIFO reset recovery and removal timing(11) 0.76 0.83 0.93 ns, Max ns, Max
Description
Units
1.59/0.68 1.76/0.68 2.01/0.68
FMAX_BRAM_RF_DELAYED_WRITE
528
477
400
MHz
FMAX_CAS_WF_NC
551
493
408
MHz
FMAX_CAS_RF_PERFORMANCE
551
493
408
MHz
FMAX_CAS_RF_DELAYED_WRITE
478
427
350
MHz
FMAX_FIFO FMAX_ECC Notes:

1. 2. 3. 4. 5. 6. 7. 8.
601 484
543 430
458 351
MHz MHz
TRACE will report all of these parameters as TRCKO_DO. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. These parameters also apply to synchronous FIFO with DO_REG = 0. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 9. These parameters include both A and B inputs as well as the parity inputs of A and B. 10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. 11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the slowest clock (WRCLK or RDCLK).
www.xilinx.com 45
DSP48E1 Switching Characteristics

Table 66: DSP48E1 Switching Characteristics
Symbol Description Speed Grade -3 -2 -1 Units
Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_A_AREG/ TDSPCKD_A_AREG TDSPDCK_B_BREG/TDSPCKD_B_BREG TDSPDCK_C_CREG/TDSPCKD_C_CREG TDSPDCK_D_DREG/TDSPCKD_D_DREG TDSPDCK_ACIN_AREG/TDSPCKD_ACIN_AREG TDSPDCK_BCIN_BREG/TDSPCKD_BCIN_BREG TDSPDCK_{A, B}_MREG_MULT/ TDSPCKD_B_MREG_MULT TDSPDCK_{A, B}_ADREG/ TDSPCKD_ D_ADREG A input to A register CLK B input to B register CLK C input to C register CLK D input to D register CLK ACIN input to A register CLK BCIN input to B register CLK 0.24/0.12 0.28/0.13 0.15/0.15 0.21/0.19 0.21/0.12 0.22/0.13 0.27/0.14 0.32/0.14 0.17/0.17 0.27/0.22 0.24/0.14 0.25/0.14 0.31/0.16 0.39/0.15 0.20/0.20 0.35/0.26 0.27/0.16 0.30/0.15 ns ns ns ns ns ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock {A, B,} input to M register CLK using multiplier {A, D} input to AD register CLK 2.04/0.01 2.34/0.01 2.79/0.01 1.09/0.02 1.25/0.02 1.49/0.02 ns ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{A, B}_PREG_MULT/ TDSPCKD_{A, B} _PREG_MULT

TDSPDCK_D_PREG_MULT/ TDSPCKD_D_PREG_MULT
{A, B,} input to P register CLK using multiplier D input to P register CLK using multiplier
3.41/0.24 3.90/0.24 4.64/0.24 3.33/0.62 3.81/0.62 4.53/0.62
ns ns ns ns ns
TDSPDCK_{A, B} _PREG/ TDSPCKD_{A, B} _PREG

TDSPDCK_C_PREG/ TDSPCKD_C_PREG TDSPDCK_PCIN_PREG/ TDSPCKD_PCIN_PREG Setup and Hold Times of the CE Pins
A or B input to P register CLK not using 1.47/0.24 1.68/0.24 2.00/0.24 multiplier C input to P register CLK not using multiplier PCIN input to P register CLK 1.30/0.22 1.49/0.22 1.78/0.22 1.12/0.13 1.28/0.13 1.52/0.13
TDSPDCK_{CEA;CEB}_{AREG;BREG}/ TDSPCKD_{CEA;CEB}_{AREG;BREG}
TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG Setup and Hold Times of the RST Pins
{CEA; CEB} input to {A; B} register CLK 0.30/0.05 CEC input to C register CLK CED input to D register CLK CEM input to M register CLK CEP input to P register CLK 0.24/0.08
0.36/0.06 0.29/0.09
0.44/0.09 0.36/0.11
ns ns ns ns ns
0.31/0.02 0.36/0.02 0.44/0.02 0.26/0.15 0.31/0.01 0.29/0.17 0.36/0.01 0.33/0.20 0.45/0.01
TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ TDSPCKD_{RSTA; RSTB}_{AREG; BREG}

TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG TDSPDO_A_CARRYOUT_MULT TDSPDO_D_P_MULT TDSPDO_A_P TDSPDO_C_P DS191 (v1.1) August 31, 2012 Advance Product Specification
{RSTA, RSTB} input to {A, B} register CLK RSTC input to C register CLK RSTD input to D register CLK RSTM input to M register CLK RSTP input to P register CLK
0.34/0.10 0.06/0.22 0.37/0.06 0.18/0.18 0.24/0.01
0.39/0.11 0.07/0.24 0.42/0.06 0.20/0.21 0.26/0.01
0.47/0.13 0.08/0.26 0.50/0.07 0.23/0.24 0.30/0.01
ns ns ns ns ns
Combinatorial Delays from Input Pins to Output Pins A input to CARRYOUT output using multiplier D input to P output using multiplier A input to P output not using multiplier C input to P output 3.21 3.15 1.30 1.13 3.69 3.61 1.48 1.30 4.39 4.30 1.76 1.55 ns ns ns ns
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 66: DSP48E1 Switching Characteristics (Contd)
Combinatorial Delays from Input Pins to Cascading Output Pins TDSPDO_{A; B}_{ACOUT; BCOUT} TDSPDO_{A, B}_CARRYCASCOUT_MULT TDSPDO_D_CARRYCASCOUT_MULT TDSPDO_{A, B}_CARRYCASCOUT TDSPDO_C_CARRYCASCOUT TDSPDO_ACIN_P_MULT TDSPDO_ACIN_P TDSPDO_ACIN_ACOUT TDSPDO_ACIN_CARRYCASCOUT_MULT TDSPDO_ACIN_CARRYCASCOUT TDSPDO_PCIN_P TDSPDO_PCIN_CARRYCASCOUT TDSPCKO_P_PREG TDSPCKO_CARRYCASCOUT_PREG {A, B} input to {ACOUT, BCOUT} output {A, B} input to CARRYCASCOUT output using multiplier D input to CARRYCASCOUT output using multiplier {A, B} input to CARRYCASCOUT output not using multiplier C input to CARRYCASCOUT output 0.47 3.44 3.36 1.50 1.34 0.53 3.94 3.85 1.72 1.53 0.63 4.69 4.58 2.04 1.83 ns ns ns ns ns
Combinatorial Delays from Cascading Input Pins to All Output Pins ACIN input to P output using multiplier ACIN input to P output not using multiplier ACIN input to ACOUT output ACIN input to CARRYCASCOUT output using multiplier ACIN input to CARRYCASCOUT output not using multiplier PCIN input to P output PCIN input to CARRYCASCOUT output 3.09 1.16 0.32 3.30 1.37 0.94 1.15 3.55 1.33 0.37 3.79 1.57 1.08 1.32 4.24 1.59 0.45 4.52 1.87 1.29 1.57 ns ns ns ns ns ns ns
Clock to Outs from Output Register Clock to Output Pins CLK PREG to P output CLK PREG to CARRYCASCOUT output 0.33 0.44 0.35 0.50 0.39 0.59 ns ns
Clock to Outs from Pipeline Register Clock to Output Pins TDSPCKO_P_MREG TDSPCKO_CARRYCASCOUT_MREG TDSPCKO_P_ADREG_MULT TDSPCKO_CARRYCASCOUT_ADREG_MULT CLK MREG to P output CLK MREG to CARRYCASCOUT output CLK ADREG to P output using multiplier CLK ADREG to CARRYCASCOUT output using multiplier 1.42 1.63 2.30 2.51 1.64 1.87 2.63 2.87 1.96 2.24 3.13 3.41 ns ns ns ns
Clock to Outs from Input Register Clock to Output Pins TDSPCKO_P_AREG_MULT TDSPCKO_P_BREG TDSPCKO_P_CREG TDSPCKO_P_DREG_MULT CLK AREG to P output using multiplier CLK BREG to P output not using multiplier CLK CREG to P output not using multiplier CLK DREG to P output using multiplier 3.34 1.39 1.43 3.32 3.83 1.59 1.64 3.80 4.55 1.88 1.95 4.51 ns ns ns ns
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 66: DSP48E1 Switching Characteristics (Contd)
Clock to Outs from Input Register Clock to Cascading Output Pins TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG} TDSPCKO_CARRYCASCOUT_{AREG, BREG}_MULT CLK (ACOUT, BCOUT) to {A,B} register output CLK (AREG, BREG) to CARRYCASCOUT output using multiplier CLK BREG to CARRYCASCOUT output not using multiplier CLK DREG to CARRYCASCOUT output using multiplier CLK CREG to CARRYCASCOUT output 0.55 3.55 0.62 4.06 0.74 4.84 ns ns
TDSPCKO_CARRYCASCOUT_ BREG TDSPCKO_CARRYCASCOUT_ DREG_MULT TDSPCKO_CARRYCASCOUT_ CREG Maximum Frequency FMAX FMAX_PATDET FMAX_MULT_NOMREG FMAX_MULT_NOMREG_PATDET FMAX_PREADD_MULT_NOADREG FMAX_PREADD_MULT_NOADREG_PATDET FMAX_NOPIPELINEREG FMAX_NOPIPELINEREG_PATDET
1.60 3.52 1.64
1.82 4.03 1.88
2.16 4.79 2.23
ns ns ns
With all registers used With pattern detector Two register multiply without MREG Two register multiply without MREG with pattern detect Without ADREG Without ADREG with pattern detect Without pipeline registers (MREG, ADREG) Without pipeline registers (MREG, ADREG) with pattern detect
741 627 412 374 468 468 306 285
650 549 360 327 408 408 267 249
547 463 303 276 342 342 225 209
MHz MHz MHz MHz MHz MHz MHz MHz
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Clock Buffers and Networks

Table 67: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
TBCCCK_CE/TBCCKC_CE(1) TBCCCK_S/TBCCKC_S(1) TBCCKO_O(2) Maximum Frequency FMAX_BUFG Notes:
1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Description
CE pins setup/hold S pins setup/hold BUFGCTRL delay from I0/I1 to O
Units
ns ns ns
0.12/0.30 0.14/0.38 0.26/0.38 0.12/0.30 0.14/0.38 0.26/0.38 0.08 0.10 0.12
Global clock tree (BUFG)
741
710
625
MHz
2.
Table 68: Input/Output Clock Switching Characteristics (BUFIO)

Symbol
TBIOCKO_O Maximum Frequency FMAX_BUFIO I/O clock tree (BUFIO) 800 800 710 MHz
Description
Clock to out delay from I to O
Speed Grade -3
1.04
-2
1.14
-1
1.32
Units
ns
Table 69: Regional Clock Buffer Switching Characteristics (BUFR)

Symbol
TBRCKO_O TBRCKO_O_BYP TBRDO_O Maximum Frequency FMAX_BUFR(1) Notes:
1. The maximum input frequency to the BUFR is the BUFIO FMAX frequency.
Description
Clock to out delay from I to O Clock to out delay from I to O with Divide Bypass attribute set Propagation delay from CLR to O
Speed Grade -3
0.60 0.30 0.71
-2
0.65 0.32 0.75
-1
0.77 0.38 0.96
Units
ns ns ns
Regional clock tree (BUFR)
600
540
450
MHz
Table 70: Horizontal Clock Buffer Switching Characteristics (BUFH)

Symbol
TBHCKO_O TBHCCK_CE/TBHCKC_CE Maximum Frequency FMAX_BUFH Horizontal clock buffer (BUFH) 741 710 625 MHz BUFH delay from I to O CE pin setup and hold
Description
Speed Grade -3
0.10
-2
0.11
-1
0.13
Units
ns ns
0.20/0.16 0.23/0.20 0.38/0.21
www.xilinx.com 49
Table 71: Duty-Cycle Distortion and Clock-Tree Skew

Symbol
TDCD_CLK TCKSKEW TDCD_BUFIO TBUFIOSKEW TDCD_BUFR Notes:
1. These parameters represent the worst-case duty-cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty-cycle distortion that might be caused by asymmetrical rise/fall times. The TCKSKEWvalue represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer tools to evaluate application specific clock skew.
Description
Global clock tree duty-cycle distortion(1) Global clock tree skew(2)
Device
All XC7Z030 XC7Z045
Speed Grade -3
0.20 0.29 0.43 0.12 0.02 0.15
-2
0.20 0.37 0.54 0.12 0.02 0.15
-1
0.20 0.37 0.57 0.12 0.02 0.15
Units
ns ns ns ns ns ns
I/O clock tree duty-cycle distortion I/O clock tree skew across one clock region Regional clock tree duty-cycle distortion
All All All
2.
MMCM Switching Characteristics

Table 72: MMCM Specification
Symbol
MMCM_FINMAX MMCM_FINMIN MMCM_FINJITTER MMCM_FINDUTY
Description
Maximum input clock frequency Minimum input clock frequency Maximum input clock period jitter Allowable input duty cycle: 1049 MHz Allowable input duty cycle: 50199 MHz Allowable input duty cycle: 200399 MHz Allowable input duty cycle: 400499 MHz Allowable input duty cycle: >500 MHz
Speed Grade -3
1066 10
-2
933 10
-1
800 10
Units
MHz MHz
< 20% of clock input period or 1 ns Max 25 30 35 40 45 0.01 550 600 1600 1.00 4.00 0.12 25 30 35 40 45 0.01 500 600 1440 1.00 4.00 0.12 25 30 35 40 45 0.01 450 600 1200 1.00 4.00 0.12 Note 1 0.20 100 1066 4.69 0.20 100 933 4.69 0.20 100 800 4.69 ns s MHz MHz % % % % % MHz MHz MHz MHz MHz MHz ns
MMCM_FMIN_PSCLK MMCM_FMAX_PSCLK MMCM_FVCOMIN MMCM_FVCOMAX MMCM_FBANDWIDTH
Minimum dynamic phase-shift clock frequency Maximum dynamic phase-shift clock frequency Minimum MMCM VCO frequency Maximum MMCM VCO frequency Low MMCM bandwidth at typical(1) High MMCM bandwidth at typical(1)
MMCM_TSTATPHAOFFSET Static phase offset of the MMCM outputs(2) MMCM_TOUTJITTER MMCM_TOUTDUTY MMCM_TLOCKMAX MMCM_FOUTMAX MMCM_FOUTMIN MMCM_TEXTFDVAR MMCM_RSTMINPULSE MMCM_FPFDMAX MMCM_FPFDMIN MMCM output jitter(3) MMCM output clock duty-cycle precision(4) MMCM maximum lock time MMCM maximum output frequency MMCM minimum output frequency(5)(6) External clock feedback variation Minimum reset pulse width Maximum frequency at the phase frequency detector Minimum frequency at the phase frequency detector
< 20% of clock input period or 1 ns Max 5.00 550 10 5.00 500 10 5.00 450 10 ns MHz MHz
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 72: MMCM Specification (Contd)
Symbol
MMCM_TFBDELAY TMMCMDCK_PSEN/ TMMCMCKD_PSEN TMMCMDCK_PSINCDEC/ TMMCMCKD_PSINCDEC TMMCMCKO_PSDONE TMMCMDCK_DADDR/ TMMCMCKD_DADDR TMMCMDCK_DI/ TMMCMCKD_DI TMMCMDCK_DEN/ TMMCMCKD_DEN TMMCMDCK_DWE/ TMMCMCKD_DWE TMMCMCKO_DRDY FDCK Notes:
1. 2. 3. 4. 5. 6. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. The static offset is measured between any MMCM outputs with identical phase. Values for this parameter are available in the Clocking Wizard. See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm. Includes global clock buffer. Calculated as FVCO/128 assuming output duty cycle is 50%. When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz.
Description
Maximum delay in the feedback path
Units
3 ns Max or one CLKIN cycle
MMCM Switching Characteristics Setup and Hold

Setup and hold of phase-shift enable Setup and hold of phase-shift increment/decrement Phase shift clock-to-out of PSDONE 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 0.59 0.68 0.81 ns ns ns
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
Setup and hold of D address Setup and hold of D input Setup and hold of D enable Setup and hold of D write enable CLK to out of DRDY DCLK frequency 1.25/0.15 1.40/0.15 1.63/0.15 1.25/0.15 1.40/0.15 1.63/0.15 1.76/0.00 1.97/0.00 2.29/0.00 1.25/0.15 1.40/0.15 1.63/0.15 0.65 200 0.72 200 0.99 200 ns, Min ns, Min ns, Min ns, Min ns, Max MHz, Max
PLL Switching Characteristics

Table 73: PLL Specification
Symbol
PLL_FINMAX PLL_FINMIN PLL_FINJITTER PLL_FINDUTY
Description
Maximum input clock frequency Minimum input clock frequency Maximum input clock period jitter Allowable input duty cycle: 1949 MHz Allowable input duty cycle: 50199 MHz Allowable input duty cycle: 200399 MHz Allowable input duty cycle: 400499 MHz Allowable input duty cycle: >500 MHz
Speed Grade -3
1066 19
-2
933 19
-1
800 19
Units
MHz MHz
< 20% of clock input period or 1 ns Max 25 30 35 40 45 800 2133 1.00 4.00 0.12 25 30 35 40 45 800 1866 1.00 4.00 0.12 25 30 35 40 45 800 1600 1.00 4.00 0.12 % % % % % MHz MHz MHz MHz ns
PLL_FVCOMIN PLL_FVCOMAX PLL_FBANDWIDTH PLL_TSTATPHAOFFSET
Minimum PLL VCO frequency Maximum PLL VCO frequency Low PLL bandwidth at High PLL bandwidth at typical(1) typical(1) outputs(2)
Static phase offset of the PLL
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 73: PLL Specification (Contd)
Symbol
PLL_TOUTJITTER PLL_TOUTDUTY PLL_TLOCKMAX PLL_FOUTMAX PLL_FOUTMIN PLL_TEXTFDVAR PLL_RSTMINPULSE PLL_FPFDMAX PLL_FPFDMIN PLL_TFBDELAY TPLLCCK_DADDR/ TPLLCKC_DADDR TPLLCCK_DI/ TPLLCKC_DI TPLLCCK_DEN/ TPLLCKC_DEN TPLLCCK_DWE/ TPLLCKC_DWE TPLLCKO_DRDY FDCK Notes:
1. 2. 3. 4. 5. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. The static offset is measured between any PLL outputs with identical phase. Values for this parameter are available in the Clocking Wizard. See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm. Includes global clock buffer. Calculated as FVCO/128 assuming output duty cycle is 50%.
Description
PLL output jitter(3) PLL output clock duty-cycle precision(4) PLL maximum lock time PLL maximum output frequency PLL minimum output frequency(5) External clock feedback variation Minimum reset pulse width Maximum frequency at the phase frequency detector Minimum frequency at the phase frequency detector Maximum delay in the feedback path
Speed Grade -3 -2
Note 1 0.20 100 1066 6.25 0.20 100 933 6.25 0.20 100 800 6.25
-1
Units
ns s MHz MHz
< 20% of clock input period or 1 ns Max 5.00 550 19 5.00 500 19 5.00 450 19 ns MHz MHz
3 ns Max or one CLKIN cycle
Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK
Setup and hold of D address Setup and hold of D input Setup and hold of D enable Setup and hold of D write enable CLK to out of DRDY DCLK frequency 1.25/0.15 1.40/0.15 1.63/0.15 1.25/0.15 1.40/0.15 1.63/0.15 1.76/0.00 1.97/0.00 2.29/0.00 1.25/0.15 1.40/0.15 1.63/0.15 0.65 200 0.72 200 0.99 200 ns, Min ns, Min ns, Min ns, Min ns, Max MHz, Max
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Device Pin-to-Pin Output Parameter Guidelines

Table 74: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)
Symbol Description Device Speed Grade -3 -2 -1 Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, without MMCM/PLL. TICKOF Clock-capable clock input and OUTFF without MMCM/PLL (near clock region) XC7Z030 XC7Z045 5.38 5.27 5.92 5.78 6.62 6.48 ns ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 75: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, without MMCM/PLL. TICKOFFAR Clock-capable clock input and OUTFF without MMCM/PLL (far clock region) XC7Z030 XC7Z045 5.38 5.88 5.92 6.46 6.62 7.23 ns ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 76: Clock-Capable Clock Input to Output Delay With MMCM

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, with MMCM. TICKOFMMCMCC Clock-capable clock input and OUTFF with MMCM XC7Z030 XC7Z045 Notes:
1. 2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation.
0.91 0.97
0.91 0.97
0.91 0.97
ns ns
Table 77: Clock-Capable Clock Input to Output Delay With PLL

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, with PLL. TICKOFPLLCC Clock-capable clock input and OUTFF with PLL XC7Z030 XC7Z045 Notes:
1. 2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. PLL output jitter is already included in the timing calculation.
0.81 0.86
0.81 0.86
0.81 0.86
ns ns
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Table 78: Pin-to-Pin, Clock-to-Out using BUFIO

Symbol
TICKOFCS
Description
Clock-to-out of I/O clock for HR I/O banks Clock-to-out of I/O clock for HP I/O banks
Speed Grade -3
4.93 4.85
-2
5.52 5.44
-1
6.20 6.11
Units
ns ns
Device Pin-to-Pin Input Parameter Guidelines

Table 79: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1) TPSFD/ TPHFD Full delay (legacy delay or default delay) global clock input and IFF(2) without MMCM/PLL with ZHOLD_DELAY on HR I/O banks XC7Z030 XC7Z045 2.98/0.30 3.09/0.30 3.33/0.30 3.50/0.47 3.67/0.47 3.97/0.47 ns ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input flip-flop or latch A zero "0" hold time listing indicates no hold time or a negative hold time.
2. 3.
Table 80: Clock-Capable Clock Input Setup and Hold With MMCM
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1) TPSMMCMCC/ TPHMMCMCC Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input flip-flop or latch Use IBIS to determine any duty-cycle distortion incurred using various standards.
No delay clock-capable clock input and IFF(2) with MMCM
XC7Z030 XC7Z045
2.35/0.23 2.63/0.23 2.90/0.23 2.55/0.09 2.84/0.09 3.14/0.09
ns ns
2. 3.
Table 81: Clock-Capable Clock Input Setup and Hold With PLL
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1) TPSPLLCC/ TPHPLLCC Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input flip-flop or latch Use IBIS to determine any duty-cycle distortion incurred using various standards.
No delay clock-capable clock input and IFF(2) with PLL
XC7Z030 XC7Z045
2.72/0.34 3.02/0.34 3.30/0.34 2.91/0.20 3.24/0.20 3.53/0.20
ns ns
2. 3.
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Table 82: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Symbol
TPSCS/TPHCS
Description
Setup/hold of I/O clock for HR I/O banks Setup/hold of I/O clock for HP I/O banks
Units
ns ns
0.36/1.36 0.36/1.50 0.36/1.70 0.34/1.39 0.34/1.53 0.34/1.73
Table 83: Sample Window

Symbol
TSAMP TSAMP_BUFIO Notes:
1. This parameter indicates the total sampling error of the PL DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers edges of operation. These measurements include: - CLK0 MMCM jitter - MMCM accuracy (phase offset) - MMCM phase shift resolution These measurements do not include package or clock tree skew. This parameter indicates the total sampling error of the PL DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers edges of operation. These measurements do not include package or clock tree skew.
Description
Sampling error at receiver pins(1) Sampling error at receiver pins using BUFIO(2)
Speed Grade -3
0.51 0.30
-2
0.56 0.35
-1
0.61 0.40
Units
ns ns
2.
Additional Package Parameter Guidelines

The parameters in this section provide the necessary values for calculating timing budgets for PL clock transmitter and receiver data-valid windows. Table 84: Package Skew
Symbol
TPKGSKEW
Description
Package skew(1)
Device
XC7Z030
Package
FBG484 FBG676 FFG676
Value
Units
ps ps ps
XC7Z045
FBG676 FFG676 FFG900
159 191
ps ps ps
Notes:
1. 2. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time from pad to ball (7.0 ps per mm). Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
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GTX Transceiver Specifications

GTX Transceiver DC Input and Output Levels
Table 85 summarizes the DC specifications of the GTX transceivers in Zynq-7000 devices. Consult UG476: 7 Series FPGAs GTX/GTH Transceivers User Guide for further details. Table 85: GTX Transceiver DC Specifications
Symbol
DVPPOUT VCMOUTDC ROUT TOSKEW DVPPIN VIN VCMIN RIN CEXT Notes:
1. 2. The output swing and preemphasis levels are programmable using the attributes discussed in UG476: 7 Series FPGAs GTX/GTH Transceivers User Guide and can result in values lower than reported in this table. Other values can be used as appropriate to conform to specific protocols and standards.
DC Parameter
Conditions
Min
Typ
Max
1000
Units
mV mV
Differential peak-to-peak output Transmitter output swing is set to voltage (1) maximum setting DC common mode output voltage. Differential output resistance Transmitter output pair (TXP and TXN) intra-pair skew Differential peak-to-peak input voltage (external AC coupled) >10.3125 Gb/s 6.6 Gb/s to 10.3125 Gb/s 6.6 Gb/s Absolute input voltage Common mode input voltage Differential input resistance Recommended external AC coupling capacitor(2) DC coupled VMGTAVTT = 1.2V DC coupled VMGTAVTT = 1.2V Equation based
VMGTAVTT DVPPOUT/4 150 150 150 200 100 2 2/3 VMGTAVTT 100 100 12 1250 1250 2000 VMGTAVTT
ps mV mV mV mV mV nF
+V
P
Single-Ended Voltage
ds191_13_072412
N 0
Figure 13: Single-Ended Peak-to-Peak Voltage
+V
Differential Voltage
PN
ds191_14_072412
Figure 14: Differential Peak-to-Peak Voltage Table 86 summarizes the DC specifications of the clock input of the GTX transceiver. Consult UG476: 7 Series FPGAs GTX/GTH Transceivers User Guide for further details.
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Table 86: GTX Transceiver Clock DC Input Level Specification

Symbol
VIDIFF RIN CEXT
DC Parameter
Differential peak-to-peak input voltage Differential input resistance Required external AC coupling capacitor
Min
250
Typ
100 100
Max
2000
Units
mV nF
GTX Transceiver Switching Characteristics

Consult UG476: 7 Series FPGAs GTX/GTH Transceivers User Guide for further information. Table 87: GTX Transceiver Performance
Speed Grade Symbol Description Output Divider FF
FGTXMAX(2) FGTXMIN(2) Maximum GTX transceiver data rate Minimum GTX transceiver data rate 1 2 FGTXCRANGE CPLL line rate range 4 8 16 1 2 FGTXQRANGE1 QPLL line rate range 1 4 8 16 1 2 FGTXQRANGE2 QPLL line rate range 2(3) 4 8 16 FGCPLLRANGE GTX transceiver CPLL frequency range 9.8 12.5 5.938.0 5.936.6 12.5 0.500
-3
-2 Package Type FB
6.6 0.500
-1(1)
Units FB
6.6 0.500 Gb/s Gb/s Gb/s Gb/s Gb/s Gb/s Gb/s
FF
10.3125 0.500
FB
6.6 0.500
FF
6.6 0.500
3.26.6 1.63.3 0.81.65 0.50.825 N/A 5.938.0 5.936.6 5.936.6 2.9653.3 1.48251.65 0.741250.825 N/A N/A N/A N/A N/A N/A N/A 1.63.3 5.936.6 N/A
Gb/s Gb/s Gb/s Gb/s Gb/s Gb/s Gb/s Gb/s Gb/s Gb/s GHz GHz GHz
2.9654.0 1.48252.0 0.741251.0 N/A N/A
2.9654.0 1.48252.0 0.741251.0 N/A 9.8 10.3125
4.96.25 2.453.125 1.2251.5625 0.61250.78125 1.63.3 5.938.0 9.812.5
4.95.15625 2.452.578125 1.2251.2890625 0.61250.64453125 1.63.3 5.938.0 9.810.3125
FGQPLLRANGE1 GTX transceiver QPLL frequency range 1 FGQPLLRANGE2 GTX transceiver QPLL frequency range 2 Notes:
1. 2. 3.
The -1 speed grade requires a 4-byte internal data width for operation above 5.0 Gb/s. Data rates between 8.0 Gb/s and 9.8 Gb/s are not available. For QPLL line rate range 2, the maximum line rate with the divider N set to 66 is 10.3125Gb/s.
Table 88: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
FGTXDRPCLK
Description
GTXDRPCLK maximum frequency
Speed Grade -3
175
-2
175
-1
156.25
Units
MHz
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Table 89: GTX Transceiver Reference Clock Switching Characteristics

Symbol Description Conditions
-3 speed grade All other speed grades 20% 80% 80% 20% Transceiver PLL only
All Speed Grades Min

60 60 40
Typ
200 200 50
Max
700 670 60
Units
MHz MHz ps ps %
FGCLK TRCLK TFCLK TDCREF

Reference clock frequency range Reference clock rise time Reference clock fall time Reference clock duty cycle
TRCLK
80%
20%
TFCLK
d s 191_15_072412
Figure 15: Reference Clock Timing Parameters Table 90: GTX Transceiver PLL /Lock Time Adaptation
Symbol
TLOCK
Description
Initial PLL lock Clock recovery phase acquisition and adaptation time for decision feedback equalizer (DFE). Clock recovery phase acquisition and adaptation time for low-power mode (LPM) when the DFE is disabled.
Conditions
All Speed Grades Min
Typ
50,000
Max
1 37 x106
Units
ms UI
TDLOCK
After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input.
50,000
2.3 x106
UI
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Table 91: GTX Transceiver User Clock Switching Characteristics(1)(2)

Symbol
FTXOUT FRXOUT FTXIN
Description
TXOUTCLK maximum frequency RXOUTCLK maximum frequency TXUSRCLK maximum frequency
Conditions
Speed Grade (3)(4) -3

412.5 412.5
-2
412.5 412.5 412.5 322.5 412.5 322.5 412.5 322.5 161.5 412.5 322.5 161.5
-1
312.5 312.5 312.5 206.5 312.5 206.5 312.5 206.5 103.5 312.5 206.5 103.5
Units
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
16-bit data path 32-bit data path
412.5 391 412.5 391 412.5 391 195.5 412.5 391 195.5
FRXIN
RXUSRCLK maximum frequency
16-bit data path 32-bit data path 16-bit data path
FTXIN2
TXUSRCLK2 maximum frequency
32-bit data path 64-bit data path 16-bit data path
FRXIN2
RXUSRCLK2 maximum frequency
32-bit data path 64-bit data path
Notes:
1. 2. 3. 4. Clocking must be implemented as described in UG476: 7 Series FPGAs GTX/GTH Transceivers User Guide. These frequencies are not supported for all possible transceiver configurations. For speed grades -3 and -2, a 16-bit data path can only be used for speeds less than 6.6 Gb/s. For speed grade -1, a 16-bit data path can only be used for speeds less than 5.0 Gb/s.
Table 92: GTX Transceiver Transmitter Switching Characteristics

Symbol
FGTXTX TRTX TFTX TLLSKEW VTXOOBVDPP TTXOOBTRANSITION TJ12.5 DJ12.5 TJ11.18 DJ11.18 TJ10.3125 DJ10.3125 TJ9.953 DJ9.953 TJ9.8 DJ9.8 TJ8.0 DJ8.0 TJ6.6_QPLL DJ6.6_QPLL TX rise time TX fall time TX lane-to-lane skew(1) Electrical idle amplitude Electrical idle transition time Total Total Total Total Total jitter(2)(4) jitter(2)(4) jitter(2)(4) jitter(2)(4) jitter(2)(4) jitter(2)(4) jitter(2)(4) Deterministic jitter(2)(4) Deterministic 12.5 Gb/s 11.18 Gb/s 10.3125 Gb/s 9.953 Gb/s 9.8 Gb/s 8.0 Gb/s 6.6 Gb/s
Description
Serial data rate range
Condition
20%80% 80%20%
Min
0.500
Typ
40 40
Max
FGTXMAX 500 15 140 0.28 0.17 0.28 0.17 0.28 0.17 0.28 0.17 0.28 0.17 0.33 0.17 0.28 0.17
Units
Gb/s ps ps ps mV ns UI UI UI UI UI UI UI UI UI UI UI UI UI UI
Deterministic jitter(2)(4) Deterministic
Deterministic jitter(2)(4) Total jitter(2)(4) Deterministic Total jitter(2)(4) jitter(2)(4)
Deterministic jitter(2)(4)
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 92: GTX Transceiver Transmitter Switching Characteristics (Contd)
Symbol
TJ6.6_CPLL DJ6.6_CPLL TJ5.0 DJ5.0 TJ4.25 DJ4.25 TJ3.75 DJ3.75 TJ3.2 DJ3.2 TJ3.2L DJ3.2L TJ2.5 DJ2.5 TJ1.25 DJ1.25 TJ500 DJ500 Notes:
1. 2. 3. 4. 5. 6. 7. 8. Using same REFCLK input with TX phase alignment enabled for up to 12 consecutive transmitters (three fully populated GTX Quads). Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. All jitter values are based on a bit-error ratio of 1e-12. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2. CPLL frequency at 1.6 GHz and TXOUT_DIV = 1. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
Description
Total jitter(3)(4) jitter(3)(4) jitter(3)(4) jitter(3)(4) Deterministic Deterministic Total Deterministic
Condition
6.6 Gb/s 5.0 Gb/s 4.25 Gb/s 3.75 Gb/s 3.20 Gb/s(5) 3.20 Gb/s(6) 2.5 Gb/s(7) 1.25 Gb/s(8) 500 Mb/s
Min

Typ

Max
0.30 0.15 0.33 0.15 0.33 0.14 0.34 0.16 0.2 0.1 0.35 0.16 0.20 0.08 0.15 0.06 0.1 0.03
Units
UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI
Total jitter(3)(4) jitter(3)(4)
Total jitter(3)(4) Deterministic jitter(3)(4) Total jitter(3)(4) jitter(3)(4) Deterministic
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Table 93: GTX Transceiver Receiver Switching Characteristics

Symbol
FGTXRX TRXELECIDLE RXOOBVDPP RXSST RXRL Serial data rate
Description
RX oversampler not enabled
Min
0.500 60 5000
Typ
10
Max
FGTXMAX 150 0 512 1250 700 200
Units
Gb/s ns mV ppm UI ppm ppm ppm
Time for RXELECIDLE to respond to loss or restoration of data OOB detect threshold peak-to-peak Receiver spread-spectrum tracking(1) Run length (CID) Data/REFCLK PPM offset tolerance Bit rates 6.6 Gb/s Bit rates > 6.6 Gb/s and 8.0 Gb/s Bit rates > 8.0 Gb/s Modulated @ 33 KHz
1250 700 200
RXPPMTOL
SJ Jitter
Tolerance(2)
Sinusoidal jitter (QPLL)(3) Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter Sinusoidal jitter (QPLL)(3) (QPLL)(3) (QPLL)(3) (QPLL)(3) (QPLL)(3) (QPLL)(3) (CPLL)(3) (CPLL)(3) (CPLL)(3) (CPLL)(3) (CPLL)(3) (CPLL)(3) (CPLL)(3) (CPLL)(3) (CPLL)(3) 12.5 Gb/s 11.18 Gb/s 10.32 Gb/s 9.95 Gb/s 9.8 Gb/s 8.0 Gb/s 6.6 Gb/s 6.6 Gb/s 5.0 Gb/s 4.25 Gb/s 3.75 Gb/s 3.2 3.2 2.5 Gb/s(4) Gb/s(5) Gb/s(6) Gb/s(7) 0.3 0.3 0.3 0.3 0.3 0.44 0.48 0.44 0.44 0.44 0.44 0.45 0.45 0.5 0.5 0.4 UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI
JT_SJ12.5 JT_SJ11.18 JT_SJ10.32 JT_SJ9.95 JT_SJ9.8 JT_SJ8.0 JT_SJ6.6_QPLL JT_SJ6.6_CPLL JT_SJ5.0 JT_SJ4.25 JT_SJ3.75 JT_SJ3.2 JT_SJ3.2L JT_SJ2.5 JT_SJ1.25 JT_SJ500
1.25
500 Mb/s
SJ Jitter Tolerance with Stressed

JT_TJSE3.2 JT_SJSE3.2 Notes:
1. 2. 3. 4. 5. 6. 7. 8.
Eye(2)
3.2 Gb/s 6.6 Gb/s 3.2 Gb/s 6.6 Gb/s 0.70 0.70 0.1 0.1 UI UI UI UI
Total jitter with stressed eye(8) Sinusoidal jitter with stressed eye(8)
Using RXOUT_DIV = 1, 2, and 4. All jitter values are based on a bit error ratio of 1e12. The frequency of the injected sinusoidal jitter is 10 MHz. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2. CPLL frequency at 1.6 GHz and RXOUT_DIV = 1. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4. Composite jitter with RX and LPM or DFE mode.
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GTX Transceiver Protocol Jitter Characteristics

For Table 94 through Table 99, the UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide contains recommended settings for optimal usage of protocol specific characteristics. Table 94: Gigabit Ethernet Protocol Characteristics
Description Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ) 1250 0.24 UI
Line Rate (Mb/s)
Min
Max
Units
Gigabit Ethernet Receiver High Frequency Jitter Tolerance

Total receiver jitter tolerance 1250 0.749 UI
Table 95: XAUI Protocol Characteristics

Description XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ) 3125 0.35 UI
Line Rate (Mb/s)
Min
Max
Units
XAUI Receiver High Frequency Jitter Tolerance

Total receiver jitter tolerance 3125 0.65 UI
Table 96: PCI Express Protocol Characteristics(1)

Standard PCI Express Transmitter Jitter Generation
PCI Express Gen 1 PCI Express Gen 2 PCI Express Gen 3(2) Total transmitter jitter Total transmitter jitter Total transmitter jitter uncorrelated Deterministic transmitter jitter uncorrelated 2500 5000 8000 0.25 0.25 31.25 12 UI UI ps ps
Description
Line Rate (Mb/s)
Min
Max
Units
PCI Express Receiver High Frequency Jitter Tolerance

PCI Express Gen 1 PCI Express Gen 2(3) Total receiver jitter tolerance Receiver inherent timing error Receiver inherent deterministic timing error 0.03 MHz1.0 MHz PCI Express Gen 3(2) Receiver sinusoidal jitter tolerance 1.0 MHz10 MHz 10 MHz100 MHz Notes:
1. 2. 3. 4. Tested per card electromechanical (CEM) methodology. PCI-SIG 3.0 certification and compliance test boards are currently not available. Using common REFCLK. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20 dB/decade.
2500 5000
0.65 0.40 0.30 1.00
UI UI UI UI UI UI
8000
Note 4 0.10
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Table 97: CEI-6G and CEI-11G Protocol Characteristics

Description Line Rate (Mb/s) Interface Min Max Units CEI-6G Transmitter Jitter Generation
Total transmitter jitter(1) 49766375 CEI-6G-SR CEI-6G-LR 0.3 0.3 UI UI
CEI-6G Receiver High Frequency Jitter Tolerance

Total receiver jitter tolerance(1) 49766375 CEI-6G-SR CEI-6G-LR 0.6 0.95 UI UI
CEI-11G Transmitter Jitter Generation

Total transmitter jitter(2) 995011100 CEI-11G-SR CEI-11G-LR/MR 0.3 0.3 UI UI
CEI-11G Receiver High Frequency Jitter Tolerance

CEI-11G-SR Total receiver jitter tolerance(2) 995011100 CEI-11G-MR CEI-11G-LR Notes:
1. 2. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock. Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock.
0.65 0.65 0.825
UI UI UI
Table 98: SFP+ Protocol Characteristics

Description SFP+ Transmitter Jitter Generation
9830.40(1) 9953.00 Total transmitter jitter 10312.50 10518.75 11100.00 0.28 UI
Line Rate (Mb/s)
Min
Max
Units
SFP+ Receiver Frequency Jitter Tolerance

9830.40(1) 9953.00 Total receiver jitter tolerance 10312.50 10518.75 11100.00 Notes:
1. Line rated used for CPRI over SFP+ applications.
0.7
UI
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Table 99: CPRI Protocol Characteristics

Description CPRI Transmitter Jitter Generation
614.4 1228.8 2457.6 Total transmitter jitter 3072.0 4915.2 6144.0 9830.4 0.35 0.35 0.35 0.35 0.3 0.3 Note 1 UI UI UI UI UI UI UI
Line Rate (Mb/s)
Min
Max
Units
CPRI Receiver Frequency Jitter Tolerance

614.4 1228.8 2457.6 Total receiver jitter tolerance 3072.0 4915.2 6144.0 9830.4 Notes:
1. Tested per SFP+ specification, see Table 98.
0.65 0.65 0.65 0.65 0.95 0.95 Note 1
UI UI UI UI UI UI UI
Integrated Interface Block for PCI Express Designs Switching Characteristics

More information and documentation on solutions for PCI Express designs can be found at: http://www.xilinx.com/technology/protocols/pciexpress.htm Table 100: Maximum Performance for PCI Express Designs
Symbol
FPIPECLK FUSERCLK FUSERCLK2 FDRPCLK
Description
Pipe clock maximum frequency User clock maximum frequency User clock 2 maximum frequency DRP clock maximum frequency
Speed Grade -3
250 500 250 250
-2
250 500 250 250
-1
250 250 250 250
Units
MHz MHz MHz MHz
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XADC Specifications
Table 101: XADC Specifications
Parameter
ADC Accuracy(1) Resolution Integral Nonlinearity(2) INL DNL No missing codes, guaranteed monotonic Offset calibration enabled Gain calibration disabled Offset calibration enabled Gain calibration disabled Ratio(2) 12 0.1 SNR FSAMPLE = 500KS/s, FIN = 20KHz External 1.25V reference On-chip reference Total Harmonic Distortion(2) THD FSAMPLE = 500KS/s, FIN = 20KHz 60 70 3 2 1 4 0.4 4 0.2 1 2 Bits LSBs LSBs LSBs % LSBs % MS/s dB LSBs LSBs dB
Symbol
Comments/Conditions
Min
Typ
Max
Units
VCCADC = 1.8V 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, Tj = 40C to 100C, Typical values at Tj=+40C
Differential Nonlinearity Offset Error Gain Error Offset Matching Gain Matching Sample Rate Signal to Noise
RMS Code Noise
ADC Accuracy at Extended Temperatures (-55C to 125C)

Resolution Integral Nonlinearity(2) Inputs(3) Unipolar operation Bipolar operation Unipolar common mode range (FS input) Bipolar common mode range (FS input) Maximum External Channel Input Ranges Adjacent channels set within these ranges should not corrupt measurements on adjacent channels 0 0.5 0 +0.5 0.1 1 +0.5 +0.5 +0.6 VCCADC V V V V V INL DNL No missing codes, guaranteed monotonic 10 1 1 Bits LSB (at 10 bits)
Differential Nonlinearity Analog
ADC Input Ranges
Auxiliary Channel Full Resolution Bandwidth On-Chip Sensors Temperature Sensor Error
FRBW
250
KHz
Tj = 40C to 100C. Tj = 55C to +125C Measurement range of VCCAUX 1.8V 5% Tj = 40C to +100C Measurement range of VCCAUX 1.8V 5% Tj = 55C to +125C
4 6 1 2
C C % %
Supply Sensor Error
Conversion Rate(4) Conversion Time - Continuous Conversion Time - Event DRP Clock Frequency ADC Clock Frequency DCLK Duty Cycle tCONV tCONV DCLK ADCCLK Number of ADCCLK cycles Number of CLK cycles DRP clock frequency Derived from DCLK 26 8 1 40 32 21 250 26 60 Cycles Cycles MHz MHz %
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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics Table 101: XADC Specifications (Contd)
Parameter
XADC Reference(5) External Reference On-Chip Reference Notes:
1. 2. 3. 4. 5. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature is enabled. Only specified for new BitGen option XADCEnhancedLinearity = ON. See the ADC chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description. See the Timing chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by 4% is permitted. On-chip reference variation is 1%.
Symbol
Comments/Conditions
Min
Typ
Max
Units
VREFP
Externally supplied reference voltage Ground VREFP pin to AGND, Tj = 40C to 100C
1.20 1.2375
1.25 1.25
1.30 1.2625
V V
Configuration Switching Characteristics

Table 102: Configuration Switching Characteristics
Symbol Power-up Timing Characteristics
TPOR TTAPTCK/TTCKTAP TTCKTDO FTCK Power-on reset 50 50 50 ms, Max
Description
Units
Boundary-Scan Port Timing Specifications

TMS and TDI setup/hold TCK falling edge to TDO output TCK frequency 3.0/2.0 7.0 66 3.0/2.0 7.0 66 3.0/2.0 7.0 66 ns, Min ns, Max MHz, Max
eFUSE Programming Conditions

Table 103 lists the programming conditions specifically for eFUSE. For more information, see UG470: 7 Series FPGA Configuration User Guide. Table 103: eFUSE Programming Conditions(1)
Symbol
IFS tj Notes:
1. The Zynq-7000 device must not be configured during eFUSE programming.
Description
VCCAUX supply current Temperature range
Min
15
Typ

Max
115 125
Units
mA C
www.xilinx.com 66
Revision History
The following table shows the revision history for this document:
Date
08/23/12 08/31/12
Version
1.0 1.1 Initial Xilinx release.
Description
Updated Tj and added Note 2 to Table 2. Updated RIN_TERM in Table 3. Updated standards in Table 9. Revised PS Performance Characteristics section introduction. Updated values in Table 17. Added Note 2 to Table 25. Added Note 3 to Table 27. Revised FMSPICLK in Table 31.
Notice of Disclaimer
The information disclosed to you hereunder (the Materials) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps. AUTOMOTIVE APPLICATIONS DISCLAIMER XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAILSAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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Ds191 XC7Z030 XC7Z045 Data Sheet

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Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045): DC and AC Switching Characteristics

DS191 (v1.1) August 31, 2012 Advance Product Specification

Programmable Logic (PL)

Key memory battery backup supply

DS191 (v1.1) August 31, 2012 Advance Product Specification

150 +220 +260 +125

Table 2: Recommended Operating Conditions (1)

0.95 1.71 1.71 1.14 1.71 0.20 0.20

1.00 1.80 1.80

1.05 1.89 1.89 1.89

3.465 VCCO + 0.20 2.625

DS191 (v1.1) August 31, 2012 Advance Product Specification

VMGTAVTT(9) VMGTVCCAUX(9) VMGTAVTTRCAL(9)

DS191 (v1.1) August 31, 2012 Advance Product Specification

Table 3: DC Characteristics Over Recommended Operating Conditions

IRPD(3) ICCADC IBATT

Temperature diode ideality factor Temperature diode series resistance

DS191 (v1.1) August 31, 2012 Advance Product Specification

DS191 (v1.1) August 31, 2012 Advance Product Specification

Table 6: Typical Quiescent Supply Current

ICCPINTQ ICCPAUXQ ICCDDRQ ICCINTQ

DS191 (v1.1) August 31, 2012 Advance Product Specification

PS Power-On/Off Power Supply Requirements

PL Power-On/Off Power Supply Sequencing

PSPL Power Sequencing

DS191 (v1.1) August 31, 2012 Advance Product Specification

Power Supply and PS Reset Requirements

Table 8: Power Supply Ramp Time

0.2 0.2 0.2

DS191 (v1.1) August 31, 2012 Advance Product Specification

DC Input and Output Levels

VIL V, Min V, Max

VOL V, Max V, Max

LVCMOS18(2) 0.300 LVCMOS25(3) 0.300 LVCMOS33(3) 0.300 HSTL_I_18 LVTTL

VCCO_MIO + 0.300 VCCO_MIO + 0.300 3.450

DDR SSTL18_I DDR SSTL15 DDR HSUL_12 Notes:

DS191 (v1.1) August 31, 2012 Advance Product Specification

Table 10: SelectIO DC Input and Output Levels(1)(2)

VIH V, Max V, Min

DS191 (v1.1) August 31, 2012 Advance Product Specification

Table 11: Differential SelectIO DC Input and Output Levels

VICM(1) V, Min V, Typ

V, Min V, Typ V, Max

V, Min V, Typ V, Max

MINI_LVDS_25 0.300 PPDS_25 RSDS_25 TMDS_33 Notes:

0.200 0.300 2.700

1.200 VCCO0.405 VCCO0.300 VCCO0.190 0.400

Table 12: Complementary Differential SelectIO DC Input and Output Levels

IOL mA, Max

IOH mA, Min

DS191 (v1.1) August 31, 2012 Advance Product Specification

LVDS DC Specifications (LVDS_25)

LVDS DC Specifications (LVDS)

DS191 (v1.1) August 31, 2012 Advance Product Specification

Testing of AC Switching Characteristics

Speed Grade Designations

Speed Grade Designations Advance

DS191 (v1.1) August 31, 2012 Advance Product Specification

Production Silicon and ISE Software Status

Speed Grade Designations -3 -2 -1

DS191 (v1.1) August 31, 2012 Advance Product Specification

Table 18: PS DDR Clock Domains Performance

Table 20: PS PLL Switching Characteristics

DS191 (v1.1) August 31, 2012 Advance Product Specification