Department of Electronics and Communication Engineering Lesson Plan

YEAR& SEC : III A SUBJECT CODE : EC2354 SUBJECT: VLSI Design

AIM To introduce the technology, design concepts and testing of Very Large Scale Integrated Circuits (VLSI). OBJECTIVE To learn the basic CMOS circuits. To learn the CMOS process technology. To learn techniques of chip design using programmable devices. To learn the concepts of designing VLSI subsystems. To learn the concepts of modeling a digital system using Hardware Description Language. To learn the various testing techniques at chip level and system level UNIT I CMOS TECHNOLOGY 9 A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal IV effects, DC transfer characteristics - CMOS technologies, Layout design Rules, CMOS process enhancements, Technology related CAD issues, Manufacturing issues UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION 9 Delay estimation, Logical effort and Transistor sizing, Power dissipation, Interconnect, Design margin, Reliability, Scaling- SPICE tutorial, Device models, Device characterization, Circuit characterization, Interconnect simulation UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN 9 Circuit families Low power logic design comparison of circuit families Sequencing static circuits, circuit design of latches and flip flops, Static sequencing element methodology- sequencing dynamic circuits synchronizers UNIT IV CMOS TESTING 9 Need for testing- Testers, Text fixtures and test programs- Logic verification- Silicon debug principles- Manufacturing test Design for testability Boundary scan UNIT V SPECIFICATION USING VERILOG HDL 9 Basic concepts- identifiers- gate primitives, gate delays, operators, timing controls, procedural assignments conditional statements, Data flow and RTL, structural gate level switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches, Structural gate level description of decoder, equality detector, comparator, priority encoder, half adder, full adder, Ripple carry adder, D latch and D flip flop. TOTAL= 45 PERIODS TEXTBOOKS: 1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 2005 2. Uyemura J.P: Introduction to VLSI circuits and systems, Wiley 2002. REFERENCES: 1 D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 2003 2 Wayne Wolf, Modern VLSI design, Pearson Education, 2003 3 M.J.S.Smith: Application specific integrated circuits, Pearson Education, 1997 4 J.Bhasker: Verilog HDL primer, BS publication,2001 5 Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003

S.No Topics Covered A brief History-MOS transistor 1 Enhancement mode & Depletion mode Ideal I-V characteristics, C-V characteristics, Non 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 34
ideal IV effects, DC transfer characteristics

Unit I I I I I I I I II II II II II II II II II III III III III III III VI VI VI VI VI VI V V V V V V

Reference Book T1 CHAPTER 1 T1 CHAPTER 2 T1 CHAPTER 2 T1 CHAPTER 3 R2 - CHAPTER 1 T1 CHAPTER 3 T1 CHAPTER 3 T1 CHAPTER 3 T1 CHAPTER 3 T1 CHAPTER 4 T1 CHAPTER 4 T1 CHAPTER 4 T1 CHAPTER 4 T1 CHAPTER 4,5 T1 CHAPTER 5 T1 CHAPTER 5 T1 CHAPTER 5 T1 CHAPTER 5 T1 CHAPTER 6 T1 CHAPTER 6 T1 CHAPTER 7 T1 CHAPTER 7 T1 CHAPTER 7 T1 CHAPTER 7 T1 CHAPTER 12 T1 CHAPTER 12 T1 CHAPTER 12 T1 CHAPTER 12 T1 CHAPTER 12 T1 CHAPTER 12 R4 CHAPTER 5 R4 - CHAPTER 7 R4 - CHAPTER -6 R4 - CHAPTER 2 R4 CHAPTER 7 R4 CHAPTER 4,5,6

Page no 1,5 42 60 73 83 91 105 107 111 120 129 145 160,179 190 193 205 210 216 243 251 265 275 284,289 531 537 541 542 544 548,559 105 166,171 131 56 161 59,117, 119

CMOS Technology : n well, P well, Twin tub and SOI Process. Layout design Rules - Lamda based rules
CMOS process enhancements, Technology related CAD issues Manufacturing issues Delay estimation Logical effort and Transistor sizing Power dissipation, interconnect, Design margin, Reliability Scaling- SPICE tutorial Device models Device characterization Circuit characterization Interconnect simulation Circuit families Low power logic design comparison of circuit families Sequencing static circuits, circuit design of latches and flip flops Static sequencing element methodology sequencing dynamic circuits synchronizers Need for testing- Testers Text fixtures and test programs Logic verification Silicon debug principlesManufacturing test Design for testability Boundary scan Basic concepts- identifiers- gate primitives, gate delays operators, timing controls, procedural assignments conditional statements Data flow and RTL, structural gate level switch level modeling Design hierarchies Behavioral and RTL modeling Test benches, Structural gate level description of decoder, equality detector, comparator, priority encoder, half adder, full adder, Ripple carry adder, D latch and D flip flop.

Signature of Staff Members

Signature of the H.O.D