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8. Semiconductor Memories
Wai Tung Ng Associate Professor
University of Toronto Electrical & Computer Engineering Toronto Ontario Canada M5S 3G4
Tel: e-mail:
(416) 978-6249 ngwt@vrg.utoronto.ca 2001 University of Toronto 7-1

Outline
Semiconductor Memories
SRAM DRAM ROM

Why EEPROM Conventional Flash E2PROM cell Structures Memory Circuits Fault Models for Semiconductor Memories Nonvolatile Memory Testing

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8.1 Semiconductor Memories Memory circuits provide the means of storing information (data) on a temporary or permanent basis and for future recalls. Magnetic memory generally is capable of storing large amount of data at very low cost, but the access time (the time it takes to locate and then read or write) is usually very long. Semiconductor memories use electrical signals to identify memory location and its content. The access time in several orders of magnitude faster that magnetic memory.
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Semiconductor Memories (contd) MOS and bipolar technologies can be used to implement various types of semiconductor memories. Semiconductor memories are usually classified into two major types: volatile, or non-volatile. Volatile memories (SRAM, DRAM) loose their data once the power supply is turned off. Non-volatile memories (ROM, EPROM) on the other hand can retain their data even after power is removed.

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Static RAM (SRAM) Random Access Memory (RAM) is a readable and write-able volatile memory. The term random access means that the user can access any location of the entire memory and in any order. RAM is further divided into static RAM (SRAM) and dynamic RAM (DRAM). Static RAM is a simple latch circuit (flip-flop) that remembers its state until it is toggled.

Static RAM (contd) The simplest SRAM would be a simple data latch with pass transistors for selection and isolation. The actual implementation is usually carried out by the 6-transistor cell.

Word Line

6-transistor SRAM cell Bit Line Bit Line

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Internal organization of a 4 64 SRAM array

A3

Input Data Buffer

A2

A1

A0 Write Enable Word 0

Dynamic RAM (DRAM) DRAMs are fabricated using MOS technology and are noted for their high capacity, low power requirement, and moderate operating speed (when compared to SRAM). DRAMs make use of MOS capacitors to store the data as electronic charges. The capacitors can be switched in and out of the bit Word line lines via a pass transistor. The storage capacitor will loose its charge over time. Therefore, DRAMs must be refreshed in a regular basis. C Bit line

SRAM Array

Word 1 A1 A2 A3 A4 A5 6-bit address decoder A0

Word 2

4 64 SRAM Array

Output Data Buffers

Sense Amplifiers B3 B2 B1 B0

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Dynamic RAM (contd) The read operation for DRAM is a destructive process. Therefore, extra peripheral circuits must be used to rewrite the DRAM cells as soon as it is read. These operations are incorporated as part of the DRAM chip and are transparent to the users. The memory organization can be similar to the SRAM array. However, the memory size for DRAMs is usually much larger. Currently DRAM in 1G-bit size are available while SRAM sizes of under a 1M-bit are more common.

Dynamic RAM (contd) The most important difference of the DRAM fabrication process from other technology is the storage capacitor. The single-transistor DRAM cell requires a capacitor that can store sufficient charge to allow the cell state to state true between refresh cycles. The most significant development in the DRAM devices has been the advance in the capacitor design. The DRAM capacitors have been improved in two ways: increasing the surface area and increasing the capacitor dielectric constant. C = i A Tox For a minimum Tox, the remaining adjustable parameters are i and A.
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Trenched DRAM Cell One area of progress in making a capacitor with a larger surface area is to form the capacitor in a trench. This technique make use of a deep trench (> 7m into the silicon). It has the advantage of allowing the transistors to be formed nearly Word Line planar on the Bit Line Strap surface with the trench extending SiO SiO n+ n+ below the device p-well active area.
2 2

Trenched DRAM Cell (copy) The effect of the large surface area and the ability to thin the gate dielectric by improving the reliability of the thin oxides has resulted in a DRAM that can store more charge in smaller top surface area.

n-substrate
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Trench Capacitor
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Stacked DRAM Cell Another area of tremendous progress in DRAM technology goes in the other direction and forms the capacitors in geometries that extend above the silicon to create a large capacitor area. The large surface areas can be created using a large planar capacitor shaped like a dome or a crown. These structures also take advantage of higher-dielectricconstant materials for the inter-level dielectric for the capacitors Ta2O5 (Ba, Sr)TiO3, etc.

Stacked DRAM Cell (contd)

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Trench Cell vs. Stacked Cell In the trench technology, the cell process is completed before the gate oxidation. Therefore there is no thermal process due to cell capacitor formation after the MOSFET formation. Another advantage in the trench cell is that there is no height difference between cell array region and peripheral circuit region. In the stacked cell, the height difference require high aspect ratio contact holes and difficulty in the planarization process after the cell formation. The MOSFET formation steps are followed by the stacked capacitor formation steps.

Trench Cell vs. Stacked Cell (contd) These include high temperature processing steps such as storage node insulator (SiO2/SiN) formation, SiN deposition for the self-aligned contact formation, etc. Salicide (Self Aligned siLICIDE) process for the source and drain of the MOSFETs should be carefully designed to endure the high temperature process steps. For applications requiring Embedded DRAM, trenched cell is more attractive because the DRAM cells are formed before the MOSFETs and because there is little height difference between the cell array and other regions on the chip.

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Read Only Memory (ROM) Certain applications may require the memory to hold data that are either permanent or will not be changed frequently. In this case, nonvolatile memory is the candidate. As the name implies, Read D 0 Only Memory (ROM) has no A D 1 provision to write or update 0 A D its memory contents. 1 2 The programming is usually D 3 ROM done during the manufacturD 4 ing process or by a burning A D procedure prior to field use. n-1 5
A

Read Only Memory (contd) ROMs can be considered as lookup tables where an address code input will produce a certain data at the output. The internal organization of ROM chips are similar to the SRAM and DRAM except that no input data buffers are necessary. ROMs can programmed by photomasks that determine the connections in an array.

D D

6 7

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Read Only Memory (contd) Masked ROM

Row 1

Read Only Memory (contd)

VDD

A0 A1

Row 2

VDD

1 of 4 address decoder

Row 3

VDD

missing connection

Row 4

VDD

Address A0 A1 0 0 1 1 0 1 0 1 1 1 1 0

Data D0 D1 D2 D3 0 0 1 1 1 0 1 1 0 1 0 1 D3 D2 D1 D0

One obvious disadvantage of the mask ROM is the fact that a new photomask must be prepared if the stored data is to be changed. This will also be accompanied by a sizable turn-around time when manufacturing the new ROMs. An alternate method of implementing the ROM is with a programmable technology such as fuse or anti-fuse. In this case, the ROM becomes a programmable parts, hence the name PROM. One advantage of the PROM is the fact that all ROMs, regardless of data content can be manufactured using the same set of photomask and fabrication procedures.

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Read Only Memory (contd) However, a one-time-only programming procedure must be applied prior to field use. After the PROM is programmed, its contents cannot be changed anymore.

8.2

Why EEPROMs?

Field programmable capability to wireless portable telecommunication equipment

True 5V or lower operation Compatible with CMOS/BiCMOS processes High operation speeds and high density Key to embedded systems Solid-state nonvolatile memories Multi-level Encoding

Word line

VDD

Fuse

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8.3

Conventional Flash E2PROM cell Structures

Flash E2PROM Cell Operations

VG = 12V VD 6 to 8V IDS n+
Electron Flow

Similar to an ordinary MOSFET except for an extra gate buried in the silicon dioxide
Charges are stored in the floating gate to alter the threshold voltage of the E2PROM cell Simple construction and fabrication steps Very high packing density Flash E2PROM and E2PROMs share the same technology
Control Gate Floating Gate

VS 5V

VG = -12V
e- e- e-

open n+

n+ p-type substrate

n+
FN Tunneling

p-type substrate Erasing

Source

Gate

Drain Programming

n+ p-type substrate

n+

For programming, hot electrons are created by the large drain bias current. These electron tunnels through the thin gate oxide and become trapped in the floating gate.
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Flash E2PROM Cell Operations For erasing, the stored electrons are removed by Frowler Nordheim (FN) tunneling from the floating gate to the substrate and the source.

Limitations of Existing Flash E2PROM Cells Most require high drain bias voltage (VD > 5V) to generate hot electrons for programming. Not directly scalable to shorter channel length. Not suitable for low voltage applications. Require high drain current (IDS @ 1mA) during programming. Require large charge pump circuits and limits the number of cells that can be programmed at once. Suffers from slow programming speed (a few s). Not suitable to replace RAM and electronic hard drives.

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Limitations of Existing Flash E2PROM Cells Most cells suffer from hole trapping in the thin gate oxide during erasing. Reduction in VTH window after several cycles of erase and programming.

Experimental Results
Programming Time
12V

Threshold Voltage (V)

floating

3.3V V T Programmed

V T Erased L = 0.8m

Time (s)
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Experimental Results (contd)

Erase Time

Experimental Results (contd)

Read Current for Different Sense Area
Drain to Source Current (mA)
3.3V

Threshold Voltage (V)

Wp+ = 25% of W
VS W/L = 6m / 0.8m 0V

-12V

VT Programmed

3.3V

floating VT Erased

Wp+ = 50% of W

Wp+ = 75% of W

L = 0.8m

Time (s)
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Source Voltage (V)

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Experimental Results (contd)

Drain Disturb Characteristics

Experimental Results (contd)

Gate Disturb Characteristics
Programmed Cell

Threshold Voltage (V)

0V

Threshold Voltage (V)

Programmed Cell

12V

floating

3.3V

0V

0V

Erased Cell

Erased Cell

Time (s)
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Experimental Results (contd)

Soft Write Characteristics
10 Years

8.4 Memory Circuits Semiconductor memories are comprised of a main storage array surrounded by peripheral circuits for read and write operations. These peripheral circuits includes row and column address decoders, data buffers/registers, sense amplifiers, and charge pumps circuits. The decoders and buffer/registers are basically digital circuits and can be implemented using conventional VLSI design methodology. The sense amplifier is basically a high gain circuit that is used to differentiate the stored information with a reference voltage.

Time (s)

3.3V

1V

0V

Erased Cell

1/VS (V-1)
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Memory Circuits (contd) This is especially critical if the storage element is a DRAM cell. Most memory arrays require separate high and low voltage supply to operate. In order to eliminate the need for multiple external power supplies, more memory chips have built-in charge pump circuits to generate multiple voltage levels from a single supply (usually 5V or 3.3V).

Sense Amplifiers One of the most difficult tasks in DRAM design is the dynamic sense amplifier. In a high density DRAM, the intrinsic differential voltage across the sense amplifier can be in the order of 10s of mV. The sense amplifier must detect and amplify this small signal with reasonable speed. On the other hand, since sense amplifiers are located between bit-lines, the available layout area is also limited, making the design particularly challenging.

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Sense Amplifiers (contd) Before the chip is selected, both nodes 1 and 2 have been pre-charged to VDD VTH by R through M3 and M4. As 1 goes high, exactly one word-line on each side of the latch rises. VDD
M3 Bitline CB 1 M1 M0
R

Sense Amplifiers (contd) Charges stored in the cells immediately redistribute along the bit-lines. It take a short but finite amount of time for the potentials on the bit-lines to settle. By the time 2 goes high to set the latch, v1(t) and v2(t) should have reached distinguishable values.

M4 2 M2
2 R

Reference Cell CB

DRAM Cell
1

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8.5

Fault Models for Semiconductor Memories

Failure Probability wear-out infant failure mortality

Fault Models (contd) Fault models allow the cost-effective development of test stimuli that will identify the failed chips, and if possible diagnose the failure mode. The fault model can be based upon different levels of abstraction: behavioral model, functional model, logical model, electrical model, and geometrical model.
The behavioral model is totally based on the system specification and is the highest level of abstraction. The functional model is based upon functional specification of the system which require certain assumptions to be made about the internal structure of the system.
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Memory device failures are usually represented by a bathtub curve.

These failures are useful life usually caused by design errors, materials Time and process defects, operational environment extremes, and aging effects. To analysis the fault memory circuit behavior and to develop techniques for failure detection, fault models are commonly used.
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Fault Models (contd)

The logical model has the properties similar to the electrical model which can allow faults to be detected and localized at the gate level. The electrical model is based upon both the functional specification of the system and complete knowledge of the internal structure at the electrical level. The geometrical model assumes complete knowledge of the chip layout.

Fault Models (contd) Logical fault modeling allows the test approach to become technology (TTL, NMOS, CMOS) independent, and hence more generally applicable. The parametric faults include excessive leakage currents, unacceptable input and output voltage levels, inadequate drive and fan-out performance, low noise margins, and low data retention time. Functional faults are based on the various fault models such as stuck-at and transition faults, bridging faults, coupling faults, and pattern sensitive faults.

Physical examination of the chip for the location of actual faults is often impossible, and hence tests must be used which are based on the logical comparison with the known good units.
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Fault Models (contd) Some of the faults that can occur in a memory chip are:
Cell stuck Read/write line stuck Chip select line stuck Data line stuck or open Short and/or cross-talk between two data lines Address line stuck or open Short between address lines Wrong access or multiple access Pattern-sensitive interaction between cells.
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Fault Models (contd) Since a memory chip is designed to store any arbitrary data pattern in its cells, ideally the functioning of each cell should be verified for all possible data patterns. However, for large memory cell arrays, this can become very time consuming, and in practice, many of these faults are unlikely to occur. Therefore a reduced functional fault model sets can be used.

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Electrical Testing Electrical testing for memories consists of DC and AC parametric tests and functional tests. DC and AC parametric tests are used for detecting faults in the external behavior of the memory devices, e.g. I/O threshold, I/O current levels, quiescent and dynamic power supply currents, propagation delays, and access times. These are often characterization tests which usually consist of a repetitive sequence of measurements to locate the operating limits of a device.

Electrical Testing (contd) They can also be production tests to determine whether the device meet their specifications. This can be done as a out-going (manufacturer) production test or an in-coming (user) inspection. The production tests can be the GO/NO GO testing to make pass/fail decisions, whereas user-detailed testing may consist of data read and record on all the DC and AC parametric and functional testing. DC and AC Parametric Testing Automated test equipment (ATE) is used to carry output the measurements.
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Electrical Testing (contd) DC electrical characteristics include quiescent and operating supply currents, output voltages low and high, I/O pin leakage currents, data retention voltage and current, input voltages low and high, etc. AC performance characteristics are measured for both the read and write cycles. The measurements include read cycle time, address access time, chip select and chip enable times, write cycle time, address setup to end of write cycle time, write pulse width, etc.

Functional Testing Algorithms There is no single pattern that could exercise a RAM thoroughly enough to detect all the failure modes. There are however, some test patterns that are developed based on some common failure modes:
Address Decoder Malfunction: In this failure mode, an open address decode line internal to the device or a defective decoder inhibits proper addressing of portions of the memory array. Multiple Write Errors: the data bits are written into a cell other than the one addressed because of capacitive coupling between the cells.

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Functional Testing Algorithms (contd)

Pattern Sensitivity: The cell storage characteristics (or response) vary with the test pattern and the data pattern stored in the surrounding cells or the rest of the memory array. Refresh Sensitivity: In DRAMS, the data can be lost during the specific minimum period between the refresh cycles due to excessive voltage or current leakage and other faults in rewriting circuitry. Slow Access Time: An above-normal capacitive load on the output driver circuit causes excessive time to sink and source current, thereby increase access time.

Functional Testing Algorithms (contd)

Slow Write Recovery: memory access time increases when a read follows immediately after a write operation that may have caused a sense amplifier to saturate, and thus unable to recover in time to allow detection of the differential voltage of the cell being read. Slow Sense Amplifier Recovery: This failure mode is caused by a sense amplifier that requires excessive time to detect one logic state after a long period of detecting the opposite logic state.

Memory testing time is proportional to the square of the memory size (n2)

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Functional Testing Algorithms (contd) ZERO-ONE Test:

This is a minimal test consisting of writing 0s and 1s to the memory cells followed by read operations. This algorithm is known as Memory Scan, MSCAN. the test length for this test is 4n (n = memory size).

Functional Testing Algorithms (contd) 2n operations (read or write) are needed for each step. Therefore, the test length for this is 42n operations. Pseudorandom Test: In deterministic testing, the control data are used to exercise the memory and then compared to a known reference data to make a pass/fail decision. An alternative way of testing the memories is to use pseudorandom test patterns as the input stimuli in a probabilistic way.

CHECKERBOARD Test:
This another short and simple test in which the memory cells are divided into two groups, cells-1 and cells-2, forming a checkerboard pattern. The checkerboard algorithm can be represented as follows: 1. Write 1 in all cells-1, and 0 in all cells-2. 2. Read all cells (words). 3. Write 0 in all cells-1 and 1 in all cells-2. 4. Read all cells.
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Functional Testing Algorithms (contd) The advantage of this is that one can detect complex faults with fairly high probability and within reasonable time. Pseudorandom testing consists of applying a string of random patterns simultaneously to a memory device under test and to a reference memory (which may be wither hardware or software configured). and compare the outputs of those memories. Pseudorandom testing is widely accepted., but the amount of fault coverage cannot be guaranteed very accurately. The probability of fault coverage are usually around 99.5%.
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References
S.M. Sze, "Modern Semiconductor Device Physics," John Wiley & Sons, 1998. ISBN 0-471-15237-4 H. Ishiuchi, T. Yoshida, H. Takato, K. Matsuo, H. Momose, S. Sawada, K. Yamazaki, K. Maeguchi, International Electron Device Meeting, Technical Digest, pp. 33-36, 1997. W.D. Brown and J.E. Brewer, Nonvolatile Semiconductor Memory Technology, A Comprehensive Guide to Understanding and Using NVSM, IEEE Press, 1998. ISBN 0-7803-1173-6, or TK7895.M4N634 1997

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