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Outline
Introduction System Fixed Fixed
Sample Tips
Switch Matrix
I/O Buffers
Slice
MUX
Register
Switch Matrix
MUX
Register
LUT
Misc Logic
table
multiplier
Virtex-2 Pro 23,316 XC2VP50 Virtex-4 42,176 XC4VFX100 Virtex-6 LX240T 37,680
Virtex-4 42,176 12 160 XC4VFX100 v3 uses this chip Virtex-6 37,680 12 768 LX240T Virtex-7 63,400 XC7VX415T 12 2,160
Hardware
description languages (HDL) like Verilog/VHDL allow designers to specify at a higher level than logic gates will use an even higher level tool called System Generator programming environment within Matlabs Simulink
We
Graphical
Generator provides two key tools for building your model generator: model ! HDL
Blocks
Hardware Simulink
provides a test environment for your design test vectors with MATLAB or Simulink blocks
System Generator
MATLAB Simulink
fir(10,0.2) sin(0:1024./pi)
SysGen
Xilinx Blocks
VHDL
Generate
Bit T r
ue
Xilinx Blocks
Simulink Blocks
Simulink Xilinx
Relates sample period to hardware clock Used to synthesize model Sets target FPGA device for model
Simulink Blocks
Must
Operate on oating point values Source: continuous-time oating point constant Sink: signal vs. time scope
Good
Gateway Blocks
Convert Top-level Must
model needs a System Generator token start and end with Gateway blocks : double to xed point conversion : xed point to double conversion
System Generator
Models Any
Simulink blocks can be used outside gateways for data sources and output analysis
Good Only
Xilinx blocks can be used inside gateways treats gateways as top-level ports
Synthesis