Digital Signal Processing

BITS Pilani
Pilani|Dubai|Goa|Hyderabad

Date : 09/1/2014

DIGITAL SIGNAL PROCESSING A signal is a function of one or more independent variables. y1 = sin (2 . Pi. 10. t); How many independent variables? This is a 1D signal. How do you represent a gray scale image pixel? Y = F (x, y); A signal can be M- dimensional.

SIGNAL

This photograph is a ____ D signal?

SIGNAL A signal is called scalar valued if its value is unique for every instant of independent variables. If a signal has multiple values at any instant, it is called as vector valued signal. Ex: Black and white image ? Colour image?

A black and white video is a ___D signal? A color video signal is a___ D signal? 3 channel and 3D signal.

DIGITAL SIGNAL PROCESSING

Three basic operations used in DSP are: Multiplication Addition Delaying

DIGITAL SIGNAL PROCESSING

1. Simple time domain operation 2. Filtering 3. Signal generation 4. Generation of complex valued signal 5. Amplitude modulation 6. Quadrature amplitude modulation 7. Multiplexing and demultiplexing

Advantages of DSP
More robust than analog signals with respect to temperature and other time variation. Easy to adjust the processing characteristic just by changing the coefficients. Accuracy can be controlled by changing the word length of signal. Flexibility (Programmability and reusability) Digital signals can be stored, recovered, transmitted received and manipulated virtually without any error. Reproductively is easy. Exact linear phase No loading problem due to cascading

Disadvantages of DSP over ASP DSP design can be expensive especially for high bandwidth signals where fast analog to digital conversion is required(>10 MHz). Design of DSP system is extremely time consuming and highly complex and specialized activity. DSP device consume more power and thus not suitable in some cases using battery power. The need for ADC and DAC not economical for simpler application.

DISCRETE TIME SIGNALS

Classification of DT signals

Periodic and aperiodic signal Symmetric and antisymmetric signal Energy and Power Signal

DISCRETE TIME SIGNALS

Properties of DT signals

The highest frequency of DT signal is pi.

DT sinusoid whose frequency differ by integer multiple of 2*pi are identical

The frequency of oscillation of DT sinusoid

increase as w

increases from 0 to pi and decreases as w increases from pi to 2*pi.

DT sinusoids are not necessarily periodic.

DSP techniques can be applicable if the system is a LTI i.e. linear time invariant. Most useful systems fall into linear time invariant category . In DSP , the signal being processed is broken into simple components, each component is processed individually, and the result is reunited.

Superposition the foundation of DSP

Common decompositions:
Impulse decomposition:
An N samples signal is decomposed in to N component signals, each containing N samples. Each of the component signals contains one point from the original signal, with the remainder of the values being zero. A single nonzero point in a string of zeros is called an impulse.

Fourier Decomposition: Fourier decomposition is important for three reasons. First, a wide variety of signals are inherently created from superimposed sinusoids. Second, linear systems respond to sinusoids in a unique way: a sinusoidal input always results in a sinusoidal output. Third, the Fourier decomposition is the basis for Fourier analysis, and the even more advanced Laplace and ztransforms. Most cutting-edge DSP algorithms are based on some aspect of these techniques.

Step decomposition: Even/Odd Decomposition Interlaced Decomposition:

Use of Impulse decomposition:

Convolution for discrete signal Convolution calculates out put of a system ( whose impulse response is known) for any discrete input. How? Impulse response

What will be the system out put to the following signal?

Input Output

Use Impulse decomposition Each impulse will be a shifted and scaled delta function. Obtain system response to each decomposed impulse. Super impose the response corresponding to each decomposed impulse. Can you draw the shape of the system output corresponding to the above input?

CONVOLUTION

x[n]

h[n]

y[n]

x[n] * h[n] = y[n]

If x[n] is an N point signal running from 0 to N-1, and h[n] is an M point signal running from 0 to M-1, the convolution of the two: y[n]= x[n] * h[n], is an N+M-1 point signal running from 0 to N+M-2, given by:

Example: x[n]= [0, 1, 2, -1, 1, 2, 1, 2, 1] h[n] = [0, 1, -1, 0] y[6]=? Here N=9, M=4 = h[0] x[6-0]+h[1]. X[6-1]+h[2].x[6-2]+h[3].x[6-3] = 0+(1)(2)+(-1)(1)+0 =2-1 =1 For obtaining the DSP system output we have to do mainly multiply and accumulate operation.

Analysis of computation required for FIR filter

Expression for 8-tap FIR filter. Y[n] = a0 X[n]+ a1 X[n-1]+ a2 X[n-2]+ -- - - - +a7X[n-7] Most recurring computation is multiplication and then accumulation (MAC)

DSP~GPP
Real time throughput requirement Used in embedded application. To support DSP computation like FFT, convolution, special features are provided. Have MAC unit Not real time throughput needed Desktop computing No special features.

What is the best suitable architecture for DSP?

Architectural evolution:
Von Neumann

Called as Von Neumann architecture. Designed by: John Von Neumann, an American mathematician. Single memory shared by both the program instructions and data. Most computers today are of the Von Neumann design.

How many cycles needed for MAC instruction for two numbers that reside in external memory? 1. Get the opcode of instruction. 2. Get data1 3. Get data2 4. Multiply and accumulate and store result. (Assume that CPU computation takes very small time in comparison to memory access) So need four cycles.

Harvard architecture

Developed at Harvard University (1940) Program instructions and data can be fetched at the same time. Increasing overall processing speed Most present day DSPs use this dual bus architecture. Ex: ADSP-21xx and AT&T's DSP16xx.

Cycles needed for MAC instruction in Harvard architecture

1. Instruction 1 fetched. 2. Instruction 1 decode and get data1 from DM and coefficient from PM 3. Perform MAC operation and store result in DM as well as fetch Instruction 2 from PM. 4. Instruction 2 decode get data1 from DM and coefficient from PM 5. Perform MAC operation and store result in DM (for inst 2) as well as fetch Instruction 3 from PM. So single MAC operation need 3 cycles

Modified Harvard architecture

Three memory banks Allow three independent memory accesses per instruction cycle. Processors based on a three-bank modified Harvard architecture include the Zilog Z893xx, Motorola DSP5600x, DSP563xx

Multiple-Access Memories
Using fast memories that support multiple, sequential accesses per instruction cycle over a single set of buses OR Using multi-ported memories that allow multiple concurrent memory accesses over two or more independent sets of buses.

This arrangement provides one program memory access and two data memory accesses per instruction word. Ex: Motorola DSP561xx processors.

Super Harvard Architecture (SHARCH DSP)

Part of program memory is used as data memory. Including an instruction cache in the CPU. The first time through a loop, slower operation Next executions of the loop will be faster This means that all of the memory to CPU information transfers can be accomplished in a single cycle. EX: ADSP-2106x and new ADSP-211xx

Enhanced DSP architectures:

Very Long Instruction Word (VLIW) architecture:

VLIW CPUs have four to eight execution units. One VLIW instruction encodes multiple operations. EX:if a VLIW device has four execution units, then a VLIW instruction for that device would have four operation fields. VLIW instructions are usually at least 64 bits in width. VLIW CPUs use software (the compiler) to decide which operations can run in parallel. Hardware's complexity for instruction scheduling is reduced. EX: TMS320 C6xx

Endians:
Big Endian(MSB in first location) Little endian How 12345678 will be stored in four location starting from 4000 in each case? TI DSP: Little endian Motorola DSP: Big endian

Numeric Representation used in DSP

Fixed-point
16-bit 20-bit 24-bit
Narrow dynamic range but costs low. Faster than FLPDSP

Floating-point
32-bit 64-bit 80-bit 128-bit
Wider dynamic range but complex hardware. Slower than FIPDSP

Fixed-Point Notation
A 16-bit fixed-point number can be interpreted as either: Integer (i.e., 20645) Fractional number (i.e., 0.75)

Integer:
Unsigned integer (from 0 to 216 i.e. 65,536) Signed integer (from 32,768 to 32,767) N-bit fixed point, 2s complement integer representation X = -bN-1 2N-1 + bN-2 2N-2 + + b020

What will be the value of 1 0 10 1 1 0 0 ?

Represent 3 using 3-bit twos complement representation. What is the maximum and minimum number you can represent using 3-bit twos complement representation?

So the dynamic range is from -4 to 3.

Let us do multiplication using 3-bit twos complement representation. 1. Multiply 2 with (-1)

Take twos complement and remove two extended sign bits.

Is the result correct ? 2. Multiply 2 with (-3)

2. Multiply 2 with (-3)

Now removing the two extended sign bits to have size of 3 we get:

Is the result correct? No. Overflow occurs as the result (-6) is out of dynamic range (-4).

Let use find the fractional representation of 3 in twos complement form? =?

011

001

Multiply 2 with (-3)

If we truncate the two LSB bits:

What is the error?

So the overflow error is avoided. As multiplication of fractional number can not exceed dynamic range no overflow will be there.

Some parameters to define representation accuracy Precision Smallest step (difference) between two consecutive N-bit numbers. Dynamic Range Ratio between the largest number and the smallest (positive) number. It can be expressed in dB (decibels) as follows: Dynamic Range (dB) =

20 log10 ( Max / Min)

Quantization error is the numeric error introduced when a longer numeric format is converted to a shorter one, e.g., when we round 1.325 to 1.33, we introduced a quantization error of 0.005.

In integer representation the precision is how much? In DSP much more precision is needed. So fractional number representation is used.

Fractional Fixed-Point Representation Called as Q-format (Quantity of fractional bits)

General Fractional Fixed-Point Representation

Q m.n notation m bits for integer portion n bits for fractional portion Total number of bits N = m + n + 1, for signed numbers Example: 16-bit number (N=16) and Q2.13 format 2 bits for integer portion 13 bits for fractional portion 1 signed bit (MSB) Special cases: 16-bit integer number (N=16) => Q15.0 format 16-bit fractional number (N = 16) => Q0.15 format; also known as Q.15 or Q15

S Integer (15 bits)

Q15.0

S Fraction (15 bits)

. .
Q.15 or Q15 Used in DSP

Binary pt position .
Q1.14

Upper 2 bits

Remaining 14 bits

Q15 used in 16-bit DSP chip, resolution of the fraction will be 215 or 30.518e6 Q15 means scaling by 1/215 Q15 means shifting to the right by 15 Example: how to represent 0.2625 in memory: Method 1 (Truncation): INT[0.2625*215]= INT[8601.6] = 8601 = 0010000110011001 Method 2 (Rounding): INT[0.2625*215+0.5]= INT[8602.1] = 8602 = 0010000110011010 By this method of rounding or truncation we introduce quantization error

Represent 0.95624 in Q4 format. Use truncation and rounding. 15.2999984 01111 Find the quantization error. Ans: 0.01874 Overflow in Fixed point addition:

Can you add 3 and 1?

This is a positive or negative number? Over flow will be there.

Numeric Representation used in DSP

Fixed-point
16-bit 20-bit 24-bit
Narrow dynamic range but costs low. Faster than FLPDSP

Floating-point
32-bit 64-bit 80-bit 128-bit
Narrow dynamic range but complex hardware. Slower than FIPDSP

Floating point representation:

Most important standard is IEEE-754 There are four type of IEEE-754 floating point representations depending on number of bits used in it. Single precession: 4 bytes Double precession: 8 bytes Extended Double precession: 10 bytes Quadruple precession: 16 bytes

Floating point representation:

Actual Emax =127 Emin = - 126 More accuracy Increased range

Normalized or biased 254 1

Floating point representation:

A number is represented by two parts: a mantissa and an exponent where value of the number = mantissa x 2exponent The mantissa is usually a signed fractional value with a single implied (not actually stored) integer bit. Exponent is in excess or biased notation (biase = 127 for single precision and 1023 for double precision) The exponent is an integer that represents the number of places that the binary point of the mantissa must be shifted right or left to obtain the original number represented.

Floating point representation:

EX: what is the value of 1 10000001 01000000000000000000000 Exponent = 129-127=2 Fraction part =0.012 = 0.25 Value = - 1.25 * 22 = - 5 Express +0.5 in single precision format. 0.5 = 1.00*2-1 Exponent = 126 (126-127=-1), sign is 0, fraction part = 0.00 0 01111110 00000000000000000000000

Floating point representation:

Ex: Represent 100.25 in IEEE754 floating point format. Steps: 1. Convert decimal to binary 2. Represent binary number obtained in proper format 3. Represent exponent in biased format 4. Zero pad. ANS: 100 = 1100100 0.25 = 0.01 100.25= 1100100.01=1.10010001*26 X-127=6 X=133 = 85h=10000101 0 1000 0101 1001000100000

Floating point representation: Floating point multiplication:

E = E1 +E2 - 127 Example: X1 = 1 10000010 00000000 X2 = 0 10000011 000.00 Ans? 1 10000110 000000

Floating point representation:

Let E1 = 250 and e2 = 250 What will be E? Need 9 bits to represent and not available. Over flow in multiplication Underflow in multiplication The minimum value of biased exponent = 1 (= -126 actual) If an actual number has exponent less than -126, this can not be normalized and called as denormal number. Ex: X = 1* 2 -64 and x2 = 1* 2 -65

Floating point representation:

Floating point addition:

EX: (- 1. 001) * 2-2 + (- 1.011) * 20 Steps: 1. Align the exponent 2. Add or subtract the mantissa 3. Normalize result Representation of specific values

Why do we need transformations?

We can't analyze all the signals that we want to, in their existing domain. Transforming a signal means looking at a signal from a different angle so as to gain new insight into many properties of the signal that may not be very evident in their natural domain. Transformation is usually implemented on an independent variable.
Continuous time signal 1. Fourier series (FS) 2. Fourier transform (FT) Discrete time signal 1. Discrete Fourier transform(DFT) 2. Discrete Time Fourier transform(DTFT) 3. Z-Transform(ZT) 3. Laplace Transform(LT)

January 11, 2014

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CTFT

DTFT

DFT

Design of Digital filter

Objective - Determination of a realizable transfer function G(z) approximating a given frequency response specification. The TF must be stable. There are two types of digital filters are there i.e. FIR and IIR. 1. FIR filter Which type of filter is this? Can you find h[n]?

If h[n] is of finite length or of infinite length? If y[n] will be of finite length or infinite length?

2. IIR filter:

a1 = - 0.9

Can you find y[n] for different values of n? Assume y[n] = 0 for n <0 What is this y[n] is called as Can it be called as impulse response?

What is the length of this impulse response? Infinite.

Can you find the z- transform and H(z) of this ? Can I write the expression for y[n] in generalized form as

Can you find z- transform and H(z) of this ?

Can I call this TF as Infinite impulse response TF .

Example: A digital system has the following response:

Can you find the impulse response for this system? h[0], h[1], h[2], .

Will this system stable? No

Can I write y[n] as following with a1 = -1.2?

Can you find H(z) for this?

What will be the pole of this TF? Can you show the location of pole in z plane? An IIR filter is stable if all poles of the TF are within the unit circle.

What are the location of the poles? At zero. So FIR filter is always stable.

Selection of Filter Type IIR FIR

p 0 + p1 z 1 + p 2 z 2 + L + p M z M H (z) = d 0 + d 1 z 1 + d 2 z 2 + L + d N z N
N

H (z) =

n=0

h[ n ] z n

Advantages in using an FIR filter (1) Can be designed with exact linear phase (2) Filter structure always stable with quantised coefficients Disadvantages in using an FIR filter - Order of an FIR filter is considerably higher(~10 times) than that of an equivalent IIR filter meeting the same specifications; this leads to higher computational complexity for FIR

FIR filter design using FS method. Need to find impulse response for finite duration. Direct truncation of impulse response leads to well known Gibbs phenomenon. It manifests itself as a fixed percentage overshoot and ripple before and after discontinuity in the frequency response

Low-Pass FIR Filter: Rectangular Window Application j N =5 N = 25 G (e )

G ( e j )

/2
G (e
j

N = 50
G (e

/2
j

N = 100

/2

/2

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Direct truncation of impulse response leads to well known Gibbs phenomenon. It manifests itself as a fixed percentage overshoot and ripple before and after discontinuity in the frequency response

IIR Digital Filter Design methods

1. IIR Filter design: Impulse-Invariant Method

2. IIR Filter design: Bilinear Transformation Method