A

B
C
D
PI_EVEN_RIN0N1 PI_ODD_RIN0N 1 RXINDN0 1 RXINBN0 1 RXINCN0 1 RXINAN0 1
PAD PAD PAD PAD PAD PAD

AN0

BN0

DN0
CN0

TP1996
TP2010
PI_EVEN_RIN0P 1 PI_ODD_RIN0P 1
PAD PAD RXINDP0 RXINBP0 RXINCP0 RXINAP0
1 1 1 1
PAD PAD PAD PAD

AP0

BP0

DP0
CP0

TP1995
TP2009
PI_EVEN_RIN1N1 PI_ODD_RIN1N 1
PAD PAD
RXINDN1 1 RXINBN1 1 RXINCN1 1 RXINAN1 1

TP1986
TP2008
PAD PAD PAD PAD

AN1

BN1

DN1
CN1
PI_EVEN_RIN1P 1 PI_ODD_RIN1P 1
PAD PAD

TP1985
TP2007
RXINDP1 1 RXINBP1 1 RXINCP1 1 RXINAP1 1
PAD PAD PAD PAD

AP1

BP1

DP1
CP1
PI_EVEN_RIN2N1 PI_ODD_RIN2N 1
PAD PAD

NC

TP1988
TP2002
PI_EVEN_RIN2P 1 PI_ODD_RIN2P 1 RXINDN2 1 RXINBN2 1 RXINCN2 1 RXINAN2 1

R0036
PAD PAD PAD PAD PAD PAD

AN2

BN2

DN2
CN2

TP1987
TP2001
VCOMF

NCR0063
NCR0038
R0037
R0064

GND
PI_EVEN_RINCLKN
1 PI_ODD_RINCLKN
1 AVDD

01.Gamma

GND
PAD PAD RXINDP2 RXINBP2 RXINCP2 RXINAP2 AVDD AVDD VCOMF
1 1 1 1
PAD PAD PAD PAD

AP2

BP2

DP2
CP2

TP1992
TP2006
HAVDD

Close to J4
PI_EVEN_RINCLKP
1 PI_ODD_RINCLKP
1
NC

PAD PAD V3D3 VCOMF2

5
5

XVCC

RXCLKDN 1 RXCLKBN 1 RXCLKCN 1 RXCLKAN 1 VGL V3D3

TP1991
TP2005
M_VCOMI2
PAD PAD PAD PAD
R0022
R0021

R0091
VGHC Close to J4

CLKAN
SCL_I SCL_GA

CLKBN

CLKDN
CLKCN
PI_EVEN_RIN3N1 PI_ODD_RIN3N 1
PAD PAD SCL_GA

VGMA[1..22]
SDA_I SDA_GA
U_DB

YV1C SDA_GA

V1D2
V3D3

PANEL_VCC
G2

TP1990
TP2004
RXCLKDP 1 RXCLKBP 1 RXCLKCP 1 RXCLKAP 1 G1

YV1C
PAD PAD PAD PAD

NCNC
PI_EVEN_RIN3P 1 PI_ODD_RIN3P 1 M_VCOMI2 80

R0092
PAD PAD

VGL

CLKAP

CLKBP
YDIOD YDIOD

CLKDP
CLKCP
79

VGHC
YOE YOE 78

TP1989
TP2003
U_DB 77

1
1
PI_EVEN_RIN4N1 PI_ODD_RIN4N 1 RXINDN3 1 RXINBN3 1 RXINCN3 1 RXINAN3 1 YCLK YCLK 76
PAD PAD PAD PAD PAD PAD

AN3

BN3

DN3
CN3
YDIOU YDIOU 75
XVCC 74

TP1994
TP2000
PANEL_VCC
PAD
PAD
73

SCL_GA1
SDA_GA1
PI_EVEN_RIN4P 1 PI_ODD_RIN4P 1 72
PAD PAD RXINDP3 RXINBP3 RXINCP3 RXINAP3 VGL
1 1 1 1 71
PAD PAD PAD PAD

AP3

BP3

DP3
CP3
70

TP1993
TP1999
VGHC 69
68
VCOMF 67

HAVDD
SCL 1 RXINDN4 1 RXINBN4 1 RXINCN4 1 RXINAN4 1 VCOMF2 66

V3D3
AVDD
PAD PAD PAD PAD PAD

AN4

BN4

DN4
CN4
65

U2810
XSTB 64

M_VCOMI2
XPOL 63
PVCC 1 SDA 1 XVCC XDIOB 62

C0003
C0002
C0001
PAD PAD RXINDP4 RXINBP4 RXINCP4 RXINAP4 VGMA[1..22]
1 1 1 1 61

B0004
B0001
B0002
PAD PAD PAD PAD

U2811
AP4

BP4

DP4
CP4
VGMA22 60

TP1978
VCOMF2
VGMA21 59
M_CHECK WP_E VGMA19

YOE
1 1 58

YCLK
PAD PAD

YDIOD
VGMA17 57

YDIOU
VGMA15 56

TP2820
TP2818
VGMA13 55
AG 1 HSYNC_F 1 VGMA12 54
PAD PAD VGMA11 53
VGL

VGMA10 52

TP2821
TP2819
XVCC
VGHC

VGMA8 51

C0006
C0005
C0004
VCOMF2

LVDS_FORMAT 1 VGMA6 50
PAD

Close to J3,J4
VGMA4 49
VGMA2 48

TP1979
VGMA1 47

C0009
C0008
C0007
SCL_E 1 46

XAVDD
PAD XAVDD 45
44

TP1982
XVCC

VGL
XHAVDD 43

V1D2
V3D3
YV1C
VGHC
FRC_RST 1 T1_RVP[4..6] 42

XHAVDD
PAD
41
T1_RVN[4..6] T1_RVP4 40

TP1981
T1_RVN4 39
SDA_E 1 T1_RVP5 38
PAD T1_RVN5
XAVDD
VGMA[1..22]

37
XSTB
X-BACK/Right

XPOL

XHAVDD

T1_RVP6 36

TP1983
T1_RVN6 35
34
33
32
T2_RVP[4..6] T1_RVCLKP 31
T1_RVCLKN 30

YV1C_S
XSTB_S T2_RVN[4..6] 29
T2_RVP4 28
T1_RVP[4..6] T2_RVN4 27

PAD
XPOL_S PAD
PAD

T2_RVP5 26
1 T1_RVN[4..6] T2_RVN5 25
1
1

T2_RVP6 24

XIN_S
T2_RVN6 23

SCL_I
SDA_I
22
21
T1_RVP0 20

4
4

YV1C_S
XSTB_S

XPOL_S

T1_RVN0

B12V
19
T1_RVP1 18
T1_RVN1

CIS
17

C177
GND
V1D2
V3D3

T1_RVP2 16
XIN_S

EXSCL
EXSDA

03.TCON_S
T1_RVN2
XSTB_S

15
YV1C_S
XPOL_S

RXINAN0 14
RXINAP0
T1_RVCLKP

13
T1_RVCLKN

T1_RVP[4..6]

R0047
T1_RVN[4..6]

T1_RVP[0..2]

CIS
12

C178
RXINAN1 T1_RVP[0..2] T2_RVCLKP 11
RXINAP1 T1_RVN[0..2] T2_RVCLKN 10
T1_RVN[0..2]

CIS
9

R0046
RXINAN[0..4]

BD103
RXINAN2 T2_RVP0 8
RXINAN[0..4] RXINAP2 T2_RVN0 7
RXINAP[0..4] RXINAP[0..4] T2_RVP1 6
RXCLKAN T2_RVN1 5

R0048
RXCLKAP T2_RVP2 4

SW_PVCC
RXINAN3 RXCLKAN T2_RVN2 3
RXINAP3 T2_RVP[0..2]

CIS
2

C106
RXCLKAP
1
T2_RVN[0..2]
J4

CIS
RXINAN4

R105
RXINAP[0..4]
RXINAP4
RXINAN[0..4]

R0045

CIS
R101
2 3

2
R0044

NC
1 4 T1_LVP[4..6]

R0049
1 3 T1_LVP[4..6]
T1_LVN[4..6]
XPOL
XSTB

T1_LVN[4..6]

CIS
CIS
C107

Q101
RN001

CIS
RXINCN0

R104
RXINCP0 T1_LVCLKP
T1_LVCLKP
RXINCN1 T1_LVCLKN

4
3
2
1
R0043
RXINCP1 T1_LVCLKN

S
S
S

G
RXINCN2 RXINCN[0..4]

CIS
IC101
R0040

RXINCN[0..4] RXINCP2 T1_LVP[0..2]

D
D
D
D
RXINCP[0..4] RXINCP[0..4] T1_LVP[0..2]
RXCLKCN T1_LVN[0..2]

5
6
7
8
R0042

RXCLKCP T1_LVN[0..2]
RXCLKCN
1
PAD
RXINCN3 RXCLKCP
RXINCP3
RXINCP[0..4]

RXINCN4

PANEL_VCC
RXINCN[0..4]

RXINCP4
R0039

CIS
C111
PANEL_VCC
2 3
R0041

NC

1 4
R0050

B12V
LVDSORD

C0022
RN002

LVDSORD
AGBSEN 1
AGBSEN PAD

B0005
U_DB
U_DF
YDIOD
YDIOU

1
PAD
XPOL XSTB

Close to U300

C0021
V12
YOE4_S
YOE3_S
YOE_S
YCLK_S

RST
YDIO_S
U300

3
3

L
H
X
O

High Aging
RST
YOE_S1
1
1
YDIO_S

YCLK_S

YOE4_S
YOE3_S

Close to J1
Normal

F0002
PAD
PAD

NC
PAD YOE_S

1 XPOL
YDIO_S

YCLK_S

R0071
R0070

PAD

12Vin1
XSTB
C0011

D0004
H
L
O
X

NC C0010
YV1C
PAD

B3.3VD
Mirror

1
1

R0014
R0013

1
Normal / Mirror Setting Table

2
2
3

CISCN2615
3
4
4
Close to U401

MGND1
GND
G1
B12V

MGND2 YV1C
R0023

G2
B3.3VD
RXINCLKAP
RXINCLKAN
RXINCLKCP
RXINCLKCN

RXINAP[0..4]
RXINAN[0..4]
RXINCP[0..4]
RXINCN[0..4]

T2_RVP[4..6]
T2_RVN[4..6]
R0015

XOUT_M

J5
12Vin
T2_RVCLKP
V1D2
V3D3

SCL_I
SDA_I

1 T2_RVCLKN
YV1C_M

1
2
2
XPOL_M
XSTB_M

3
3
4
4
5
5
6
GND

6
V1D2
V3D3

7
EXSCL
EXSDA

7
04.TCON_M

8
XSTB_M

YV1C_M
XPOL_M

XOUT_M

8 PI_ODD_RIN0N RXINBN0
9
9 PI_ODD_RIN0N PI_ODD_RIN0P RXINBP0
T2_RVCLKP
T2_RVCLKN

10
T2_RVP[4..6]

RXINBN[0..4]
T2_RVN[4..6]

R0060

10 PI_ODD_RIN0P T2_RVP[0..2]
11
RXINBP[0..4]

11 PI_ODD_RIN1N PI_ODD_RIN1N RXINBN1 T2_RVP[0..2]

12
12 PI_ODD_RIN1P PI_ODD_RIN1P RXINBP1 T2_RVN[0..2]
13
13 PI_ODD_RIN2N T2_RVN[0..2]
14
R0059

14 PI_ODD_RIN2P PI_ODD_RIN2N RXINBN2 RXINBN[0..4]

15
15 PI_ODD_RIN2P RXINBN[0..4] RXINBP2
16
16 PI_ODD_RINCLKN RXINBN[0..4] RXINBP[0..4] RXINBP[0..4]
17
17 18 PI_ODD_RINCLKP PI_ODD_RINCLKN RXINBP[0..4] RXCLKBN
R0061

18 PI_ODD_RINCLKP RXINCLKBN RXCLKBP T1_LVP[4..6]

19
19 PI_ODD_RIN3N PI_ODD_RIN3N RXINCLKBP RXINBN3 RXCLKBN
20 G2
20 PI_ODD_RIN3P PI_ODD_RIN3P RXINBP3 T1_LVN[4..6]
21 G1
21 PI_ODD_RIN4N RXCLKBP T1_LVP4
22 80
22 PI_ODD_RIN4P PI_ODD_RIN4N RXINBN4 T1_LVN4
23 79
23 PI_ODD_RIN4P RXINBP4 T1_LVP5
24 78
24 PI_EVEN_RIN0N T1_LVN5
25 77
R0058

25 PI_EVEN_RIN0P PI_EVEN_RIN0N T1_LVP6

26 76
26 PI_EVEN_RIN1N PI_EVEN_RIN0P T1_LVN6
27 2 3 75
27 28 PI_EVEN_RIN1P 74
R0057

28 PI_EVEN_RIN1N
NC

29 PI_EVEN_RIN2N 1 4 73
R0062

29 PI_EVEN_RIN2P PI_EVEN_RIN1P
30 72
30 T2_LVP[4..6] T1_LVCLKP
31 71
31 PI_EVEN_RINCLKN PI_EVEN_RIN2N T2_LVP[4..6] T1_LVCLKN
32 70
32 33 PI_EVEN_RINCLKP PI_EVEN_RIN2P T2_LVN[4..6] 69
RN003

33 T2_LVN[4..6] T2_LVP4
34 68
34 PI_EVEN_RIN3N PI_EVEN_RINCLKN RXINDN0 T2_LVN4
35 67
35 PI_EVEN_RINCLKP

2
2

36 PI_EVEN_RIN3P RXINDP0 T2_LVP5 66

36 PI_EVEN_RIN4N PI_EVEN_RIN3N T2_LVN5
37 65
R0056
RXINDN[0..4]

37 PI_EVEN_RIN4P PI_EVEN_RIN3P RXINDN1 T2_LVP6

38 64
RXINDP[0..4]

38 RXINDP1 T2_LVN6
39 63
39 PI_EVEN_RIN4N RXINDN[0..4]
40 62
R0053

40 PI_EVEN_RIN4P RXINDN2
41 61
41 RXINDN[0..4] RXINDP2 RXINDP[0..4] T1_LVP0
42 60
42 43 WP_E RXINDN[0..4] RXINDP[0..4] T1_LVN0 59
R0055

43 RXINDP[0..4] RXCLKDN T1_LVP1

44 58
44 LVDS_FORMAT RXINCLKDN RXCLKDP RXCLKDN T1_LVN1
45 57
R2764
WP

45 RXINCLKDP RXINDN3 T1_LVP2

46 56
46 RXINDP3 RXCLKDP T1_LVN2
47 55
47
NC

48 T1_LVP[0..2] 54
48 RXINDN4
49 53
49 RXINDP4 T1_LVN[0..2]
50 52
R0052

R0634

50 T2_LVCLKP
51 51
R0604
R0615

51 T2_LVCLKP
I2C_SCL
SW_PVCC
HSYNC

I2C_SDA

FRC_NRESET
MAIN_CHECK

G1 T2_LVCLKN 50
G1 G2 2 3 T2_LVCLKN T2_LVP[0..2] 49
R0054

G2 T2_LVP[0..2]
Close to U401

G3 T2_LVN[0..2] T2_LVP0 48
G
R0633

G3 T2_LVN[0..2]
NC
NC

G4 1 4 T2_LVN0 47
R0051

G4
FRC_RST CIS

G5 T2_LVP1 46
G5 T2_LVN1
R657

G6 S D 45
SDA R2761_DE
SCL R2760_DE
FRCBlock

PVCC CIS R2770

G6
VGL

G7 T2_LVP2 44
HSYNC
XVCC

AG CIS R2766
HSYNC_F R2763
M_CHECKCIS R2765

G7
VGHC

I2C_SCL
I2C_SDA

T2_LVN2
CIS
XAVDD

G8 43
RN004

SW_PVCC

G8 LVDSORD
XHAVDD

NC
NC
VCOMF2

FRC_NRESET

G9 42
XSTB
XPOL

R0635
M_VCOMI2

G9
MAIN_CHECK
VGMA[1..22]

G10 41
Q0602

G10 AGBSEN
SCL_E
SDA_E

40
VGMA22 39
EDID_WP

VGMA21 38
CIS

VGMA19 37
I2C_SCL VGMA17
C502

36
CIS
CIS
R656CIS

VGMA15 35
1
2
3
4
MGND1
MGND2
RST
YOE4_M
YOE3_M
YOE_M
YCLK_M
YDIO_M

I2C_SDA VGMA13 34
LVDSORD
X-FRONT/Left

U401

VGMA12
CIS
1
2
3
4

33
G1
G2

VGMA11 32
CN901
NC

VGMA10 31
C0017
AGBSEN
high Aging

SCL_I
SDA_I
R658
RST

AGING

VGMA8 30
HSYNC
SW_PVCC
MAIN_CHECK

VGMA6
FRC_NRESET

29
YOE_M
YCLK_M
R0027

R555_DE

VGMA4 28
NC

VGMA2 27
YOE4_M
YOE3_M

VGMA1 26
YDIO_M R0066

25
YOE

24
R0033

XAVDD 23
D0006

22
R0018

XHAVDD 21
V3D3
D0002
Path balance between U300 &U401

XVCC XDIOF 20
D0003
YDIOD
YDIOU

19
YCLK

C0024

XPOL 18
R544
R539_DE

1 XSTB 17
PAD
NC

16
EDID_WP

15
VCOMF2 14
R0094
R0025 AGING

1 13
V3D3

PAD
RST

1 VGHC 12
PAD
11
SCL_I

VGL
B3.3VD

10
LVDS_FORMAT
C0015
C0014
C0013
C0012

9
C0026

R0010

XVCC 8
NC
NC
NC
NC

R0001

Path balance between U300 &U401

1 7
PAD YDIOU YDIOU 6
SDA_I

YCLK YCLK 5
U_DF 4
R0028
R0095

YOE YOE 3
V3D3
Close to U401

YDIOD YDIOD 2
M_VCOMI2 M_VCOMI2 1
Size
J3

Date:

1
1
1

Custom

1
SCL_I
SDA_I
I2C_SCL
GH1

I2C_SDA

Model Name
1
1
1
1

EDID_WP

<Variant Name>
U_DF

GH7
PAD
PAD
PAD
PAD

CIS
CIS

5
6
7
8
R15_OP
R14_OP

1
NC

Document Number
XVCC

1 1
YOE

GH6

T315HW02
Top View
WP
YCLK

SCL
VCC
YDIOD
YDIOU
R0020
R0019

GH2

GH11

A2
A1
A0

SDA GND
U0106
Close to J3

Wednesday, October 01, 2008

4
3
2
1

1 1
T315HW02 V3 Tcom MEMC Board

1
GH8
GH9
Td(sec) = R(Ω) * C(F) * 0.79
=0.022u * 5.62M * 0.79 = 97mS

SCL_I

SDA_I

Sheet
GH3

V3 Tcom\MEMC Board
1

1
1
R0093
GH5

of
GH10

1
GH4

10
友達光電電視顯示器產品研發處

Rev
EC02
A
B
C
D
 5 4 3 2 1

D D

AUO Confidential

80 J4 1 80 J3 1

T-CON_1(Slave) T-CON_2(Master)
AUO-12401 B1 AUO-12401 B1
GAMMA
C U0300 U0401 C
DC-DC 1 1

FRC PART
[Page: FRC_IO,
FRC_DDR
and FRC_POWER]
I2C Connector(4Pin)

DDR
1
IC500
DDR
4
CN901

1 4 1 51
Power Connector(4Pin) LVDS Connector(51Pin)
CN2615 J1

B B

A A

<Variant Name>

友達光電電視顯示器產品研發處
Model Name T315HW02 V3 Tcom MEMC Board
Placement
Size Document Number Rev
C T315HW02 V3 Tcom\MEMC Board EC02
Date: Wednesday, October 01, 2008 Sheet 1 of 10

5 4 3 2 1
 5 4 3 2 1

AVDD
R0221

PAD
Layout closely to IC, far from D201 and L201
TI65161: R201=127K; R203=10K; C206=120pF
BD8160: R201=127K; R203=10.2K;C206=200pF NC

1
15.73±0.08V
D0201
410mA(avg)/680mA(peak)
PANEL_VCC
SW Vo1 S D AVDD_F
AVDD
L0201
R0225
Q0201

G
D R0201 D
C0201 C0202 R0220
C0203 C0204 C0213 C0214 C0215 C0216 C0217 C0218

C0206

R0202 C209: AVDD soft-start time control

TI65161: R213=0 ; C207=22n
BD8160: R213=7.5K; C207=2.2n
C201, C202 put closed to L201 U0201 C0209
R0212
C0207 1 28
R0213 FB SS
R0203

2 27 GD
COMP GD

Vo1 3 26 C0210 C210: AVDD and VGH delay time control

OS DLY2

C0208
C211: VGL delay time control
4 25 C0211
SW DLY1

Trace overlapping
SW 5 24 REF
SW REF

C0256 6 23 C0212
PGND GND
NC
7 22
D0207 D0206 PGND AVIN

C
NC NC C109 put closed to Pin 8
C
Vo1 8 21 PANEL_VCC
SUP VINB
C0255
D0205 D0204 C0251 C0231
PANEL_VCC 9 20 C0230
R0230 EN2 VINB

C0252 V3D3
R0224 10 19

PAD
DRP NC
D0203

1
VGL
VGL R0223 A C0253 C230 put closed to Pin 22 C231 put closed to Pin 20

1
R0231 C0261 C0258 C0257 J 11 18 L0202 3.3V
PAD C0254 K DRN SWB
R0211 Layout close to IC 1000mA(avg)/1200mA(peak)

1
VGH R207 C0232
12 17 V3D3_F V3D3

PAD
PANEL_VCC FREQ BOOT V3D3
Current limit R to reduce inrush R0222 V1D2
current during YV1C switch VGL D0202

PAD
REF R0208 13 16 C0233 C234 R0204
FBN EN1 PANEL_VCC
C0235 1.2V
1000mA(avg)

1
U0302
14 15 R0262
FBP FBB V1D2_F V1D2

G1
Layout closely to Pin13 and far from D203, D204, D205,D206 and D207 I O

GND
Vin Vout V1D2
TI65161: R207=49.9K; R208=10K
BD8160: R207=61.2K; R208=10K

G1

G
U0204 R0205 C237 C238
C0236
12

11

G1 R0209
GND

GND

G1 GND GND
250mA(avg) VGH 1 10
VGH VFLK YV1C
VGHM R0227 2 9 Layout closely to pin15 and far from L202 and D202
B
VGHC VGHM CD B
TI65161: R204=191K; R205=110K; C235=10pF
3 8 R0210
SVGHM VDPM BD8160: R204=191K; R205=110K; C235=68pF
NC R0228
C0259
NC
C0260
4
RE VD
7 C0275
GND

GND

R0252 R0251 R0250 C0270

NC
5

R0257 R0258 AVDD

R0249 R0248
AVDD
Layout close to Pin14 and far from D203, D204, D205,D206 and D207 1/2 AVDD soft-start
R0253 R0254 R0255 TI65161: R209=226K; R210=10.2K U0208
BD8160: R209=226K; R210=10.2K close pin7
1 8 close pin6
SS EN
C0263 2 7 R0261
BST COMP
PANEL_VCC 3 6
VFB=0.9V R0259
VIN FB R0260
C0626 4 5 C0271 C0268
SW GND

G1
C0264

G1
HAVDD

PAD
7.02±0.1V
410mA(avg)/680mA(peak)
MAX : 3.2 mm

1
L0203
HAVDD_F HAVDD
HAVDD
R0256
D0208
C0265 NCC0266 C0267
A A

<Variant Name>

友達光電電視顯示器產品研發處
Model Name T315HW02 V3 Tcom MEMC Board
DC-DC
Size Document Number Rev
Custom T315HW02 V3 Tcom\MEMC Board EC02
Date: Wednesday, October 01, 2008 Sheet 1 of 10
5 4 3 2 1
 5 4 3 2 1

VGMA_REF MPVGMA131 VGMA13

8
AVDD R0156 MPVGMA122 7 VGMA12
NC

PAD
MPVGMA1 VGMA1 MPVGMA113 6 VGMA11

R0100 R0101 VGMA[1..22] VGMA[1..22] R0171

NC MPVGMA104 5 VGMA10

1
REFB1 VGMA1 RN108
AVDD AVDD VGMA_REF NC
C0101

1
R0105 R0107
Close to U103 pin38 Close to U103 pin32 AVDD_MGA MPVGMA8 1 8 VGMA8

PAD
C0124 C0125 R0106 MPVGMA6 2 7 VGMA6 MPVGMA211 8 VGMA21

GND VG1 C0170

C0171 MPVGMA4 3
MPVGMA2 4
NC 6
5
VGMA4
VGMA2
MPVGMA192
MPVGMA173 NC 7
6
VGMA19
VGMA17
GND
REFB2 VGMA2 MPVGMA154 5 VGMA15
REF_F1 REF_F11
R0108 RN107

C
1 REF_F1 1 REF_F11 RN109
C0102

1
PAD PAD

CATH

PAD
VZREF C0115 C0117
D R0115 D
1 R R0112
PAD REF U0104 VG2 R0157

ANODE

MPVGMA2

MPVGMA1
R0113 REFB4 VGMA4 R0172 MPVGMA22 VGMA22

4 5 RN104
NC
C0103

1
3 6

A
R0114 R0120 2 7 R0173

PAD
Close to U103 pin23 1 8
R0118 VCOMF2

REFB6
VG4
VGMA6 U0105
NC
Close to U103 pin29

14

13

12

11

10

8
REF_F22 REF_F12
R0174 V3D3
NC

GMA2

GMA1

GMA0

AGND

AVDD

VDD_AMP

VCOM_FB
C0104

1
1 REF_F22 1 REF_F12
PAD PAD MPVGMA4 15 7

PAD
R0123 R0124 GMA3 VCOM
C0116 C0118
MPVGMA6 16 6
VG6 GMA4 GND_AMP R0175
REFB8 VGMA8 MPVGMA8 17 5 V3D3_MGA
Close to U103 GMA5 DVDD R0176
C0174
C0173 NC
MPVGMA10 18 4
C0105

1
R0126 R0127 GMA6 A0
MPVGMA11 19 3

PAD
GMA7 SDA
AVDD_MGA 20 2

REFB1
Positive Gamma Value REFB10
VG8
VGMA10
AVDD SCL
MPVGMA22
21 1

GMA10

GMA11

GMA12

GMA13

GMA14
AGND GMA15

GMA8

GMA9
R0180 R0181
R0103

G1
C0106

1
Close to U103 pin30

PAD

22

23

24

25

26

27

28

G1

SDA_GA
R0104

SCL_GA
REF2

MPVGMA12

MPVGMA13

MPVGMA15

MPVGMA17

MPVGMA19

MPVGMA21
VG10
1 REF_F2 REFB11 VGMA11
PAD AVDD
R0110 4 5 RN105
C0119 C0107

1
3 6
C 2 7 R0177 R0178 C

PAD
1 8
R0111
REF4 VG11

REF_F10
REF_F11

REF_F12
REF_F13
REF_F15
REF_F17
REF_F19
REF_F4 REFB12 VGMA12 V3D3_MGA
1
Max9669 Programmable Gamma Buffer

REF_F4
REF_F6
REF_F8
PAD
R0116
C0108

1
R0169

11
U108A
AVDD R0179
NC

PAD
VCOMF 3 +
R0117 U0103 VCOMF2

36
35
34
33
32
31
30
29
28
27
26
25
1
REF6
NC

G1
R0146 Close to U103 pin22 VG12 U108D

11

11

11
U108B U108C 2 -
1 REF_F6 REFB13 VGMA13

Li
Ki
Ji
Ii
Hi
VSS
VDD
Gi
Fi
Ei
Di
Ci
PAD R0144 REF_F2 REF_F21
37 24 5 + 10 + 12 +

4
R0121 REF_F1 Mi Bi REF_F22 R0170 C0163
38 23 C0109 7 8 14

1
C0127 VCOMI Ni Ai AVDD AVDD_MGA
VCOMF 39 22 6 - 9 - 13 -
R0145 Vcomi VDD C0126
40 21

PAD
R0122 N.C. VSS REFB22
Close to U103 pin43 41 20

4
N.C. Ao
42 19
REF8 AVDD N.C. VSS REFB21 VG13 AVDD_MGA
C0123 43 18
REF_F8 VDD Bo REFB15 VGMA15
1 44 17
PAD VSS N.C.
45 16
R0125 VDD N.C.
46 15 C0110

1
VCOMO VSS VDD
VCOMF2 47 14
REFB1 Vcomo N.C. REFB19
48 13

PAD
VDD
NoVSS Co C0120
VCOMF
Mo

Go
Ho

Do
Ko

Eo
Fo
Lo

Jo
Io

R0128 R0147
REF10 VG15 R0148
NCR0160
1
2
3
4
5
6
7
8
9
10
11
12
REF_F10 C0122 REFB17 VGMA17
1
PAD V3D3
R0129 RN106 BANK_SEL R0161
REFB10
REFB11

REFB12
REFB13
REFB15
REFB17
4 5 C0111
NC AVDD_GA

1
REFB2
REFB4
REFB6
REFB8

3 6 R0167

PAD
Close to U103 pin15 2 7 AVDD
NC

PAD
R0130 1 8
Close to U103 pin47

1
VG17 R0166 C0162
REFB11 REFB19 VGMA19
NC R0168 R0162
C0112

1
B AVDD R0159 B
AVDD_GA

PAD
C0121
C0161
R0163

V3D3
REFB12
Negative Gamma Value REFB21
VG19
VGMA21
R0158
VCOMF2

R0131 R0165
C0160 NC
Close to U103 pin8 C0113

1
PAD
R0164 C0156
R0132
REF13 VG21
REF_F13

32

31

30

29

28

27

26

25
1
PAD R0143
R0133 REFB22 VGMA22
VG1 & VG22 => L255.

REFIN

BANK_SELECT

STD_REG

DVDD

SET

INPCOM/DVROUT

INNCOM

OUTCOM
VG2 & VG21 => L254 C0114

1
PVGMA1 1 24 PVGMA22
OUT1 OUT18
R0134 VG4 & VG19 => L223

PAD
REF15 PVGMA2 PVGMA21
2 23
OUT2 OUT17
PAD
1 REF_F15 VG6 & VG17 => L128 VG22 PVGMA4 PVGMA19
3 22
OUT3 OUT16
R0135 VG8 & VG15 => L32 PVGMA6 PVGMA17
4 21
VG10 & VG13 => L1 OUT4 U101 OUT15
R0136 5 20
REF17
VG11 & VG12 => L0 C0157 GND GND C0159
AVDD_GA 6 19 AVDD_GA
REF_F17 AVDD AVDD
1
PAD
7 18
R0137 V3D3 OUT5 OUT14
SDA_GA SCL_GA 8 17
OUT6 OUT13

OUT10

OUT11

OUT12
OUT7

OUT8

OUT9
U0102 G1

SDA

SCL
R0138 G1
REF19
1 REF_F19 PVGMA13 1 8 VGMA13 1 8

PVGMA10 10

PVGMA11 11

12

13

PVGMA12 14

PVGMA13 15

PVGMA15 16
PAD R0155 R0154 PVGMA12 VGMA12 C0158 VDD VSS R0182 R0183
2 7
A R0139 PVGMA22
NC
VGMA22 PVGMA1
NC
VGMA1 PVGMA11 3 NC 6 VGMA11 2
PA5(HS) PA0(HS)
7 A

PVGMA8
PVGMA10 4 5 VGMA10
3 6
RN102 PA4(HS) PA1(HS)
R0140 4 5
REF21 PA3(HS) PA2(HS)
1 REF_F21
PAD <Variant Name>
PVGMA8 1 8 VGMA8
R0141 PVGMA6 2 7 VGMA6 PVGMA21 1 8 VGMA21
PVGMA4 3 NC 6 VGMA4 PVGMA19 2 7 VGMA19
友達光電電視顯示器產品研發處
NC
1

1
PVGMA2 4 5 VGMA2 PVGMA17 3 6 VGMA17
PVGMA15 4 5 VGMA15
PAD

PAD

PAD

PAD
R0142 RN101 Model Name T315HW02 V3 Tcom MEMC Board
RN103 ISL24813 Programmable Gamma Buffer
REFB22 Gamma
PA5_A

PA4_A

PA3_A

PA2_A
Size Document Number Rev
Custom T315HW02 V3 Tcom\MEMC Board EC02
Date: Wednesday, October 01, 2008 Sheet 1 of 10
5 4 3 2 1
 5 4 3 2 1

T2_lVCLKP

T2_LVCLKN
T2_RVCLKP

T2_RVCLKN
Data Mapping Setting Table

T2_LVP[4..6]

T2_LVP[0..2]
T2_RVP[4..6]

T2_RVP[0..2]

T2_LVN[4..6]

T2_LVN[0..2]
T2_RVN[4..6]

T2_RVN[0..2]
PIX_SFT_EN 0
MODE41 1

T2_LVCLKN
T2_LVCLKP
Closed to pin65 of U401

T2_RVCLKN
T2_RVCLKP
D
FRVS1 0 D

T2_LVN[0..2]
T2_LVP[0..2]
T2_RVN[4..6]

T2_RVN[0..2]
T2_RVP[4..6]

T2_RVP[0..2]

T2_LVN[4..6]
T2_LVP[4..6]
VDD_V3D3_M FRVS2 0

3
RN0401 C0403 C0404
Close to U401 C0402 BRVS 0
CHPXF 0

2
Close to U401

3
RN0400 CHPXB 0
VDD_V1D2_M
CHFB 0
C0406 C0407

2
C0405
CHML 0
For KME use CHRB 1

T2_RVN0

T2_RVN1

T2_RVN2
T2_RVP0

T2_RVP1

T2_RVP2
VDD_V1D2_M

T2_LVN4

T2_LVN5

T2_LVN6

T2_LVN0

T2_LVN1

T2_LVN2
T2_LVP4

T2_LVP5

T2_LVP6

T2_LVP0

T2_LVP1

T2_LVP2
R0402 CHPN 1
VDD_V3D3_M VDD_V3D3_M
VDD_V1D2_M VDD_V1D2_M When ODEN is low or OPEN,
OD_EN(Internal Register )
120HZ
0 : OD disable
U0401 1 : OD enable

G1
R0403

96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
C C0409
NC When ODEN is high, Closed to pin56 of U401 C

RV2N

GND

RV1N

RV0N

LV7N

LV6N

GND

LV5N

LV4N

GND

LVCLKN

LV3N

LV2N

GND

LV1N

LV0N
RV2P

RV1P

RV0P

LV7P

LV6P

LV5P

LV4P

LVCLKP

LV3P

LV2P

LV1P

LV0P
VDDM

VDDM

VDDM
G1

VDDC12
C0408
OD_EN(Internal Register )
0 : OD enable
L0401
97 64 1 : OD disable V3D3
PV3P TEST
98 RV3N SWAPL 63
R0404 99 62
VDDWR GOAEN R0405 VDD_V3D3_M C0430 C0411
100 61 NC
NC 101
PFCAP
RVCLKP
SPDEN
DCREN 60 C0410
102 59 ODEN_M
T2_RVN6 RVCLKN ODEN AGBSEN
103 RV4P AGBSEN 58 AGBSEN
T2_RVP6 104 57 LVDSORD LVDSORD
T2_RVN5 RV4N LVDSORD
L0402 105 RV5P VDDIO 56
V1D2 V1D2 T2_RVP5 106 55
RV5N GND
107 VDDM VDDC12 54
108 GND VSEL 53
C0412 C0414 C0415 T2_RVN4 109 52 XSTB_M XSTB_M
C0413 T2_RVP4 RV6P XSTB
110 51
RV6N XBDO
On Bottom Layer
AUO12401 K1
111 50 XPOL_M XPOL_M
RV7P XPOL YDIO_M
112 RV7N YDIO 49 YDIO_M
R0406 YCLK_M

EPWP_M

VCCE_M

GNDE_M
INSDA_M
113 48

INSCL_M
GND YCLK YCLK_M
114 47 YOE_M YOE_M
GND RMLVDS YOE1
GND 115 VDDIO YOE2 46
R0407 116 45
REXT VDDIO
117 44
118
VDDC12
T2 GND
43 YOE3_M YOE3_M

PAD

PAD

PAD

PAD

PAD
VDD_V1D2_M VDDC12 YOE3 YOE4_M
119 GND YOE4 42 YOE4_M
120 41 YV1C_M YV1C_M
V3D3 VDD_V3D3_M VDDIO YV1C
V3D3 121 40

1
R0408 GND GND
L0403 122 GND VDDC12 39
123 38 RST RST U0402
C0416 C0418 C0419 XIN_M VDDIO RSTN INSDA_M
124 GND INSDA 37 5 SDA GND 4
C0417 1 125 36 INSCL_M 6 SCL 3
PAD OSCSEL_M 126 PWM INSCL EPWP_M A2
B
OSCSEL EPWP 35 7 WP A1 2 B
127 34 EXSDA EXSDA 8 VCC 1
XIN EXSDA A0
RXCLKON
RXCLKOP

RXCLKEN
EXSCL

RXCLKEP
128 33
RXINO0N

RXINO1N

RXINO2N

RXINO3N

RXINO4N
RXINO0P

RXINO0P

RXINO2P

RXINO3P

RXINO4P

RXINE0N

RXINE1N

RXINE2N

RXINE3N

RXINE4N
EXSCL

RXINE0P

RXINE1P

RXINE2P

RXINE3P

RXINE4P
XOUT EXSCL

VDDC12
VDDC12
R0401 R0409 R0410
VDDL

VDDL

VDDL
PAD 1
GND

GND

GND
R0411
XOUT_M
Closed to pin117 of U401 XOUT_M D0401
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD_V3D3_M

GND C0420
VDD_V1D2_M VDD_V1D2_M
Y0401 VDD_V3D3_M VDD_V3D3_M
2

RXINDN0

RXINDN1

RXINDN2

RXINDN3

RXINDN4
RXINBN0

RXINBN1

RXINBN2

RXINBN3

RXINBN4

RXINDP0

RXINDP1

RXINDP2

RXINDP3

RXINDP4
RXINBP0

RXINBP1

RXINBP2

RXINBP3

RXINBP4

C0421 R0412 VDD_V1D2_M

C0422
C0401
C0423
Closed to pin8 of U402
3

R0413 VDD_V3D3_M
RXCLKDN
RXCLKBN

RXCLKDP
RXCLKBP

C0426
RXINDN[0..4]
RXINBN[0..4]

RXINDP[0..4]
RXINBP[0..4]

C0424 C0425
C0427
A A

Closed to pin127 of U401 <Variant Name>

RXCLKBP
RXCLKBN

RXCLKDP
RXCLKDN
RXINBP[0..4]
RXINBN[0..4]

RXINDP[0..4]
RXINDN[0..4]

友達光電電視顯示器產品研發處
Closed to pin33 of U401 Model Name T315HW02 V3 Tcom MEMC Board
Tcom(Master)
Size Document Number Rev
Custom T315HW02 V3 Tcom\MEMC Board EC02
Date: Wednesday, October 01, 2008 Sheet 1 of 10
5 4 3 2 1
 5 4 3 2 1

D D
FRC_IO
05A.FRC_IO
RXINAN0
PI_ODD_RIN0N RX1B_AN RXINAN1
PI_ODD_RIN0N PI_ODD_RIN0N RX1B_BN Power
PI_ODD_RIN1N PI_ODD_RIN1N RXINAN2
PI_ODD_RIN2N PI_ODD_RIN1N RX1B_CN RXINAN3
PI_ODD_RIN2N PI_ODD_RIN2N RX1B_DN
PI_ODD_RIN3N PI_ODD_RIN3N RXINAN4 B12V
PI_ODD_RIN4N PI_ODD_RIN3N RX1B_EN B12V
PI_ODD_RIN4N PI_ODD_RIN4N RXINAN[0..4]
RXINAP0 B3.3VD
PI_ODD_RIN0P RX1B_AP RXINAP1 B3.3VD
PI_ODD_RIN0P PI_ODD_RIN0P RX1B_BP
PI_ODD_RIN1P PI_ODD_RIN1P RXINAP2 VREF
PI_ODD_RIN2P PI_ODD_RIN1P RX1B_CP RXINAP3 VREF
PI_ODD_RIN2P PI_ODD_RIN2P RX1B_DP
PI_ODD_RIN3P PI_ODD_RIN3P RXINAP4 B1.8V_DDR
PI_ODD_RIN4P PI_ODD_RIN3P RX1B_EP B1.8V_DDR GND
PI_ODD_RIN4P PI_ODD_RIN4P RXINAP[0..4]
RXINCLKAN RXINCLKAN
RX1B_CLKN RXINCLKAP
PI_ODD_RINCLKN PI_ODD_RINCLKN RX1B_CLKP RXINCLKAP
PI_ODD_RINCLKP PI_ODD_RINCLKP RXINCN0 05C.FRC_Power
RX3B_AN RXINCN1
FRC_NRESET FRC_NRESET RX3B_BN RXINCN2
RX3B_CN RXINCN3
RX3B_DN RXINCN4
RX3B_EN
C I2C_SCL I2C_SCL RXINCN[0..4] C
RXINCP0
RX3B_AP RXINCP1
I2C_SDA I2C_SDA RX3B_BP RXINCP2
RX3B_CP RXINCP3 DDR
RX3B_DP RXINCP4
HSYNC HSYNC RX3B_EP
RXINCP[0..4]
RXINCLKCN RXINCLKCN B1.8V_DDR
RX3B_CLKN RXINCLKCP B1.8V_DDR
MAIN_CHECK MAIN_CHECK RX3B_CLKP RXINCLKCP
SW_PVCC SW_PVCC RXINBN0
RX2B_AN RXINBN1 VREF
RX2B_BN RXINBN2 VREF GND
PI_EVEN_RIN0N RX2B_CN RXINBN3
PI_EVEN_RIN0N PI_EVEN_RIN0N RX2B_DN
PI_EVEN_RIN1N PI_EVEN_RIN1N RXINBN4
PI_EVEN_RIN2N PI_EVEN_RIN1N RX2B_EN
PI_EVEN_RIN2N PI_EVEN_RIN2N RXINBN[0..4] 05B.FRC_DDR
PI_EVEN_RIN3N PI_EVEN_RIN3N RXINBP0
PI_EVEN_RIN4N PI_EVEN_RIN3N RX2B_AP RXINBP1
PI_EVEN_RIN4N PI_EVEN_RIN4N RX2B_BP RXINBP2
PI_EVEN_RIN0P RX2B_CP RXINBP3
PI_EVEN_RIN0P PI_EVEN_RIN0P RX2B_DP
PI_EVEN_RIN1P PI_EVEN_RIN1P RXINBP4
PI_EVEN_RIN2P PI_EVEN_RIN1P RX2B_EP
PI_EVEN_RIN2P PI_EVEN_RIN2P RXINBP[0..4]
PI_EVEN_RIN3P PI_EVEN_RIN3P RXINCLKBN RXINCLKBN
PI_EVEN_RIN4P PI_EVEN_RIN3P RX2B_CLKN RXINCLKBP
PI_EVEN_RIN4P PI_EVEN_RIN4P RX2B_CLKP RXINCLKBP
B B
PI_EVEN_RINCLKN RXINDN0
PI_EVEN_RINCLKN RX4B_AN RXINDN1
PI_EVEN_RINCLKP PI_EVEN_RINCLKP RX4B_BN RXINDN2
RX4B_CN RXINDN3
RX4B_DN RXINDN4
RX4B_EN
RXINDN[0..4]
RXINDP0
RX4B_AP RXINDP1
RX4B_BP RXINDP2
RX4B_CP RXINDP3
RX4B_DP RXINDP4
B3.3VD

RX4B_EP
RXINDP[0..4]
GND

RXINCLKDN RXINCLKDN
RX4B_CLKN RXINCLKDP
RX4B_CLKP RXINCLKDP

GND B3.3VD

A
<Variant Name> A

友達光電電視顯示器產品研發處
Model Name T315HW02 V3 Tcom MEMC Board
FRC Top
Size Document Number Rev
B T315HW02 V3 Tcom\MEMC Board EC02
Date: Wednesday, October 01, 2008 Sheet 1 of 10
5 4 3 2 1
 5 4 3 2 1

PI_ODD_RIN4P PI_ODD_RIN4P
PI_ODD_RIN4N PI_ODD_RIN4N R619

R611

PI_ODD_RIN3P PI_ODD_RIN3P
PI_ODD_RIN3N PI_ODD_RIN3N

PI_ODD_RIN2P PI_ODD_RIN2P RX1B_CLKN

FRC
PI_ODD_RIN2N PI_ODD_RIN2N R603 RX1B_CLKP
IC500C RX1B_AN
RX1B_AP
R595
D D
RX1B_BN
PI_ODD_RIN1P PI_ODD_RIN1P PI_ODD_RIN4P M1 A16 R501 RX1B_CLKN RX1B_BP
PI_ODD_RIN1N PI_ODD_RIN4N P_ZB_RX4_P P_XA_CLK_N R502 RX1B_CLKP
PI_ODD_RIN1N M2 B16
PI_ODD_RIN3P P_ZB_RX4_N P_XA_CLK_P R503 RX1B_AN
L1 A13 RX1B_CN
PI_ODD_RIN0P PI_ODD_RIN3N P_ZB_RX3_P P_XA_RX0_N R504 RX1B_AP
PI_ODD_RIN0P L2 B13 RX1B_CP
PI_ODD_RIN0N R1 PI_ODD_RIN2P P_ZB_RX3_N P_XA_RX0_P R505 RX1B_BN
PI_ODD_RIN0N J1 A14
PI_ODD_RIN2N J2 P_ZB_RX2_P P_XA_RX1_N B14 R506 RX1B_BP
P_ZB_RX2_N P_XA_RX1_P RX1B_DN
PI_ODD_RIN1P H1 A15 R507 RX1B_CN RX1B_DP
R579 PI_ODD_RIN1N P_ZB_RX1_P P_XA_RX2_N R508 RX1B_CP
H2 B15
PI_ODD_RIN0P P_ZB_RX1_N P_XA_RX2_P R509 RX1B_DN
G1 A17 RX1B_EN
PI_ODD_RIN0N P_ZB_RX0_P P_XA_RX3_N R510 RX1B_DP
PI_ODD_RINCLKP G2 B17 RX1B_EP
PI_ODD_RINCLKP P_ZB_RX0_N P_XA_RX3_P R511 RX1B_EN
PI_ODD_RINCLKN K1 A18
PI_ODD_RINCLKN P_ZB_CLK_P P_XA_RX4_N R512 RX1B_EP
K2 B18 RX2B_CLKN
PI_EVEN_RIN4P PI_EVEN_RIN4P P_ZB_CLK_N P_XA_RX4_P R513 RX2B_CLKN
PI_EVEN_RIN4P F1 B22 RX2B_CLKP
PI_EVEN_RIN4N R618 PI_EVEN_RIN4N P_ZA_RX4_P P_XB_CLK_N R514 RX2B_CLKP
PI_EVEN_RIN4N F2 B21 RX2B_AN
PI_EVEN_RIN3P P_ZA_RX4_N P_XB_CLK_P R515 RX2B_AN
E1 A19 RX2B_AP
PI_EVEN_RIN3N E2 P_ZA_RX3_P P_XB_RX0_N B19 R516 RX2B_AP
R610 PI_EVEN_RIN2P P_ZA_RX3_N P_XB_RX0_P R517 RX2B_BN
C1 A20 RX2B_BN
PI_EVEN_RIN2N P_ZA_RX2_P P_XB_RX1_N R518 RX2B_BP
C2 B20 RX2B_BP
PI_EVEN_RIN3P PI_EVEN_RIN1P P_ZA_RX2_N P_XB_RX1_P R519 RX2B_CN
PI_EVEN_RIN3P B1 A22
PI_EVEN_RIN3N PI_EVEN_RIN1N P_ZA_RX1_P P_XB_RX2_N R520 RX2B_CP
PI_EVEN_RIN3N B2 A21 RX2B_CN
PI_EVEN_RIN0P P_ZA_RX1_N P_XB_RX2_P R521 RX2B_DN
A1 C22 RX2B_CP
PI_EVEN_RIN2P PI_EVEN_RIN0N P_ZA_RX0_P P_XB_RX3_N R522 RX2B_DP
PI_EVEN_RIN2P A2 C21
PI_EVEN_RIN2N R602 PI_EVEN_RINCLKP P_ZA_RX0_N P_XB_RX3_P R523 RX2B_EN
PI_EVEN_RIN2N D1 D22 RX2B_DN
PI_EVEN_RINCLKN P_ZA_CLK_P P_XB_RX4_N U2849 RX2B_EP
D2 D21 RX2B_DP
RX4B_EP R537 P_ZA_CLK_N P_XB_RX4_P R525 RX3B_CLKN
T21 H22
R594 RX4B_EN R538 P_YB_TX4_P P_YA_CLK_N R526 RX3B_CLKP
T22 H21 RX2B_EN
RX4B_DP R539 P_YB_TX4_N P_YA_CLK_P R527 RX3B_AN
R21 E22 RX2B_EP
PI_EVEN_RIN1P RX4B_DN R540 P_YB_TX3_P P_YA_TX0_N R528 RX3B_AP
PI_EVEN_RIN1P R22 E21
PI_EVEN_RIN1N RX4B_CP R541 P_YB_TX3_N P_YA_TX0_P R529 RX3B_BN
PI_EVEN_RIN1N N21 F22 RX3B_CLKN
RX4B_CN R542 P_YB_TX2_P P_YA_TX1_N R530 RX3B_BP
N22 F21 RX3B_CLKP
PI_EVEN_RIN0P RX4B_BP R543 P_YB_TX2_N P_YA_TX1_P R531 RX3B_CN
PI_EVEN_RIN0P M21 G22 RX3B_AN
PI_EVEN_RIN0N R586 RX4B_BN U2850 P_YB_TX1_P P_YA_TX2_N R532 RX3B_CP
PI_EVEN_RIN0N M22 G21 RX3B_AP
RX4B_AP R545 P_YB_TX1_N P_YA_TX2_P R533 RX3B_DN
L21 J22
RX4B_AN R546 P_YB_TX0_P P_YA_TX3_N R534 RX3B_DP
L22 J21 RX3B_BN
R578 RX4B_CLKP R547 P_YB_TX0_N P_YA_TX3_P R535 RX3B_EN
P21 K22 RX3B_BP
RX4B_CLKN R548 P22 P_YB_CLK_P P_YA_TX4_N K21 R536 RX3B_EP
C
P_YB_CLK_N P_YA_TX4_P C
PI_EVEN_RINCLKP RX3B_CN
PI_EVEN_RINCLKN RX3B_CP

RX3B_DN
RX4B_EP RX3B_DP
RX4B_EN
RX3B_EN
RX4B_DP RX3B_EP
RX4B_DN

RX4B_CP
RX4B_CN

RX4B_BP
RX4B_BN
B3.3VD
RX4B_AP
RX4B_AN
B3.3VD B3.3VD

RX4B_CLKP C501
RX4B_CLKN

B3.3VD

CIS R513_DE
IC503
NC

R627
R628
R629
R630

R631
R632
8 1
R5841_DE R5842_DE R584 VCC NC
7 2
EEPROM_SCL WP A1
6 3
NC NC R633 I2C_SDA EEPROM_SDA 5
SCL A2
4
SDA GND

FRC
R524
IC500B R634 I2C_SCL
R635 EEPROM_SDA
B B
R582 A11 N2 R636 EEPROM_SCL
R590 B10 GPIO00 SSDA N1
R598 GPIO01 SSCL R637_DE
A10 M3
R606 B9
GPIO02 MSDA
N3
NC
R614 GPIO03 MSCL R638 HSYNC
A9 A12 HSYNC
R622 GPIO04 V
B8 B11
R583 GPIO05 PWM R639_DE HSYNC
A8 B12
R591 B7
GPIO06 H
A3
NC
T_RST R599 GPIO07 TRST_N R640
A7 A5
MAIN_CHECK R607 GPIO08 TMS
MAIN_CHECK P2 B5
SW_PVCC R642 GPIO09 TDO TP501
SW_PVCC P3 A4 1
R615 GPIO10 TDI PAD
R2 B4
R623 GPIO11 TCLK R641_DE
R3 P1
FRC_NRESET FRC_NRESET B6
GPIO12 XOUT
R1
NC
R644 RESET_N XIN R643
A6
TM
GND
1 TP502
PAD
R585_1 R585
CIS
X501

1 2

B3.3VD B3.3VD

R588

IC589

1 3
GND

/RESET VDD
C586_1 C586
A A
2

<Variant Name>

友達光電電視顯示器產品研發處
Model Name T315HW02 V3 Tcom MEMC Board
FRC IO
Size Document Number Rev
C T315HW02 V3 Tcom\MEMC Board EC02
Date: Wednesday, October 01, 2008 Sheet 1 of 10
5 4 3 2 1
 5 4 3 2 1

L102
TP_B1D05V
GND GND C122_1 CIS
B12V IC104 CIS 1 B1.05V CIS DE
B12V PAD
B3.3VD B3.3VD B1.05V_DLL B3.3V_OSC B3.3VD B2.5V_VDDL_PLL B12V CIS BD108 BD109_DE
B1.8V_DDR B1.8V_DDR CIS R113_2 1 8 NCV1.05VF
VREF BD129 BS SS C130_OP
VREF
2 7 CIS BD2007
IN EN
3 6 R108
C604 C605 C588 C589 C505 C506 C507 C508 C509 C503 C504 SW COMP
CIS CIS CIS CIS CIS CIS CIS CIS CIS CIS CIS

GND
C156 C127 4 5 C145_1 C134 C2728 C2729 C2730 C2731 C2732 C2733 C2734 C2735
GND FB

FRC
CIS
IC500E

MGND1
C129
VREF
D D

1
W12 J7 CIS CIS R119_1
C688 C689 DRAM_VREF VDD105_S C157 C158 R118_1 D105_1
G7 T13
VDD105 VDD105DLL B2.5V_VDDL
G14 H4 NC
VDD105 VDDLZ25PLL

C148_1_OP

C149_1_DE
H7 J4
VDD106 VDDLZ25
H14 K19 CIS CIS CIS CIS

2
VDD105 VDDLY25PLL
J10 M19 C510 C511 C512 C513 C514 C515 C516 C517
VDD105 VDDLY25
J13 H19 C146_1
VDD105 VDDLY25
J14 D14
VDD105 VDDLX25PLL
P14 D16
VDD105 VDDLX25
R7 D12
VDD105 VDDLX25
R14 P4
VDD105 VDD33OSC TP_B3D3V
T7 D8
VDD105 VDD33
T14 D7

PAD
VDD105 VDD33 B1.8V_DDR R157_DE
G8 M4 CIS CIS
VDD105 VDD33 BD120 R113_OP
G15
VDD105 VDD18
P16 CIS CIS CIS CIS CIS CIS
H8 T15 NC CIS B3.3VD CIS B3.3V_OSC

1
VDD105 VDD18 C518 C519 C520 C521 C522
H15 T12 BD2711 BD2713
VDD105 VDD18 B1.05V_MPLL B1.05V_PLL
J8 T8
VDD105 VDD18
J15 P7 CIS CIS L103 CIS
VDD105 VDD18 C122 R114
K9
VDD105 VDD105PLL
R4 CIS
K10 T9 CIS CIS CIS CIS IC110 CIS CIS
VDD105 VDD105 CIS C2788 C2789
K13 T16 C612 C613 C523 C524
VDD105 VDD105 R113_1
K14 R16 1 8
VDD105 VDD105 BS SS C147_OP CIS C145
N9 R9
VDD105 VDD105 R115
N10 P9 2 7
VDD105 VDD105 IN EN
N13 J16
VDD105 VDD105 CIS CIS
N14 J9 3 6
VDD105 VDD105 C159 C120 SW COMP
P8 H16

GND
VDD105 VDD105
P10 H9 CIS 4 5 CIS CIS CIS CIS CIS CIS CIS CIS CIS CIS
VDD105 VDD105 B1.05V GND FB C152 C153 C2736 C2737 C2738 C2739 C2740 C2741 C2742 C2743
P13 G16 C121
VDD105 VDD105 CIS
P15 G9

MGND1
VDD105 VDD105 R118
R8 R15
C VDD105 VDD105 CIS CIS CIS CIS CIS C
CIS CIS CIS CIS CIS

1
C525 C526 C527 C528 C529 C530 C531 C160 U2841 DE CIS
D105 CIS CIS R119
CIS NC
C148_OP C149_DE
C146

FRC

2
IC500D

CIS 47NF/10%/16V/X7R/0603
C5 W19
VSS VSS CIS CIS CIS CIS CIS
C6 W18 CIS CIS
VSS VSS
C7 W17
VSS VSS C536 C537 C539 C541 C542 C543 C544
C8 W16
VSS VSS B2.5V_VDDL
C9
VSS VSS
W15 CIS
C10 W14 TP_B2D5V L116
VSS VSS
C11 W13

PAD
VSS VSS B3.3VD
C12 W11
VSS VSS
C13 W10 CIS 10NF/10%/50V/X7R/0603 CIS CIS CIS
VSS VSS IC102 U2842 C108
C14 W9

1
VSS VSS
C15 W8
VSS VSS
C16 W4 1 3

GND
VSS VSS Vin Vout
C17
VSS VSS
V19 CIS CIS CIS CIS CIS CIS CIS
C18 V4 CIS
VSS VSS U501 C538 C540 U502 U503 U504 U505 C112 B2.5V_VDDL_PLL
C19 U22 CIS

2
VSS VSS L117
C20 U20
VSS VSS
D3 U19
VSS VSS
D4 U4
VSS VSS
D5 U3 CIS CIS
VSS VSS C163 C183
D6
VSS VSS
U2 CISBD160 B1.05V_MPLL
D9
VSS VSS
T20 CIS 100NF/10%/16V/X7R/0603
D10 T19
VSS VSS
D11
VSS VSS
T11 CIS CIS
B D13 T10 C161 C162 B
VSS VSS105MPLL B1.05V
D15 T4
VSS VSS105PLL
D17 T3
VSS VSS CIS
D18 T2 CIS CIS CIS
VSS VSS
D19 R20
VSS VSS C532 C533 C534 C535 B3.3VD
D20 R19 CIS
VSS VSS L111 IC109
E3
VSS VSS
R13 CISBD163 B1.05V_DLL
E4 R12 1 5 V1.05VF
VSS VSS IN OUT
E19 R11 CIS
VSS VSS CIS
E20
VSS VSS
R10 CIS CIS CIS 2
GND
CIS CIS
F3 P20 C195 C194 C191 C196_1 C196 CIS CIS R137 C164 C165
VSS VSS C125 R140 C192_2 CIS
F4 P19 3 4
VSS VSS /EN FB C190 C190_1 C190_2
F19 P12
VSS VSS
F20 P11
VSS VSS
G3 N20
VSS VSS
G4 N19
VSS VSS
G10
VSS VSS
N16 CIS CIS CISBD2712 B1.05V_PLL
G11 N15 R125 CIS C192
VSS VSS R141
G12 N12
VSS VSS
G13
VSS VSS
N11 CIS CIS
G19 N8 C189 C2748
VSS VSS
G20 N7

1
VSS VSS
H3 N4
VSS VSS33OSC
H10 M20

PAD
VSS VSS
H11 M16
VSS VSS TP_B1D8V
H12 M15
VSS VSS
H13 M14

PAD
VSS VSS TP_B1D05V_PLL
H20 M13
VSS VSS B3.3VD CIS
J3 M12
VSS VSS IC107 CIS B1.8V_DDR
J11 M11

1
VSS VSS L112
J12 M10
VSS VSS
J19 M9 3 2
VSS VSS Vin Vout

ADJ
J20 M8
VSS VSS R142 R138
A K3 M7 A
VSS VSS
K4 L20 CIS CIS CIS

1
VSS VSS R139 CIS
K7 L19
VSS105_S VSS CIS C101
K8
VSS VSS
L16 CIS
K11 L15 CIS C103 C102 <Variant Name>
VSS VSS C109
K12 L14
VSS VSS
K15 L13
VSS VSS C014 C105
K16
K20
VSS VSS
L12
L11 R143
CIS
CIS CIS 友達光電電視顯示器產品研發處
VSS VSS
L3 L10
VSS VSS Model Name T315HW02 V3 Tcom MEMC Board
L4 L9
VSS VSS
L7
VSS VSS
L8 FRC Power
Size Document Number Rev
Custom T315HW02 V3 Tcom\MEMC Board EC02
Date: Wednesday, October 01, 2008 Sheet 1 of 10
5 4 3 2 1
 5 4 3 2 1

FRCD_DQS0_N

FRCD_DQS0_P
FRC_DQ10

FRC_DQ13

FRC_DM0
FRC_DQ6

FRC_DQ7

FRC_DQ1

FRC_DQ0
FRC
B1.8V_DDR
IC500A VTT_FRC

FRCD_ADDR[0..12]
FRCD_ADDR0 AA9 W7
FRCD_ADDR1 DRAM_A0 DRAM_TEST_D2 [MDSD32M16B]
AB8 W6
FRCD_ADDR10 DRAM_A1 DRAM_TEST_D1
AA15 W5
DRAM_A10 DRAM_TEST_ANALOG IC301

G1
G2
G3
G7
G8
G9
FRCD_ADDR11 FRCD_NWE

D7
D8
D9
E1
E2
E3
E7
E8
E9
AA16 AA13

F1
F2
F3
F7
F8
F9
FRCD_ADDR12 DRAM_A11 DRAM_WE_N FRCD_NRAS
Y16 AB14
FRCD_ADDR2 DRAM_A12 DRAM_RAS_N FRCD_ODT
AA8 AA12

LDM
/LDQS

LDQS
DQ10

DQ13

NC5

DQ6

DQ7

DQ1

DQ0
[VSSQ]

[VDD]

[VSS]
[VSSQ]

[VDDQ]

[VSSQ]

[VSSQ]

[VDDQ]

[VDDQ]
[VDDQ]

[VDDQ]
DRAM_A2 DRAM_ODT

R318
R319
R320
R321
R322
R323
R324
R317

R325

R326
FRCD_ADDR3 Y9 AB4 FRCD_DQS3_N
FRCD_ADDR4 DRAM_A3 DRAM_DQS3_N FRCD_DQS3_P
Y8 AA4
FRCD_ADDR5 DRAM_A4 DRAM_DQS3 FRCD_DQS2_N
AA7 AA3
FRCD_ADDR6 DRAM_A5 DRAM_DQS2_N FRCD_DQS2_P
Y7 Y3
FRCD_ADDR7 DRAM_A6 DRAM_DQS2 FRCD_DQS1_N FRC_DQ11 FRC_DQ4
AA14 AA22 D3 H1
D
FRCD_ADDR8 DRAM_A7 DRAM_DQS1_N FRCD_DQS1_P DQ11 DQ4 D
Y14 AB22 D2 H2
FRCD_ADDR9 DRAM_A8 DRAM_DQS1 FRCD_DQS0_N FRC_DQ12 [VSSQ] [VSSQ] FRC_DQ3
Y15 AA21 D1 H3
FRCD_BA0 DRAM_A9 DRAM_DQS0_N FRCD_DQS0_P DQ12 DQ3 FRC_DQ2
AA11 AB20 C9 H7
FRCD_BA1 DRAM_BA0 DRAM_DQS0 FRC_DQ9 FRC_DQ8 [VDDQ] DQ2
Y11 AA18 C8 H8 B1.8V_DDR
FRCD_BA2 DRAM_BA1 DRAM_DQ9 FRC_DQ8 DQ8 [VSSQ] FRC_DQ5 BD508
Y10 W20 C7 H9
FRCD_NCAS DRAM_BA2 DRAM_DQ8 FRC_DQ7 [VDDQ] DQ5
Y13 W22 C3 J1
FRCD_CLK DRAM_CAS_N DRAM_DQ7 FRC_DQ6 FRC_DQ9 [VDDQ] [VDDL] VREF
AA10 AA17 C2 J2
FRCD_NCLK DRAM_CK DRAM_DQ6 FRC_DQ5 DQ9 [VREF] C301 C771
AB10 U21 C1 J3
FRCD_CLKE DRAM_CK_N DRAM_DQ5 FRC_DQ4 FRC_DQ15 [VDDQ] [VSS] C302 C773 C313 C314 C316 C317 C319
Y12 AB16 B9 J7
FRCD_NCS DRAM_CKE DRAM_DQ4 FRC_DQ31 DQ15 [VSSDL] FRCD_CLK
AB12 AA5 B8 J8
FRC_DM0 DRAM_CS_N DRAM_DQ31 FRC_DQ30 FRCD_DQS1_P [VSSQ] CK
Y20 Y1 B7 J9
FRC_DM1 DRAM_DM0 DRAM_DQ30 FRC_DQ3 FRC_DM1 UDQS [VDD] FRCD_CLKE
Y19 AA20 B3 K2
FRC_DM2 DRAM_DM1 DRAM_DQ3 FRC_DQ29 UDM CKE FRCD_NWE
AB1 Y6 B2 K3
FRC_DM3 DRAM_DM2 DRAM_DQ29 FRC_DQ28 FRC_DQ14 [VSSQ] /WE FRCD_NRAS
Y2 W1 B1 K7
FRC_DQ[0..31] FRC_DQ0 DRAM_DM3 DRAM_DQ28 FRC_DQ27 DQ14 /RAS FRCD_NCLK
V20 AA1 A9 K8
FRC_DQ1 DRAM_DQ0 DRAM_DQ27 FRC_DQ26 FRCD_DQS1_N [VDDQ] /CK FRCD_ODT
Y17 Y4 A8 K9
FRC_DQ10 DRAM_DQ1 DRAM_DQ26 FRC_DQ25 /UDQS ODT FRCD_BA2
AB21 W2 A7 L1
FRC_DQ11 DRAM_DQ10 DRAM_DQ25 FRC_DQ24 [VSSQ] BA2 FRCD_BA0
AA19 Y5 A3 L2
FRC_DQ12 DRAM_DQ11 DRAM_DQ24 FRC_DQ23 [VSS] BA0 FRCD_BA1
Y18 AA6 A2 L3
FRC_DQ13 DRAM_DQ12 DRAM_DQ23 FRC_DQ22 NC4 BA1 FRCD_NCAS
W21 W3 A1 L7
FRC_DQ14 DRAM_DQ13 DRAM_DQ22 FRC_DQ21 [VDD] /CAS
AB18 AB6
FRC_DQ15 DRAM_DQ14 DRAM_DQ21 FRC_DQ20
Y21 U1
FRC_DQ16 DRAM_DQ15 DRAM_DQ20 FRC_DQ2 C325 C327 C329 C331 C332 C335
AB2 V21

A10/AP
DRAM_DQ16 DRAM_DQ2

[VDD]

[VDD]
FRC_DQ17 FRC_DQ19

[VSS]

[VSS]
V2 V3

NC1
NC3
NC2
DRAM_DQ17 DRAM_DQ19

A12

A11

/CS
FRC_DQ18 AA2 VTT_FRC

A8

A9
A7
A4
A6
A5
A3

A0
A2
A1
DRAM_DQ18
R357

R8
R7
R3
R2
R1
P9
P8
P7
P3
P2
N8
N7
N3
N2
N1
M9
M8
M7
M3
M2
L8
R372_DE
NC

R358
R359
R360
R361
R362
R363
R364
R365
R366
R367
R368
R369
R370
R371
FRCD_NCS C344 C341 C340
FRCD_ADDR10
C FRCD_ADDR1 C
FRCD_ADDR2
FRCD_ADDR0
FRCD_ADDR3
FRCD_ADDR5
FRCD_ADDR6
FRCD_ADDR4
FRCD_ADDR7
FRCD_ADDR9
FRCD_ADDR11
FRCD_ADDR8
FRCD_ADDR12
B1.8V_DDR FRCD_ADDR[0..12]

VREF VTT_FRC

R387
R388
IC108 R389
R390
1 8 R391
NC VTT

R386
R385
R384
R383
R382
R381
R380
R379
R378
R377
R376
R375
R374
R373
2 7
VTT_FRC GND PVIN B1.8V_DDR
3 6
VSENSE AVIN
4 5
VREF VDDQ VTT_FRC
C306 C307 C759 C760 C761 C762 C763 C169 C170 C167 C168 U2839 U2840 VTT_FRC BD509

C772
C348 C349 C351 C352 C354

M9
M8
M7
M3
M2
R8
R7
R3
R2
R1

N8
N7
N3
N2
N1
P9
P8
P7
P3
P2

L8
A10/AP
/CS
NC1
NC3
NC2
A12

A8
A11
A9
A7
A4
A6
A5
A3

A0
A2
A1
[VDD]
[VSS]

[VSS]
[VDD]
GND

R398
R399
R397
R394
R395
A1 L7
[VDD] /CAS
A2 L3
B
C305 C304 C303 C764 C765 C766 C767 NC4 BA1 B
A3 L2
[VSS] BA0 FRCD_BA2
A7 L1
FRCD_DQS3_N [VSSQ] BA2
A8 K9
/UDQS ODT
A9 K8
FRC_DQ30 [VDDQ] /CK
B1 K7
DQ14 /RAS C360 C362 C364 C366 C368 C370
B2 K3
FRC_DM3 [VSSQ] /WE
B3 K2
FRCD_DQS3_P UDM CKE
B7 J9
UDQS [VDD]
B8 J8
FRC_DQ31 [VSSQ] CK C308
B9 J7
DQ15 [VSSDL] C309
C1 J3
FRC_DQ25 [VDDQ] [VSS] VREF
C2 J2
DQ9 [VREF]
C3 J1
[VDDQ] [VDDL] FRC_DQ21
C7 H9
FRC_DQ24 [VDDQ] DQ5
C8 H8
DQ8 [VSSQ] FRC_DQ18
C9 H7
FRC_DQ28 [VDDQ] DQ2 FRC_DQ19
D1 H3
DQ12 DQ3
D2 H2
FRC_DQ27 [VSSQ] [VSSQ] FRC_DQ20
D3 H1
DQ11 DQ4 C379 C375
C376
[VDDQ]

[VDDQ]

[VDDQ]
[VDDQ]

[VDDQ]
[VSSQ]

[VSSQ]

[VSSQ]

[VSSQ]
/LDQS

LDQS
[VDD]
DQ10

DQ13

[VSS]

LDM
DQ6

DQ7

DQ1

DQ0
NC5
D7
D8
D9
E1
E2
E3
E7
E8
E9
F1
F2
F3
F7
F8
F9
G1
G2
G3
G7
G8
G9

IC302
[MDSD32M16B]

FRCD_DQS2_N
FRC_DM2
FRC_DQ26
FRC_DQ29
FRC_DQ22
FRCD_DQS2_P
FRC_DQ23
A FRC_DQ17 A
FRC_DQ16

CIS

<Variant Name>

友達光電電視顯示器產品研發處
Model Name T315HW02 V3 Tcom MEMC Board
FRC DDR
Size Document Number Rev
Custom T315HW02 V3 Tcom\MEMC Board EC02
Date: Wednesday, October 01, 2008 Sheet 1 of 10
5 4 3 2 1
 5 4 3 2 1

T1_lVCLKP

T1_LVCLKN
T1_RVCLKP

T1_RVCLKN
Data Mapping Setting Table

T1_LVP[4..6]

T1_LVP[0..2]
T1_RVP[4..6]

T1_RVP[0..2]
T1_RVN[4..6]

T1_RVN[0..2]

T1_LVN[4..6]

T1_LVN[0..2]
PIX_SFT_EN 0

T1_LVCLKN
T1_LVCLKP
MODE41 1
Closed to pin65 of U300

T1_RVCLKN
T1_RVCLKP
FRVS1 0

T1_LVN[0..2]
T1_LVP[0..2]
D D

T1_RVN[4..6]

T1_RVN[0..2]
T1_RVP[4..6]

T1_RVP[0..2]

T1_LVN[4..6]
T1_LVP[4..6]
VDD_V3D3_S FRVS2 0

3
RN0301 C0322 C0323
Close to U300 C0321 BRVS 0
CHPXF 0

2
4

3
RN0300
Close to U300
CHPXB 0
VDD_V1D2_S
CHFB 0

2
C0325 C0326
C0324
CHML 0
For KME use CHRB 1

T1_RVN0

T1_RVN1

T1_RVN2
T1_RVP0

T1_RVP1

T1_RVP2
VDD_V1D2_S

T1_LVN4

T1_LVN5

T1_LVN6

T1_LVN0

T1_LVN1

T1_LVN2
T1_LVP4

T1_LVP5

T1_LVP6

T1_LVP0

T1_LVP1

T1_LVP2
R0310 CHPN 1
VDD_V3D3_S VDD_V3D3_S
VDD_V1D2_S VDD_V1D2_S When ODEN is low or OPEN, 120HZ
OD_EN(Internal Register )
0 : OD disable
1 : OD enable

G1
R0309

96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
C
C0328
NC When ODEN is high, Closed to pin56 of U300 C

RV2N

GND

RV1N

RV0N

LV7N

LV6N

GND

LV5N

LV4N

GND

LVCLKN

LV3N

LV2N

GND

LV1N

LV0N
RV2P

RV1P

RV0P

LV7P

LV6P

LV5P

LV4P

LVCLKP

LV3P

LV2P

LV1P

LV0P
VDDM

VDDM

VDDM
G1

VDDC12
C0327
OD_EN(Internal Register )
0 : OD enable
L0301
97 64 1 : OD disable V3D3
PV3P TEST
98 RV3N SWAPL 63
R0311 99 62
VDDWR GOAEN R0308
NC 100
101
PFCAP SPDEN 61
60
NC VDD_V3D3_S C0330
C0319
C0320
RVCLKP DCREN ODEN_S
102 RVCLKN ODEN 59
T1_RVN6 103 58 AGBSEN

L0300
T1_RVP6
T1_RVN5
104
105
RV4P
RV4N
RV5P
U0300 AGBSEN
LVDSORD
VDDIO
57
56
LVDSORD
AGBSEN
LVDSORD

V1D2 V1D2 T1_RVP5 106 55

RV5N GND
107 VDDM VDDC12 54
108 GND VSEL 53
C0301 C0303 C0304 T1_RVN4 109 52 XSTB_S XSTB_S
C0302 T1_RVP4 RV6P XSTB
110 51
RV6N XBDO
On Bottom Layer
AUO12401 K1
111 50 XPOL_S XPOL_S
RV7P XPOL YDIO_S
112 RV7N YDIO 49 YDIO_S
R0312 113 48 YCLK_S YCLK_S
GND YCLK YOE_S

EPWP_S

VCCE_S

GNDE_S
114 47

INSDA_S

INSCL_S
RMLVDS YOE1 YOE_S
GND GND 115 46
R0313 VDDIO YOE2
116 REXT VDDIO 45
117 44
118
VDDC12
T1 GND
43 YOE3_S YOE3_S

PAD

PAD

PAD

PAD

PAD
VDD_V1D2_S VDDC12 YOE3 YOE4_S
119 GND YOE4 42 YOE4_S
120 41 YV1C_S YV1C_S
L0302 VDDIO YV1C
V3D3 V3D3 VDD_V3D3_S 121 40

1
R0342 GND GND
122 GND VDDC12 39
123 38 RST RST U0301
C0305 C0307 C0308 VDDIO RSTN INSDA_S
PAD 1 124 GND INSDA 37 5 SDA GND 4
C0306 XIN_S 125 36 INSCL_S 6 SCL 3
OSCSEL_S 126 PWM INSCL EPWP_S A2
XIN_S OSCSEL EPWP 35 7 WP A1 2
B 127 34 EXSDA EXSDA 8 VCC 1 B
XIN EXSDA A0
RXCLKON
RXCLKOP

RXCLKEN
EXSCL

RXCLKEP
128 33
RXINO0N

RXINO1N

RXINO2N

RXINO3N

RXINO4N
RXINO0P

RXINO0P

RXINO2P

RXINO3P

RXINO4P

RXINE0N

RXINE1N

RXINE2N

RXINE3N

RXINE4N
RXINE0P

RXINE1P

RXINE2P

RXINE3P

RXINE4P
XOUT EXSCL EXSCL

VDDC12
VDDC12
R0303 R0304 R0305
VDDL

VDDL

VDDL
1
GND

GND

GND
PAD R0306
XOUT_S
Closed to pin117 of U300 D0300
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD_V3D3_S

GND C0317
VDD_V1D2_S VDD_V1D2_S
NC
Y0301 VDD_V3D3_S VDD_V3D3_S
2

RXINCN0

RXINCN1

RXINCN2

RXINCN3

RXINCN4
RXINAN0

RXINAN1

RXINAN2

RXINAN3

RXINAN4

RXINCP0

RXINCP1

RXINCP2

RXINCP3

RXINCP4
RXINAP0

RXINAP1

RXINAP2

RXINAP3

RXINAP4

C0309 R0301 VDD_V1D2_S

NC NC C0312
C0311
C0313
Closed to pin8 of U301
3

R0302 VDD_V3D3_S
NC
RXCLKCN
RXCLKAN

RXCLKCP
RXCLKAP

C0315
RXINCN[0..4]
RXINAN[0..4]

RXINCP[0..4]
RXINAP[0..4]

C0310 C0314
C0316
NC
A A

Closed to pin127 of U300 <Variant Name>

RXCLKAP
RXCLKAN

RXCLKCP
RXCLKCN
RXINAP[0..4]
RXINAN[0..4]

RXINCP[0..4]
RXINCN[0..4]

Closed to pin33 of U300 友達光電電視顯示器產品研發處

Model Name T315HW02 V3 Tcom MEMC Board
Tcom(Slave)
Size Document Number Rev
Custom T315HW02 V3 Tcom\MEMC Board EC02
Date: Wednesday, October 01, 2008 Sheet 1 of 10
5 4 3 2 1