ET8017

Electronic Instrumentation

HW 6

by

Dali ZHANG 4219058

2013/10/22

Student Number: 4219058 Name: Dali Zhang

ET8017 Electronic Instrumentation HW 6

Page 1 of 3 2013/10/22

1.

Vo1 Vo2

Fig.1

As shown in Fig. 1, in sampling phase , output of offset voltage is stored in C1 and C2 . In amplifying phase , charge injection will happen. Performance of the system depends on load capacitance. Assume that C1 = C2 = C, for worst case, that is when all injection charge goes into the capacitors, residual offset will be Q inj 1 Q inj 2 0.1Q inj C C2 Vos ,res = 1 20 V A1 A1 C with Q inj = 100 pC A1 = 2000 So C 0.25 nF Only consider residual offset caused by off-resistance. Assume that input resistance of the next stage is , which means all charge will go to ground through the off-resistance. For simplicity, assume that input voltage is constant in amplifying phase. Vin Vos Q1 (t) Vo1 (t) = AVcm A A + 2 2 C1 Vin Vos Q 2 (t) Vo2 (t) = AVcm + A +A 2 2 C2 with t Vos C1 Vo1 (t) Q1 (t) = A + dt 2 0 R off t Vos C2 Vo2 (t) Q2 t = A dt 2 0 R off which yields t 1 Vout t = A[Vin + Vos ,res ,r t ] = Vo2 t Vo1 t = AVin + V (t)dt R off C 0 out with the initial condition that Vos ,res ,r 0 = 0, we have Vos ,res ,r t = Vin eR off C 1
t

20 V

t R off C ln (1 +

20 V ) Vin

Assume that input voltage is 1 V, we have t < 50 ns Finally we have auto zeroing should take place less than every 50 ns s or with a frequency higher than 20 MHz.

Student Number: 4219058 Name: Dali Zhang

ET8017 Electronic Instrumentation HW 6

Page 2 of 3 2013/10/22

2.

Fig. 2

As shown in Fig. 2, in sampling phase , output of offset voltage is stored in Caz . In amplifying phase , charge injection will happen at S2. For an ideal amplifier, which means all injection charge goes into the capacitors, residual offset will be Q inj Vos Vos ,res = + 20 V Caz A + 1 with Q inj = 100 pC So C 10 F Only consider residual offset caused by off-resistance. The circuit turns out to be an opamp circuit with negative feedback. For simplicity, assume that input voltage is constant in amplifying phase. Vout t = A Vin + Vos ,res ,r t t Vout V t Vout Vin Vos ,res ,r dt dt A 1 t 0 0 R R Vos ,res ,r t = = = V + Vos ,res ,r dt C C RC 0 in with the initial condition that Vos ,res ,r 0 = 0, we have Vos ,res ,r t t = Vin e RC t 1
A 1

20 V

RC 20 V ln (1 + ) A1 Vin Assume that input voltage is 1 V, residual offset voltage will be t 500 ns Finally we have auto zeroing should take place at least every 500 ns s or 2 MHz.

3.
As shown in Fig. 2, let's assume that the amplifier and all switches are ideal. In sampling phase, output voltage of the amplifier or the voltage across the auto-zeroing capacitor will be Vos, synchronously. In amplifying phase, offset voltage will go on increase, while no charge will be available for the auto-zeroing capacitor. So residual input offset will be the same as the mismatch between offset voltage and the voltage across Caz. Worst case will happen just at the end of amplifying phase, it will be 0.5 Vos (t) Vos (t) Vos ,res = 10 mv/s + = 5 v + f A+1 A+1 For circuit shown in Fig. 1, Vos ,res = 5 v

Student Number: 4219058 Name: Dali Zhang

ET8017 Electronic Instrumentation HW 6

Page 3 of 3 2013/10/22

4.

Fig. 3

Accuracy of three signal method is limited by ADC resolution and noise. For this assignment, we don't know the noise level. So we can assume that noise, except for quantization noise, is zero. Quantization noise will not be more than 1 LSB. So accuracy of the system is limited by ADC resolution only. It is known that ADC resolution is Vref ,ADC 1 R ADC = = 20 0.954 V 20 2 2 which is also the uncertainty of the system. For three-signal method, we have V1 = A(Vos + Vin ) V2 = A(Vos + Vref ) V3 = AVos For highest accuracy, assume that uncertainties of Vin and Vref are neglectable. For simplicity, assume that Vin = 1, Vref = 0 V, we have V1 V2 A= = V1 V2 Vin Vref V3 V3 Vos = V Vref = V1 V2 in V1 V2 Uncertainty of V1 , V2 , and V3 are 0.5R ADC , results are uniformly distributed. So uncertainty of gain A will be 2R ADC A = 1.91 V Vin Vref Uncertainty of offset voltage will be Vos Vos Vos 1 2Vos Vos = R ADC + + (Vin Vref ) = R ADC ( + )(Vin Vref ) V1 V2 V3 A A which is not able to find an exact number with current conditions. (Assignment 4 is a little bit strange. Given reference voltage of the ADC 1 V, how can the input range be -1~+1 V? With some range useless? Or with something else that can detect >0 & <0?)