17th Telecommunications forum TELFOR 2009 Serbia, Belgrade, November 24-26, 2009.

Abstract Broadband Wireless Access (BWA) is a

promising technology which can offer high speed voice, video
and internet connection. The leading candidate for BWA is
WiMAX, a technology that complies with the IEEE 802.16
family of standards. This paper is focused towards the
hardware Implementation of WirelessMAN-OFDM Physical
Layer of IEEE Std 802.16d Transmitter on FPGA. The RTL
coding style of Verilog HDL was used which gave a high level
design-flow for developing and validating communication
system protocols and provides flexibility of modifications in
future in order to meet real world performance evaluation.
The proposed design is fully supportive to adaptive
modulation schemes described in IEEE Std 802.16d and
equipped with soft interfaces for MAC layer and RF-front
end, so that in future more work could be done in order to
deploy complete WiMAX CPE IP core.
Keywords WiMAX, IEEE Std 802.16d, OFDM, PHY
Layer.
I. INTRODUCTION
his paper elaborates the hardware design strategies to
model OFDM baseband Transmitter PHY of IEEE Std
802.16d,approved by IEEE-Standards Association on June
24, 2004 to consolidate IEEE Std 802.16-2001, IEEE Std
802.16a-2003, and IEEE Std 802.16c-2002 [1]. The
revised system aims on describing MAC and multiple
physical layer specifications of fixed BWA systems [2].
WiMAX is the name given to the products based on IEEE
Std 802.16 protocol. The arrival of the WiMAX has made
long-range wireless network communication (up to 40km)
a reality. Its high-speed voice, video and data services
become an alternative to 3G [3], and compromise between
high speed data transmission and mobility was achieved
This paper covers the OFDM PHY details and its
architectural view to model a real-time hardware. The text
is fully supportive to adaptive modulation and coding
schemes described in the OFDM WiMAX standard with
channel bandwidth selection of 1.75, 3.5, 7 and 14 MHz
and CP time of 16 samples. The minimum and maximum
data rates achieved with these specs were 5.64 Mbps and
50.82 Mbps respectively which require a maximum of
6.55 MHz clock for processing. Altera Cyclone II
EP2C35F672C6 FPGA chip on DE2 Development kit was
used for the purpose of hardware synthesis.

Shahid Abbas, Waqas Ali khan and Talha Ali Khan are the students of
Final Year in Department of Electronic Engineering, NED University of
Engineering and Technology, Karachi- 75270, Pakistan, (email:
shahid.nedian@hotmail.com, waqas035@hotmail.com,
talha080@hotmail.com ).
Saba Ahmed is Assistant Professor in Telecommunications
Department, NED University of Engineering and Technology, Karachi-
75270, Pakistan, (email: sabaa@neduet.edu.pk ).

This document grasps an overview of OFDM PHY
compliant IEEE Std 802.16d and its FPGA
implementation under section II. Section III provides data
rate calculations, required system clock and hardware
synthesis results.
II. WIMAX OFDM PHY & FPGA IMPLEMENTATION
The OFDM PHY of IEEE 802.16d basically consists of
three processes namely channel coding, modulation and
OFDM as shown in Fig. 1. Each of these comprises of
certain internal processes depending upon specific coding
schemes. This sequence of steps is employed at transmitter
while they are applied in the reverse order at reception [4].
Fig. 1. PHY Processing Sequence [1].
A. Channel Coding
It is a set of processes by which one can make the
signal secure while transmitting through a physical
channel. In the proposed design, channel coding typically
comprises of three steps [1] as shown in Fig. 2.
1) Data Scrambling
A 15-bit PRBS generator having polynomial, 1+ x
14
+
x
15
was implemented to produce scrambled data bits. The
seed value shown in Fig. 3 shall be used to calculate the
scrambled bits [1]. The DIUC value is simply the Rate ID
values as mentioned in table 224 of section 8.3.3.4.3 of
IEEE Std 802.16d.
FPGA implementation of scrambler is capable of
performing scrambling of 8-bits at a time, making system
to work faster 7 times with no extra hardware as the next
state of LFSR register was defined by the XORed shifting
of LSBs to eight MSBs position. Hardware architecture is
given in Fig. 4, showing I/O interfaces of the module.
OFDM Baseband Transmitter Implementation
Compliant IEEE Std 802.16d on FPGA
Shahid Abbas, Studend Member, IEEE, Waqas Ali Khan, Talha Ali Khan and Saba Ahmed
T
Fig. 2. Channel Coding [5].
Fig. 3. Scrambler Downlink Initialization Vector [1].
141

Fig. 4. Architecture of Scrambler.
2) FEC
It is the process employed to detect and correct errors
without retransmission [6]. For OFDM PHY, the FEC is
accomplished by the concatenation of Reed-Solomon outer
code and a rate compatible Convolution inner code shown
in Fig. 5. WiMAX supports adaptive PHY, hence different
modulation and coding schemes could be employed
depending upon channel conditions [7], details of whose
are given in table 1.


a) Reed-Solomon Coding
RS-Encoding is specified by adding parity symbols to
the original data packet. If data packet contains k-symbols
each of m-bit(s) then encoded version is determined by
RS(n,k,t), with n is length of coded block and t is the
maximum number of symbols that can be corrected. RS-
Encoding governs the relations (1), (2) and (3) [8];
n = 2
m
1 (1)
k = 2
m
-1 - 2t (2)
t = (n - k)2 (3)
In the proposed design, RS-code shall be derived from
a systematic RS (N = 255, K = 239, T = 8) code using GF
(2
8
), primitive and generator polynomial depicted in (4)
and (5) respectively [1].
p(x) = x
8
+ x
4
+ x
3
+x
2
+ 1 (4)
g(x) = (x +
0
)(x +
1
). . . (x +
21-1
); = u2 Ecx (5)
In this project the RS-encoder was generated using
Altera Quartus-II 9.0 mega function wizard and was
wrapped in a top-level file to introduce variable coding
rates depicted in table 1 The I/O data path is 8-bit wide.
The numcheck signal specifies the desired number of
parity symbols. The operation is completed in minimum
14 and maximum 124 clock cycles. The high-level
hardware design is shown in Fig. 6.
b) Convolutional Encoding
In OFDM PHY, each RS encoded data is further
encoded by convolutional encoder with a native rate of
1/2, a constraint length equal to 7. The output code bits are
generated by generator polynomial defined in (6) and (7);

0
1
= 171
oct
F0R X (6)

0
1
= 1SS
oct
F0R (7)

Four coding rates are given in table 1, which are
achieved by puncturing patterns given in table 2 hence
four convolutional encoders were implemented, each
having input data path 8, 16, 24 and 40 bits.
TABLE 2. PUNCTURING PATTERNS FOR CC-CODE RATES [1].

CC-Code Rates
Rate 1/2 2/3 3/4 5/6
X 1 10 101 10101
Y 1 11 110 11010
XY X
1
Y
1
X
1
Y
1
Y
2
X
1
Y
1
Y
2
X
3
X
1
Y
1
Y
2
X
3
Y
4
X
5

These four encoders were enclosed in a top-level file,
contain input and output data buffers and selects only one
encoder at a time indicated by rate_id input. The input data
path is 8-bit while output is 48-bit wide. The whole
process takes at least 16 and at most 244 clocks. The
hardware view is shown in Fig. 7.

TABLE 1. MANDATORY CHANNEL CODING PER MODULATION [1].
Modulation
Un-coded block
size (bytes)
Coded block
Size (bytes)
Overall rate RS-Code CC Code rate
BPSK 12 24 1/2 (12,12,0) 1/2
QPSK 24 48 1/2 (32,24,4) 2/3
QPSK 36 48 3/4 (40,36,2) 5/6
16-QAM 48 96 1/2 (64,48,8) 2/3
16-QAM 72 96 3/4 (80,72,4) 5/6
64-QAM 96 144 2/3 (108,96,6) 3/4
64-QAM 108 144 3/4 (120,108,6) 5/6
Fig. 5. OFDM PHY FEC Scheme [5].
Fig. 6. Reed-Solomon Top-Level Module Design.
Fig. 7. Convolutional-Encoder Top-Level Module
142

3) Interleaving
Let N
cpc
be the number of coded bits per subcarrier,
i.e., 1, 2, 4 or 6 for BPSK, QPSK, 16-QAM, or 64-QAM
respectively. Let s = ccil (N
cpc
2). Within a block of
N
cbps
bits at transmission, let k be the index of the coded
bit before the first permutation; m
k
be the index of that
coded bit after the first and before the second permutation
and let [
k
be the index after the second permutation. The
first and second permutation is defined by (8) and (9)
respectively;
m
k
= [
N
cbps
12
. k
mod12
+loor(
k
12
) (8)
[
k
= s. loor [
m
k
s
+(m
k
+N
cbps
- loor(
12.m
k
N
cbps
))
mod(s)
(9)

Where N
cbps
= 192, 384, 768 and 1152 called number
of coded bits per OFDM symbol for BPSK, QPSK, 16-
QAM and 64-QAM respectively [1].
Interleaver was designed by an array of 1152, 1-bit
registers. The input data bus is 48-bit which takes
minimum of 4 and maximum of 24 clock cycles. Writing
address of array is generated inside the module which
takes decision on the value of rate_id input. There are 4-
output data buses, corresponds to provide data to BPSK,
QPSK, 16-QAM and 64-QAM modulation mappers,
having widths 1, 2, 4 and 6 bit(s) respectively. As there are
192-data carriers, so for output 192 clock cycles are
needed, hence operation of interleaver takes minimum of
196 and maximum of 216 cycles. Hardware architectural
view is presented in Fig. 8. All the modules of channel
coding are wrapped up under a top-level file.
Fig. 8. High-Level View of Interleaver.
B. Digital Modulation
OFDM PHY is adaptive and supports BPSK, QPSK,
16-QAM and 64-QAM for data carriers modulation. The
constellation diagrams are gray mapped, shows the
magnitudes I and Q components of each incoming bit(s) as
given in (10) Table 3 gives the Q1.14 representation of I
and Q magnitudes using (10), which are 16-bit wide [9];
Mag. Of Carrier = (value of the carrier at that point)*C
(10)
Where C = normalization factor, its value is 1,
1 2 , 1 1u and 1 42 for BPSK, QPSK, 16-QAM
and 64-QAM respectively [1].
The modulation mappers were modeled as ROMs in
which 16-bit hex numbers were saved, outputted for
respective combinations of input bits. Two ROMs were
employed for each mapper, one for I part and other for Q.
Thus total of 8 ROMs were wrapped up in 4 sets
corresponds to complete mapper of any scheme, having
different input data bus widths and number of locations
but same 16-bit wide output path.

TABLE 3. Q1.14 FIXED POINT FORMAT OF I & Q MAGNITUDES

The rate_id input selects one of the four output lines
The top level design is shown in Fig. 9.

The I and Q parts each of 192 data subcarriers are fed
into OFDM symbol assembler which inserts pilot, DC and
guard carriers to make total of 256 carriers for OFDM
realization.
C. Orthogonal Frequency Division Multiplexing
IFFT of magnitude N, applied on N symbols, realizes
an OFDM signal [10]. The IFFT takes frequency domain
spectrum X(k)and converts it to time domain signal x(n)
by successively multiplying it by a range of sinusoids as
given by (11);
x(n) = X(k) sin _
2nkn
N
] - ] X(k) cos(
2nkn
N
N-1
n=0
)
N-1
n=0
(11)
Where k = 0 to N-1 and N = 256 [11].
1) OFDM Symbol Assembler
An OFDM symbol is made up of three types of basic
sub-carriers [3];
192 Data subcarriers: Frequency indices; -100 to -
1 and +1 to +100 (except at pilot positions).
8 Pilot subcarriers (BPSK modulated): Frequency
indices; -88, -63, -38, -13, +13, +38, +63 and
+88.
56 Null subcarriers: Frequency indices; DC-carrier
at 0; Lower guard from -128 to -101; upper guard
from +101 to +127.
Pilots are generated by PRBS generator using
MODULATIO
N
CARRIER
VALUE
MAGNITUDE HEX (16-BIT)
BPSK
1 1 4000
-1 -1 C000
QPSK
1 0.707106781 2D41
-1 -0.707106781 D2BF
16-QAM
1 0.316227766 143D
-1 -0.316227766 EBC3
3 0.948683298 3CB7
-3 -0.948683298 C349
64-QAM
1 0.15430335 09E0
3 0.46291005 1DA0
5 0.77151675 3160
7 1.08012345 4520
-1 -0.15430335 F620
-3 -0.46291005 E260
-5 -0.77151675 CEA0
-7 -1.08012345 BAE0
Fig. 9. Hardware Realization of Mapper
143

polynomial x
11
+ x
9
+1, which produces a sequence w
k
at
its LSB and denotes the OFDM symbol number in the
current frame[1]. Pilots are BPSK modulated and their I
magnitudes are given by 1 -2w
k
and 1 -2w

k
for carrier
indices -88, -38, 63, 88 and -63, -13, 13, 38 respectively.
DC and guard are null carriers with zero magnitudes. The
OFDM symbol is assembled inside a module comprises of
pilot generator module and two 256x16 RAMs, each for I
and Q parts to accommodate on specified locations
correspond to frequency indices[12]. The input data line of
each RAMs selects either data, pilot, DC or guard carriers.
The system is designed in a way that pilot, DC and guard
carriers are already present in the RAMs, and just after 2
clocks of 1
st
input data sample, output is available.
2) The IFFT Module
The IFFT module is fed by the OFDM symbol
assembler with 256-complex samples. The IFFT module
was generated using Altera Quartus-II 9.0 mega function
wizard and wrapped in a top-level file to produce sop, eop
and source_ena signals internally in the same way as for
RS-encoder. It takes minimum of 512 clocks to complete
the processing. The output data is fed to CP generator
which introduces the redundancy to the OFDM symbol
thus act as a protection from inter symbol interference.
3) CP Generator
A copy of the last N
IPP1
-
1
0
, samples is appended to
the beginning of the symbol, which is termed as CP and
increases symbol duration hence multipath is achieved
[12]. The value of 0 is taken as 1/16 which represents a
moderate channel, thus the term N
IPP1
-
1
0
, comes out to
be 16 and the overall symbol length becomes 272-complex
samples. The hardware structure is simply achieved by
designing two 256x16 RAMs, in which first whole 256-
complex carriers are written but reading is started from
239 to 255 and then 0 to 255 RAM locations. The whole
process takes about 532 clocks.
This is all about the hardware implementation of IEEE
Std 802.16d OFDM PHY on FPGA, next section would
present various results of the project.
III. RESULTS
A. Data Rate Calculation
Data rate = un-coded bits / OFDM symbol Duration (12)

I
s
= [ 1(nBw)N
IPP1
](1 + 0) (13)

Where I
s
=

OFDM symbol Duration;
n = 8/7 called sampling factor;
Bw = Channel Bandwidth; in this design it was taken as
1.75, 3.5, 7 and 14 MHz ;
N
IPP1
= 256 called IFFT points;
0 = 1/16; called ratio of CP time to useful symbol
time.

Using (12) and (13) for each modulation and coding
scheme depicted in table 1, the minimum and maximum
data rates were found to be 5.64 Mbps and 50.82 Mbps for
BPSK 1/2 and 64-QAM 3/4 respectively that require 6.55
MHz clock which was easily achieved by scaling down the
oscillator of frequency 50 MHz on Altera DE2 FPGA
development kit. Timing analysis suggests 109.26 MHz
as maximum attainable speed for the implemented design.
B. Hardware Resources
Synthesis of the design using Altera Quartus II 9.0
Web Edition software suggests device resource summary
for Altera Cyclone II EP2C35F672C6 FPGA chip shown
in table 4.
TABLE 4. SYNTHESIS RESULTS
Module
LC
Combination
LC
Registers
Memory
Bits
DSP Mult-
ipliers
Channel
coder
3007 2123 1152 0
Mapper 7 8 2048 0
OFDM 3864 4386 56577 18
Total 6878 6517 59777 18
IV. CONCLUSION
Simulations on ModelSim-Altera 6.4a (Quartus II 9.0)
Starter Edition were fully compliant with the IEEE test
data provided in the standard. For hardware prototyping of
the design, Visual Basic application software was
developed which provides GUI for data sending and
receiving to FPGA Chip through UART interface. As
FPGA platform provides a flexible design approach so this
work could open up the doors for many other projects as
one can deploy complete WiMAX CPE if MAC and RF
front end for Rx and Tx would properly designed and
integrated.
V. REFERENCES
[1] IEEE Standard for Local and Metropoliton Area Networks. Part 1 :
Air Interface for Fixed Broadband Wireless Access Systems. New
York, USA : s.n., October 1, 2004.
[2] Jordan Douglas Guffey. OFDM Physical Layer Implementation for
the Kansas University Agile Radio. University of Kansas. Kansas :
s.n., 2008. Technical Report.
[3] Wimax-speed. wikimedia.org. [Online] [Cited: September 5, 2009.]
http://commons.wikimedia.org/wiki/File:Wimax-speed.jpg.
[4] Lili Zhang. A study of IEEE 802.16a OFDM-PHY Baseband.
Electrical Engineering, Linkping Institute of Technology.
Linkping : s.n., 2005. Master thesis in Electronics Systems. LiTH-
ISY-EX--05/3627--SE.
[5] Loutfi Nuaymi. WiMAX: Technology for Broadband Wireless
Access. ENST Bretagne : John Wiley & Sons Ltd, 2007. p. 310.
[6] Andy Bateman. Digital Communication - Design for the Real
World. s.l. : Addison Wesley Longman Ltd., 1999.
[7] Mohammad Azizul Hasan. Performance Evaluation of
WiMAX/IEEE 802.16 OFDM Physical Layer. Department of
Electrical and Communications Engineering , Helsinki University
of Technology . Espoo : s.n., 2007. Master Thesis.
[8] Bernard Sklar. Digital Communications Fundamentals and
Applications. 2nd. Los Angeles : Pearson Education, Inc.
[9] MATLAB 7.8.0 (R2009a), Help. s.l. : MathWorks, Inc., 2009.
[10] van Nee, R. and Prasad, R. OFDM for Wireless Multimedia
Communications. s.l. : Artech House, 2000.
[11] Charan Langton. OFDM. Intuitive Guide to Principles of
Communications. [Online] http://www.complextoreal.com/.
[12] Amalia Roca Persiva . Implementation of a WiMAX simulator in
Simulink. Institute of Communications & Radio-Frequency
Engineering, Vienna University of Technology. Vienna : s.n., 2007.
Master Thesis.

144
High Level Modeling of an Ultra Wide-Band
Baseband Transmitter in MATLAB
Waqas Ali Khan, Talha Ali Khan, Muhammad Arif Ali and Shahid Abbas
Final Year Students of Electronics Department
NED University of Engineering & Technology
Karachi, Pakistan
(waqas035, talha080, arifali137, shahid.nedian)@hotmail.com
AbstractWireless Personal Area Network ( WPAN ) system
with ranges of 4-10 m become popular in replacing wire system,
technologies such as Bluetooth and ZigBee used for this purpose
but due to its low data rate of 1 Mbps which is not enough for
large file transfer and applications like video streaming there is a
need of technology which address all these issues, Ultra
Wideband is such a emerging wireless technology which support
data rates up to 0.5 Gbps. UWB with its Multi-Band Orthogonal
Frequency Division Multiplexing ( MB-OFDM ) infrastructure is
an ultimate choice for the transmission of high speed data by
dividing its wide frequency spectrum into sub 14-bands. The
architecture of MB-OFDM transmitter baseband is presented in
this paper and its modeling in MATLAB is discussed in detail.
Modeling of UWB PHY transmitter baseband in MATLAB is
helpful for designing its commercial product by optimizing
various parameters.
I. INTRODUCTION
In February 2002, the Federal Communications
Commission (FCC) allocated a large spectrum from 3.1 GHz
to 10.6 GHz for use of commercial applications of UWB.
Since then great efforts are made in standardization of UWB
devices. The IEEE 802.15.3 Task Group ( TG3a ) is set for
proposing final draft for UWB standards, the committee finals
two drafts one proposed UWB using direct sequence CDMA
supported by Xtreme Spectrum and Deca Wave and other is
UWB using MB-OFDM base structure supported by Intel and
Texas but deadlock arises between these two. So group of
more than 170 companies which includes Intel, Texas and
Motorola and many others forms a forum with the name of
WiMedia Alliance for the development of UWB system using
multi-band ofdm structure which announces its High Rate
Ultra Wideband MAC and PHY standards which is also
supported by ECMA by releasing two international ISO based
specifications ECMA 368 and ECMA 369 for Ultra Wideband
technology. Also, in 2007 IEEE 802.15 Task Group (TG4a)
approved a standard which support UWB infrastructure using
Direct sequence CDMA spread spectrum approach.
Ultra Wideband with its absolute bandwidth of more than
500 MHz and with its low transmitting power provides wealth
of advantages better than any communication system
because these two features provides high accuracy and
friendly coexistence with other communication system, to
fulfill these requirements many wireless protocols have been
designed but Orthogonal Frequency Division Multiplexing
(OFDM) has become the ultimate choice for modulation
scheme for high data rate digital transmission due to its
spectral efficiency and robustness against multipath
interference.
In multi-band OFDM approach the large swaths of ultra
wideband frequency spectrum is divided into fourteen smaller
subbands, each of 528 MHz which is further grouped into five
bands each of which comprises of three subbands and the last
one consists of two subbands as see in Fig. 1. The MB-OFDM
UWB system also supports multiples modes of operation: a
mandatory mode in which first three subbands are included
(Mode 1) and an optional mode which consist of seven
subbands (Mode 2).
The remaining paper is organized as follows Section 2
provides a brief overview on the architecture of the baseband
portion of MB-OFDM transmitter. The modeling of building
blocks of MB-OFDM transmitter is discussed in detail in
Section 3. Finally some concluding remarks and future work is
discussed in Section 4.

II. ARCHITECTURE OF MB-OFDMTRANSMITTER BASEBAND
Basic building blocks of MB-OFDM transmitter baseband
is shown in Figure 2. Data from MAC is coming to side
stream scrambler which function isto randomizes the data
stream to remove repeated patterns and spaces, after which
incoming data are encoded to reduce the bit error rate. The
main purpose isto correct the error that are arises due to the
channel, convolutional encoder is suitable for this purpose
with coding rate of 5/8 which is acquired by puncturering
some data. The stream of data then shall be interleaved prior
to modulation to provide robustness against burst of errors.
After coding and interleaving serial binary data divided
into group of two bits which is converted into complex valued
constellation points which becomes input to the IFFT which is
the core of baseband portion of transmitter. A 128 point IFFT
is used to create 122 subcarriers out of which 12 are pilot
subcarriers, 100 data subcarriers and 10 are guard subcarriers,
five at each end. The rest six are set to null subcarriers. To
compensate for multipath propagation and to eliminate ISI a
Zero pad suffix of length 37 is added. Table 1. summarizes the
parameters related to ultra wideband MB-OFDM modulation.
2009 International Conference on Emerging Technologies
978-1-4244-5632-1/09/$26.00 2009 IEEE 194
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Figure 1. Division of UWB Frequency Spectrum
III . TRANSMITTER BASEBAND DESIGN IN MATLAB
Matlab is a high level technical computing language which
provide interactive envoirment for algorithm development and
modeling of communication system. Also integration of
Simulink with Matlab offer various tools for simulating and
testing any communication system. UWB with transfer data
rate of 200 Mbps is modeled. Below is the description of the
UWB Model proposed in Simulink.
A. Input of the Transmitter / Scrambler
Input source for the scrambler is the data from MAC Layer
which includes MAC Header , HCS and MAC frame body,
since the coming data is in the pattern of 1s and 0s so it can
be modeled by any data source which can create a pattern of
1s and 0s. A Maximum Length Sequence (MLS) is used for
this purpose which is the type of pseudorandom binary
sequence. They are polynomial rings generated using maximal
linear feedback shift registers and are so called because they
are periodic and reproduce every binary sequence that can be
reproduced by the shift registers. The polynomial used for this
purpose is defined by expression as follows;
f(x) = x
10
+ x
3
+ 1 (1)

In Matlab there is a builtin block of PN SEQUENCE
GENERATOR which has a parameters of generator
polynomomial and initial states of shift registers which in our
case become [ 1 0 0 0 0 0 0 1 0 0 1 ] and [ 0 0 0 0 0 0 0 0 0 1].
B. Scrambler
A scrambler (often referred to as a randomizer) is a device
that manipulates a data stream before transmitting. The
purpose of scrambling is to eliminate the dependence of a
signals power spectrum upon the actual transmitted data and
making it more disperse to meet maximum power spectral
density requirements, because if the power is concentrated
in a narrow frequency band, it can interfere with adjacent
channels. A side-stream scrambler shall be used to whiten
only portions of the PLCP header , i.e., the MAC header and
HCS, and the entire PSDU.
In addition, the scrambler shall be initialized to a seed
value specified by the MAC at the beginning of the MAC
header and then re-initialized to the same seed value at the
beginning of the PSDU.
The polynomial generator, g(D), for the pseudo-random
binary sequence (PRBS) generator shall be;
g(D) = 1 + D
14
+ D
15
(2)
Where D is a single bit delay element and integers in the
power of D represent connection of shift register with modulo
2 adder. Using this generator polynomial, the corresponding
PRBS, x
n
, is generated as;

x
n
= x
n-14
x
n-15
(3)
The scrambled data bits s
n
are obtained as follows;

s
n
= b
n
x
n
(4)
where b
n
are unscrambled data bits.
In Matlab there is a block of scrambler with a parameter of
scramble polynomial and initial states. Scramble polynomial is
defined by 2 and the initial states represents the states of
scrambler register when simulation starts.
C. FEC Encoder ( Convolutional Encoder )
Convolutional Coding is a part of the Forward Error
Correction (FEC) done in communication systems. The
purpose of forward error correction (FEC) is to improve the
capacity of a channel by adding some carefully designed
redundant information to the data being transmitted through
the channel. The process of adding this redundant information
is known as channel coding .
Convolutional codes operate on serial data, one or a few
bits at a time. The two parameters which defined
convolutional codes are : the code rate and the constraint
length, the code rate is defined as the ratio of number of bits
into the convolutional encoder to the number of channel
symbols output by the convolutional encoder in a given
encoder cycle. The constraint length, k, denotes the length
of the convolutional encoder.
Figure 2. Basic Architecture of MB-OFDM Transmitter Baseband
Scrambler FEC Encoder Puncturer
Interleaver Mapper
OFDM
Modulator (IFFT
& ZPS )
195
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TABLE 1. PARAMETERS OF MB-OFDM MODULATION
Parameters Values
NSD : Number of Data Subcarrier 100
NSP : Number of Pilot Subcarrier 12
NSG : Number of Guard carriers 10
NST : Number of total Subcarrier 122
Number of Null carriers used 6
Number of Samples per zero padding suffix 37
Total Number of samples per symbol 165
Subcarrier Modulation QPSK
TSYM : Symbol Interval 312.5 ns
Code Rate 1/3. 1/2, 5/8, 3/4, 11/32
In the proposed design of our model of UWB for 200
Mbps according to the defined standard the code rate is 5/8
which is obtained by combining five encoder with a rate of /3
(known as mother rate) and by puncturering some output bits.
The constraint length parameter k is 7. The generator
polynomial define for UWB are g
0
= 133
8
, g
1
= 165
8
and g
2
=
171
8
, these numbers are in octet system which is converted to
binary number system where in binary number if bit is 1 then
it shows the connection of that register with modulo addition
and if bit is 0 then register is not connected with shift registers
as shown in Figure 3. The bit denoted as A shall be the first
bit generated by the encoder, followed by the bit denoted as
B, and finally, by the bit denoted as C. The Convolutional
Encoder block in Matlab has a parameter of Trellis structure
which is define by poly2trellis command which has two
arguments constraint length and code generator polynomial
which is defined above. Poly2trellis command create a trellis
diagram which is best representation for convolutional
encoding. The operation mode is selected Terminate trellis
by appending bitsby pop down menu which terminate the
trellis at the all zero state by appending tail bits at the end of
each input frame.
D. Puncturer
The principle of puncturing is a process by which a few
parity bits are deleted in order to improve the code rate. In
Matlab the puncture block creates an output vector by
removing selected elements of the input vector and preserving
others. The input can be a real or complex vector of length K.
The block determines which elements to remove or preserve by
using the binary Puncture vector parameter. If Puncture vector
(k) = 0, then the kth element of the input vector does not
become part of the output vector and If Puncture vector (k) = 1,
then the kth element of the input vector is preserved in the
output vector. Since the input is frame base therefore puncture
vector must be multiple of it.
Figure 3. Convolutional encoder : rate R = 1/3, constraint length k = 7
E. Interleaver
In MB-OFDM system we perform two types of
interleaving: symbol interleaving and tone interleaving as see
in Figure 4. In Symbol interleaving bits of stream are
interleaved over three OFDM symbol to acquire different level
of frequency diversity because each OFDM symbol is
transmitted in different frequency bands. The symbol
interleaver works on 3N
CBPS
bits where N
CBPS
is the number of
coded bits per OFDM symbol which in our case is 200. If A(i)
and B(j) represent the input and output bits of the symbol
interleaver respectively at position j, the relationship between
the two is given by;
B(j) = A{ floor( i/N
CBPS
) + 3mod( i, N
CBPS
) } (5)
Where i, j = 0, 1, 2 .N
CBPS
.
The output B(j) from symbol interleaver is passed through
tone interleaver. Tone interleaver is then used to interleave bits
in each OFDM symbol to exploit frequency diversity across
tones and provide robustness against narrow band interferers. If
C(i) and D(j) represents inputs and outputs of tone interleaver
respectively, the relationship between them is given by;
D(j) = C{ floor( i/N ) + 10mod( i, N ) } (6)
Where N = N
CBPS
/10
i, j = 0, 1, 2, N
CBPS
Matrix interleaver blocks has a parameters of number of
columns and number of rows which in our case become 100
and 3 respectively for symbol interleaver and for tone
interleaver it becomes 10 and 10. Buffer block is also used to
scale up the matrix size at the beginning of symbol interleaver
and at the end of matrix interleaver, buffer block is also used
in the mid position to scale down the dimension of data matrix
to make correct input dimensions for tone interleaver.
F. SubCarrier Modulator (QPSK Modulator Baseband)
For data rates less than or equal to 200 Mbps preferred
subcarrier modulation is QPSK and for data rate greater than
200 Mbps Dual carrier modulation (DCM) is preferred. Since
our proposed UWB system is for 200 Mbps so we use QPSK
baseband modulator. The serial binary data from the
interleaver shall be grouped into two bits and converted into
complex numbers representing QPSK Constellation points.
The conversion shall be performed according to the Gray-
coded constellation mappings. The values, d, are formed by
multiplying the resulting (I + jQ) value by a normalization
factor of KMOD, as described in (7);
Figure 4. A block diagram of the various stages of the bit interleaver
196
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d = ( I + jQ )*K
MOD
(7)
where K
MOD
= Normailzation Factor = 1 / 2
For QPSK, b
o
determines the I value and b
1
determines the
Q value. Matlab has builtin QPSK baseband modulator block
with parameters Input type, Constellation ordering and phase
offset which we set Bit , Gray and pi/4 respectively in our
case.
G. OFDM Modulator
This is the core block of MB-OFDM Transmitter Base
band. In this block construction of an OFDM signal and IFFT
operation takes place. OFDM Signal can be described by the
(8);
S
n
[k]=1/N
FFT
[ C
D,n
[l]exp(j2*pi*M
D
[l]k/N
FFT
)+ C
G,n
[l]
exp(j2*pi*M
G
[l]k/N
FFT
)+ C
P,n
[l]exp(j2*pi*M
P
[l]k/N
FFT
)] (8)
where limit of first is [0,N
SD
1] , limit of second is
[0, N
SG
1] and the last one has a limit [0,N
SP
1] and k [0,
N
FFT
1]. C
D,n
[l] , C
G,n
[l] and C
P,n
[l] are the complex numbers
placed on the l
th
data,guard and the pilot subcarriers of n
th
OFDM symbol and M
D
[l],M
G
[l] and M
P
[l] define a mapping
from the indices [0,N
SD
1], [ 0, N
SG
1] and [0,N
SP
1] to
the logical frequncy offset indices as defined in Table 3. In
baseband portion data is transmitted from Physical Service
Data Unit (PSDU) to PLCP Protocol Data Unit (PPDU),
which comprises of PLCP Preamble, PLCP Header and
PSDU, PLCP Header and PSDU is modeled as the input
source of the transmitter because they need scrambling now
we modeled PLCP Preamble which comprises of Packet
Synchronization Sequence, Frame Synchronization Sequence
and Channel Estimation Sequence which is modeled in Matlab
by creating a matrix of [123x9], [128x3] and [128x6] with
values defined in [5]. After constellation mapping of a signal
its enter into the Modulator Subsystem where its first passes
through the Group data for OFDM Symbol block which
reshape the signal after then its indices is converted into
logical frequency offset with the help of SELECT ROW
block, also Pilot signal and Null carriers are added to it which
is modeled by using DSP CONSTANT block and their values
are defined in the parameters of the block, all these signals are
TABLE 2. QPSK CARRIER MAPPING
Input bit ( b0b1 ) I-out Q-out
00 -1 -1
01 -1 1
10 1 -1
11 1 1
then Concatenate into single dimension by using MATRIX
CONCATENATE block. Channel Estimation Sequence block
is then concatenate with the output of the MATRIX
CONCANTENATE block. After the construction of
signalinverse fast fourier transform is applied by using builtin
block of the IFFT in Matlab, Packet Synchronization
Sequence and Frame sequence is added concatenate with the
output of the IFFT by again using MATRIX
CONCATENATE block. Zero padding suffix and guard
interval is added in the last so we get a [ 165 x 1 ] length of an
OFDM signal which is our requirement.
TABLE 3. FREQUNCY OFFSET INDICES
H. Simulation Results
Transmitted OFDM signal can be viewed using SCOPE
block whose snapshot is shown in Fig. 6.

IV . CONCLUSION
In this model, we proposed architecture of MB-OFDM
UWB baseband transmitter. Power Spectrum of Transmitter
shows in Figure 6. that it fulfill the FCC standards for UWB
System. By changing code rate and subcarrier modulator
block, we can model this system for various data rates for
M
D
[l] M
G
[l] M
P
[l]
l 56 ; l = 0 -61 + l ;
l =0.4
-55 + 10*l ; l = 0, 1, 2, 3,,11
l 55 ; 1 l 9 52 + l ;
l =5.9
l 54 ; 10 l 18
l 53 ; 19 l 27
l 52 ; 28 l 36
l 51 ; 37 l 45
l 50 ; 46 l 49
l 49 ; 50 l 53
l 48 ; 54 l 62
l 47 ; 63 l 71
l 46 ; 72 l 80
l 45 ; 81 l 89
l 44 ; 90 l 98
l 43 ; l = 99
Figure 5. Implementation of Bit Interleaver in Matlab
197
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UWB system. Thus this model provides good basis for
implementing an ASIC for proposed design in future.
REFRENCES
[1] D. M. W. Leenaerts. (2006). Transceiver Design for Multiband OFDM
UWB. EURASIP Journal on Wireless Communications and Networking
.
[2] MATLAB 7, The Language of Technical Computing. (n.d.). Retrieved
from
http://www.mathworks.com/applications/tech_computing/technical_liter
ature.html
[3] A Tutorial on Convolutional Coding with Viterbi Decoding, Spectrum
Applications. (n.d.). Retrieved from
http://home.netcom.com/~chip.f/viterbi/tutorial.html
[4] A. Batra et al. (March2003). Multi-band OFDM Physical Layer
Proposal for IEEE 802.15 Task Group 3a.
[5] Fixed-Point Modeling in an Ultra Wideband (UWB) Wireless
Communication System. (2004, May ). MATLAB Digest .
[6] Fredrik Kristensen, Peter Nilsson, Anders Olsson. (n.d.). Flexible
baseband transmitter for OFDM. Retrieved from
www.imec.be/pacwoman/publications/WP8- Lund-CSS03-11-07-2003-
V1.0.pdf
[7] ( 3rd Edition , December 2008.). High Rate Ultra Wideband PHY and
MAC Standard
[8] Implementing WiMax OFDM Timing and Frequency Offset Estimation
in Lattice FPGAs. (2005). White papers .
[9] Maximum Length Sequence. (n.d.). Retrieved 2009, from wikipedia.org:
http://en.wikipedia.org/wiki/Maximum_length_sequence
[10] Min-Su Kim, HoJun Kim, Jong Tae Kim,. (2008). High-level Modeling
of UWB PHY for IEEE 802.15.4a. International Confrence and Hybird
Information Technology.
[11] Nishant Kumar. (2004). MAC and PHY Layer Design for Ultra-
WideBand Communications. Master Thesis, Virginia Polytechnic
Institute and State University, Electrical and Computer Engineering.
[12] Xu Jinsong, Lu Xiaochun, Wu Haitao, Bian Yujing, Zou Decai, Zou
Xiaolong, Wang Chaogang. (2008). Implementation of MB-OFDM
Transmitter Baseband Based on FPGA. Circuits and Systems for
Communications, 2008. ICCSC 2008. 4th IEEE International
Conference on, (pp. 50-54). Shanghai.
198
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Figure 6. OFDM Transmitted Signal
199
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22
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1) Data Scrambling
It protects against-theoretic uncertainty, avoiding long
sequences of consecutive ones or consecutive zeros. A 15-
bit PRBS generator having polynomial, 1+ x
14
+ x
15
was
implemented to produce scrambled data bits on each burst
of downlink data [1]. The seed value shown in Fig. 4 shall
be used to calculate the scrambled bits. The DIUC value is
simply the Rate ID values as mentioned in table 224 of
section 8.3.3.4.3 of IEEE Std 802.16d.
The FPGA implementation of scrambler is capable of
performing scrambling of 8-bits at a time instead of single
bit. This makes system to work faster 7 times with no extra
hardware as the next state of LFSR register was defined by
the XORed shifting of LSBs to eight MSBs position.
Hardware architecture is given in Fig. 5, showing I/O
interfaces of the module.
2) FEC
It is the process employed to detect and correct errors
without retransmission [6]. For OFDM PHY, the FEC is
accomplished by the concatenation of Reed-Solomon outer
code and a rate compatible Convolution inner code shown in
Fig. 6. As the WiMAX supports adaptive PHY, hence
different modulation and coding schemes could be
employed depending upon channel conditions [7], details of
whose are given in table 1.
a) Reed-Solomon Coding
RS-Encoding is specified by adding parity symbols to
the original data packet. If data packet contains k-symbols
each of m-bit(s) then encoded version is determined by
RS(n,k,t), with n is length of coded block and t is the
maximum number of symbols that can be corrected. RS-
Encoding governs following relations [8];
n = 2
m
- 1 (1)
k = 2
m
-1 - 2t (2)
t = (n - k)2 (3)
Figure 5. Architecture of Scrambler
In the proposed design, RS-code shall be derived from a
systematic RS (N = 255, K = 239, T = 8) code using GF (2
8
),
primitive and generator polynomial depicted in (4) and (5)
respectively [1].
p(x) = x
8
+ x
4
+ x
3
+x
2
+ 1 (4)
g(x) = (x +
0
)(x +
1
). . . (x +
21-1
); = u2 Ecx (5)
In this project the RS-encoder was generated using
Altera Quartus-II 9.0 mega function wizard and was
wrapped in a top-level file in order to introduce variable
coding rates depicted in table 1 and to produce sop, eop,
numcheck and source_ena signals internally which are
needed by Alteras generated RS-encoder. The I/O data path
is 8-bit wide. The numcheck signal specifies the desired
number of parity symbols. The operation is completed in
minimum 14 and maximum 124 clock cycles. The high-
level hardware design is shown in Fig. 7.
b) Convolutional Encoding
It is described by two parameters; the code rate and the
constraint length. The code rate mn, is expressed as a ratio
of the number of input bit(s) m to the output bits n in a
given encoder cycle. The constraint length parameter K
denotes the length of the convolutional encoder, i.e. how
many K-bit stages are available to feed the combinatorial
logic that produces the output symbols [8].
In OFDM PHY, each RS encoded data is further
encoded by convolutional encoder with a native rate of 1/2,
a constraint length equal to 7. The output code bits are
generated by generator polynomial defined in (6) and (7);

0
1
= 171
oct
F0R X (6)

0
1
= 1SS
oct
F0R (7)
Figure 3. Channel Coding [5]
Figure 4. OFDM Scrambler Downlink Initialization Vector [1]
Figure 6. OFDM PHY FEC Scheme [5]
23
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TABLE 1. MANDATORY CHANNEL CODING PER MODULATION [1]
Modulation
Un-coded block size
(bytes)
Coded block
Size (bytes)
Overall rate RS-Code CC Code rate
BPSK 12 24 1/2 (12,12,0) 1/2
QPSK 24 48 1/2 (32,24,4) 2/3
QPSK 36 48 3/4 (40,36,2) 5/6
16-QAM 48 96 1/2 (64,48,8) 2/3
16-QAM 72 96 3/4 (80,72,4) 5/6
64-QAM 96 144 2/3 (108,96,6) 3/4
64-QAM 108 144 3/4 (120,108,6) 5/6


Four coding rates are given in table 1, which are
achieved by puncturing patterns specified in the given table
2 due to which four convolutional encoders of rate 1/2. 2/3,
3/4 and 5/6 were implemented, each having input data path
8, 16, 24 and 40 bits respectively so that data could be
processed in parallel rather than serially to save the system
clock cycles. These four encoders were enclosed in a top-
level file which contains input and output data buffers and
selects only one encoder at a time indicated by rate_id input.
The input data path is 8-bit while output is 48-bit wide. The
whole process takes at least 16 and at most 244 clocks. The
hardware view is shown in Fig. 8.
3) Interleaving
In order to reduce probability of burst errors, interleaving is
done which makes adjacent coded bits non-adjacent. Let
Ncpc be the number of coded bits per

TABLE 2. PUNCTURING PATTERNS FOR CC-CODE RATES [1]
CC-Code Rates
Rate 1/2 2/3 3/4 5/6
X 1 10 101 10101
Y 1 11 110 11010
XY X1Y1 X1Y1Y2 X1Y1Y2X3 X1Y1Y2X3Y4X5

subcarrier, i.e., 1, 2, 4 or 6 for BPSK, QPSK, 16-QAM, or
64-QAM respectively. Let s = ccil (Ncpc2). Within a
block of N
cbps
bits at transmission, let k be the index of the
coded bit before the first permutation; m
k
be the index of
that coded bit after the first and before the second
permutation and let [
k
be the index after the second
permutation. The first and second permutation is defined by
(8) and (9) respectively;
m
k
= [
N
cbps
12
. k
mod12
+loor(
k
12
) (8)
[
k
= s. loor [
m
k
s
+(m
k
+N
cbps
- loor(
12.m
k
N
cbps
))
mod(s)
(9)

Where N
cbps
= 192, 384, 768 and 1152 called number of
coded bits per OFDM symbol for BPSK, QPSK, 16-QAM
and 64-QAM respectively [1].
The hardware realization of interleaver was designed
using an array of 1152, 1-bit registers. The input data bus is
48-bit which takes minimum of 4 and maximum of 24 clock
cycles in accommodation of bits to pre-calculated positions.
Writing address of array is generated inside the module
which takes decision on the value of rate_id input which
specifies the modulation scheme and then on an internal
counters state which denotes how many input packets have
been written to register array. There are 4-output data buses,
each corresponds to provide data to BPSK, QPSK, 16-QAM
and 64-QAM modulation mappers, having widths 1, 2, 4
and 6 bit(s) respectively. As there are 192-data carriers, so
for output 192 clock cycles are needed, hence operation of
interleaver takes minimum of 196 and maximum of 216
cycles. Hardware architectural view is presented in Fig. 9.
All the modules of channel coding are wrapped up under a
top-level file which communicates to the
Figure 7. Reed-Solomon Top-Level Module Design

Figure 8. Convolutional-Encoder Top-Level Module Architecture
24
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modulation mapper through its four output data buses
described in upcoming sub-section.
B. Digital Modulation
As the OFDM PHY is adaptive therefore it supports
multiple schemes BPSK, QPSK, 16-QAM and 64-QAM for
data carriers modulation. The constellation diagrams are
gray mapped and shows the magnitudes I and Q (In-phase
and Quadrature) components of each incoming bit(s)
combination along with their normalization factor C to
calculate magnitude of each point in the constellation
diagram as given in (10);

Mag. Of Carrier = (value of the carrier at that point)*C (10)
Where C = normalization factor, its value is 1,
1 V2 / , 1 V1u / and 1 V42 / for BPSK, QPSK, 16-QAM and
64-QAM respectively [1].
Using (10), the magnitudes I and Q parts of all points in
each modulation schemes were calculated and assigned
them Q1.14 Fixed Point Representation [9] so that each
subcarrier is now written as a 16-bit signed number each for
I and Q part, this simplification is given in table 3. ROMs in
which 16-bit hex numbers were saved which are outputted
for respective combinations of input bits corresponds to the
gray mapped constellation plots.
TABLE 3. Q1.14 FIXED POINT FORMAT OF I & Q
MAGNITUDES
MODULATION CARRIER VALUE MAGNITUDE HEX (16-BIT)
BPSK
1 1 4000
-1 -1 C000
QPSK
1 0.707106781 2D41
-1 -0.707106781 D2BF
16-QAM
1 0.316227766 143D
-1 -0.316227766 EBC3
3 0.948683298 3CB7
-3 -0.948683298 C349
64-QAM
1 0.15430335 09E0
3 0.46291005 1DA0
5 0.77151675 3160
7 1.08012345 4520
-1 -0.15430335 F620
-3 -0.46291005 E260
-5 -0.77151675 CEA0
-7 -1.08012345 BAE0

The modulation mappers were simply modeled as For
designing of each modulation mapper, two ROMs were
implemented, one for I part and other for Q. Thus total of 8
ROMs were wrapped up in 4 sets of top-level modules each
corresponds to complete mapper of any scheme, each
having different input data bus widths and number of
locations but same 16-bit wide output path. The rate_id
input selects one of the four output lines corresponding to
requested modulation. The top level design is shown in Fig.
10.
The I and Q parts each of 192 data subcarriers are fed
into OFDM symbol assembler which inserts pilot, DC and
guard carriers to make total of 256 carriers for OFDM
realization.
C. Orthogonal Frequency Division Multiplexing
OFDM theory states that the IFFT of magnitude N,
applied on N symbols, realizes an OFDM signal, where each
symbol is transmitted on one of the N orthogonal
frequencies [10]. The IFFT takes frequency domain
spectrum X(k)and converts it to time domain signal x(n)
by successively multiplying it by a range of sinusoids as
given by (11);
x(n) = _ X(k) sin [
2nkn
N
- ] _ X(k) cos(
2nkn
N
N-1
n=0
)
N-1
n=0
(11)

Where k = 0 to N-1 and N = 256 [11].
1) OFDM Symbol Assembler
An OFDM symbol is made up of three types of basic
sub-carriers [3];
192 Data subcarriers: Frequency indices; -100 to -1
and +1 to +100 (except at pilot positions).
8 Pilot subcarriers: Frequency indices; -88, -63, -
38, -13, +13, +38, +63 and +88.
56 Null subcarriers: Frequency indices; DC-carrier
at 0; Lower guard from -128 to -101; upper guard
from +101 to +127.
Pilots are generated by PRBS generator using
polynomial x
11
+ x
9
+1, which produces a sequence w
k
at its
LSB and denotes the OFDM symbol number in the current
frame[1]. Pilots are BPSK modulated and their I magnitudes
are given by 1 -2w
k
and 1 -2w

k
for carrier indices -88, -
38, 63, 88 and -63, -13, 13, 38 respectively.


Figure 9. High-Level View of Interleaver
Figure 10. Hardware Realization of Mapper
25
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DC and guard are null carriers with zero magnitudes.
The OFDM symbol is assembled inside a module comprises
of pilot generator module and two 256x16 RAMs, each for I
and Q parts to accommodate on specified locations
correspond to frequency indices[12]. The input data line of
each RAMs selects either data, pilot, DC or guard carriers.
2) The IFFT Module
The IFFT module is fed by the OFDM symbol
assembler with 256-complex samples. The IFFT module
was generated using Altera Quartus-II 9.0 mega function
wizard and wrapped in a top-level file in the same way as
for RS-encoder. It takes minimum of 512 clocks to
complete the processing. The output data is fed to CP
generator which introduces the redundancy to the OFDM
symbol thus act as a protection from inter symbol
interference.
3) CP Generator
A copy of the last N
IPP1
-
1
0
, samples is appended to
the beginning of the symbol, called CP which increases
symbol duration hence multipath is achieved [12]. The
value of 0 is taken as 1/16, thus the term N
IPP1
-
1
0
, comes
out to be 16 and the overall symbol length becomes 272-
complex samples. The hardware structure is simply
achieved by designing two 256x16 RAMs, in which first
whole 256-complex carriers are written but reading is
started from 239 to 255 and then 0 to 255 RAM locations.
This is all about the hardware implementation of IEEE Std
802.16d OFDM PHY on FPGA, next section would present
various results of the project.
III. RESULTS
A. Data Rate Calculation
Data rate = un-coded bits / OFDM symbol Duration (12)

I
s
= [ 1(nBw)N
IPP1
](1 + 0) (13)

Where I
s
=

OFDM symbol Duration;
n = 8/7 called sampling factor;
Bw = Channel Bandwidth; in this design it was taken as 1.75,
3.5, 7 and 14 MHz ;
N
IPP1
= 256 called IFFT points;
0 = 1/16; called ratio of CP time to useful symbol time.

Using (12) and (13) for each modulation and coding
scheme depicted in table 1, the minimum and maximum
data rates were found to be 5.64 Mbps and 50.82 Mbps for
which 6.55 MHz clock is required which was easily
achieved by scaling down the oscillator of frequency 50
MHz on Altera DE2 FPGA development kit. Timing
analysis suggests that implemented system could attain a
maximum of 109.26 MHz.
B. Hardware Resources
Table 4 shows Synthesis results of the design using
Altera Quartus II 9.0 software and device resource
summary for Altera Cyclone II EP2C35F672C6 FPGA chip.
TABLE 4. SYNTHESIS RESULTS
Module
LC
Combination
LC
Registers
Memory
Bits
DSP Mult-
ipliers
Channel
coder
3007 2123 1152 0
Mapper 7 8 2048 0
OFDM 3864 4386 56577 18
Total 6878 6517 59777 18

IV. CONCLUSION
Simulations on ModelSim-Altera were fully compliant
with the IEEE test data. For hardware prototyping of the
design, Visual Basic application software was developed
which provides GUI for data sending and receiving to
FPGA Chip through UART interface. As FPGA platform
provides a flexible design approach so this work could be
integrated with MAC layer and RF front end for Rx and Tx
to deploy complete WiMAX CPE.
V. REFERENCES
[1] IEEE Standard for Local and Metropoliton Area Networks. Part 16 :
Air Interface for Fixed Broadband Wireless Access Systems. New
York, USA : s.n., October 1, 2004.
[2] Jordan Douglas Guffey. OFDM Physical Layer Implementation for
the Kansas University Agile Radio. University of Kansas. Kansas :
s.n., 2008. Technical Report.
[3] Wimax-speed. wikimedia.org. [Online] [Cited: September 5, 2009.]
http://commons.wikimedia.org/wiki/File:Wimax-speed.jpg.
[4] Lili Zhang. A study of IEEE 802.16a OFDM-PHY Baseband.
Electrical Engineering, Linkping Institute of Technology.
Linkping : s.n., 2005. Master thesis in Electronics Systems. LiTH-
ISY-EX--05/3627--SE.
[5] Loutfi Nuaymi. WiMAX: Technology for Broadband Wireless Access.
ENST Bretagne : John Wiley & Sons Ltd, 2007. p. 310.
[6] Andy Bateman. Digital Communication - Design for the Real World.
s.l. : Addison Wesley Longman Ltd., 1999.
[7] Mohammad Azizul Hasan. Performance Evaluation of WiMAX/IEEE
802.16 OFDM Physical Layer. Department of Electrical and
Communications Engineering , Helsinki University of Technology .
Espoo : s.n., 2007. Master Thesis.
[8] Bernard Sklar. Digital Communications Fundamentals and
Applications. 2nd. Los Angeles : Pearson Education, Inc.
[9] MATLAB 7.8.0 (R2009a), Help. s.l. : MathWorks, Inc., 2009.
[10] van Nee, R. and Prasad, R. OFDM for Wireless Multimedia
Communications. s.l. : Artech House, 2000.
[11] Charan Langton. OFDM. Intuitive Guide to Principles of
Communications. [Online] http://www.complextoreal.com/.
[12] Amalia Roca Persiva . Implementation of a WiMAX simulator in
Simulink. Institute of Communications & Radio-Frequency
Engineering, Vienna University of Technology. Vienna : s.n., 2007.
Master Thesis.
26
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1569241621-1
MBOFDM Transmitter Baseband Physical Layer
Modeling and Simulation in MATLAB

Waqas Ali Khan, Talha Ali Khan, Shahid Abbas, Syed Muhammad Danish and Muhammad Arif Ali
Final Year Students of Electronics Department, NED University of Engineering & Technology Karachi, Pakistan
(waqas035, talha080, shahid.nedian, danish514, arifali137)@hotmail.com


Abstract Wireless Personal Area Network System becomes
popular in replacing a wire technologies for short area range
communication system. Technologies such as Bluetooth, Wi-Fi
and ZigBee are used for this purpose but due to their low
transfer data rates they are unable to handle all those
applications which need high transfer rate like transfer of files
which has a size in GBs. Ultra Wide Band is such a wireless
promising technology which covers all these aspects by using its
MBOFDM Infrastructure. MBOFDM structure supports data
rate up to 0.5 Gbps by dividing the 7.5 GHz broad frequency
spectrum of UWB into sub bands. Baseband portion of UWB
Transmitter is modeled in this paper which proves to be helpful
in the evaluation of various parameters of UWB.
I. INTRODUCTION
After the allocation of 7.5 GHz spectrum by FCC in
February 2002, great efforts were put on the standardization of
UWB. Recently two architectures are followed as worldwide
standards in developing the UWB products. One is based on
the MBOFDM structure which is supported by Wi Media
Alliance and ECMA and other is based on the Direct Sequence
Approach which is supported by IEEE 802.15.4 Task Group as
discussed in [1].
UWB due to its wide bandwidth provides wealth of
advantages as compared to any other communication system.
Also due to its MBOFDM infrastructure its become able to
fulfils the requirement of digital data at a very high data rate
which is one of its promising feature.
In multi-band OFDM approach, UWB frequency spectrum
is divided into fourteen smaller sub bands, each of 528 MHz
which is further grouped into six bands each of which
comprises of three sub bands and the fifth one consists of two
sub bands as see in Fig. 1.528 MHz which is further grouped
into six bands each of which comprises of three sub bands and
the fifth one consists of two sub bands as see in Fig. 1.
Rest of the paper is organized in the following manner:
Section 2 describes the brief overview on the working of the
Baseband portion of the Transmitter. Section 3 gives the
modeling description of PHY Layer and last Section comprises
of the conclusion and future work.
II. WORKING OF BASEBAND PORTION OF UWB PHY LAYER
Baseband Portion of UWB PHY Layer is shown in Fig. 2.
Data from MAC is coming to side stream scrambler which
function is to randomize the data stream to remove repeated
patterns and spaces, after which incoming data are encoded to
reduce the bit error rate. The main purpose is to correct the
error that are arises due to the channel, convolutional encoder
is suitable for this purpose with coding rate of 5/8 which is
acquired by puncture ring some data. The stream of data then
shall be interleaved prior to modulation to provide robustness
against burst of errors.
After coding and interleaving serial binary data divided into
group of two bits which is converted into complex valued
constellation points which become input to the IFFT which is
the core of baseband portion of transmitter. A 128 point IFFT
is used to create 122 subcarriers out of which 12 are pilot
subcarriers, 100 data subcarriers and 10 are guard subcarriers,
five at each end. The rest six are set to null subcarriers. To
compensate for multipath propagation and to eliminate ISI a
Zero pad suffix of length 37 is added.
III. UWB MODELED LAYER DESCRIPTION IN MATLAB
Matlab combine with Simulink become a very powerful
tool to modeled any communication system. In this paper we
modeled a Baseband portion of an UWB Tx PHY Layer which
support data rate up to 200 Mbps. Below we describe the
modeling of each block of Baseband Transmitter in detail.
A. Scrambler
A scrambler is a device that manipulates a data stream
Proceedings of 2009 IEEE Student Conference on Research and Development (SCOReD 2009),
16-18 Nov. 2009, UPM Serdang, Malaysia
978-1-4244-5187-6/09/$26.00 2009 IEEE
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1569241621-2

before transmitting. The purpose of scrambling is to eliminate
the long sequences of 1s and 0s. In UWB PHY Layer a side
stream scrambler is used to eliminate 1s and 0s from the data
which come from MAC Layer.
In Matlab there is a built in block of scrambler with a
parameter of scramble polynomial and initial states. Scramble
polynomial is defined by (1), and the initial states represent
the states of scrambler register when simulation starts.

g(D) = 1 + D
14
+ D
15
(1)

B. Convolutional Encoder
In the proposed design of our model of UWB for 200 Mbps
according to the defined standard the code rate is 5/8 which is
obtained by combining five encoder with a rate of 1/3 (known
as mother rate) and by puncturering some output bits. The
constraint length parameter k is 7. The generator polynomial
define for UWB are g0 = 133
8
, g1 = 165
8
and g2 = 171
8
, these
numbers are in octet system which is converted to binary
number system where in binary number if bit is 1 then it shows
the connection of that register with modulo addition and if bit
is 0 then register is not connected with shift registers.

The Convolutional Encoder block in Matlab has a
parameter of Trellis structure which is define by poly2trellis
command which has two arguments constraint length and code
generator polynomial which is defined above. Poly2trellis
command create a trellis diagram which is best representation
for convolutional encoding.

C. Puncturer
The principle of puncturing is a process by which a few
parity bits are deleted in order to improve the code rate. In
Matlab the puncture block creates an output vector by
removing selected elements of the input vector and preserving
others.

If Puncture vector (k) = 0, then the kth element of the input
vector does not become part of the output vector and If
Puncture vector (k) = 1, then the kth element of the input
vector is preserved in the output vector.
D. Interleaver
In MB-OFDM system we perform two types of
interleaving: symbol interleaving and tone interleaving. In
Symbol interleaving bits of stream are interleaved over three
OFDM symbol to acquire different level of frequency diversity
because each OFDM symbol is transmitted in different
frequency bands. The symbol interleaver works on 3N
CBPS
bits
where N
CBPS
is the number of coded bits per OFDM symbol
which in our case is 200. If A (i) and B (j) represent the input
and output bits of the symbol interleaver respectively at
position j, the relationship between the two is given by;

B(j) = A{ floor( i/N
CBPS
) + 3mod( i, N
CBPS
) } (2)

Where i, j = 0, 1, 2 .N
CBPS
.
The output B (j) from symbol interleaver is passed through
tone interleaver. Tone interleaver is then used to interleave bits
in each OFDM symbol to exploit frequency diversity across
tones and provide robustness against narrow band interferers. If
C (i) and D (j) represents inputs and outputs of tone interleaver
respectively, the relationship between them is given by;

D(j) = C{ floor( i/N ) + 10mod( i, N ) } (3)

Where N = N
CBPS
/10
i, j = 0, 1, 2, N
CBPS


In Matlab, block of interleaver is modeled by using block
interleaver block which arranges the incoming data without
omitting any data sample. The pattern of sequence which we
obtained by solving above equations is placed in the parameter
box of Block Interleaver block.

E. Constellation Mapper
UWB System for 200 Mbps data rate use QPSK as a sub
carrier modulator. The serial binary data from the interleaver
shall be grouped into two bits and converted into complex
numbers representing QPSK Constellation points. The
conversion shall be performed according to the Gray-coded
constellation mappings. Matlab has built in QPSK baseband
modulator block with parameters Input type, Constellation
ordering and phase offset which we set Bit, Gray and pi/4
respectively in our case.

F. Construction of Data Sub Carriers
Since Data carriers from QPSK Modulator is come in the
form of [300x1] Matrix but our requirement is [100x1] Matrix
because an OFDM Symbol consist only 100 sub carriers
therefore this block is used to extract [100x1] Matrix. Data
from QPSK Block is given to Reshape Block which functions
are to change the dimensions of input matrix into the desired
form. Output from this block is appearing in the form of
[100x3] Matrix which is then submits to Multiport Selector
Block from which we extract three [100x1] Matrix. It is then
sent to Merge Block which reorder these three [100x1] Matrix.
Above procedure is depicted in Fig. 3. Now Data Carriers are
ready to enter into the Construction of IFFT signal Block.
30
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1569241621-3

Figure 3. Construction of Data Sub Carrier Block
G. Construction of IFFT Signal Block
This Block consists of many sub blocks. In this block signal
is prepared before given it to the IFFT Block. First Operation
which we done here is the indexing of Data Sub carriers
according to the defined standard as given in [1] which is
achieved by again using Multiport Selector Block. Pilot, Guard
and Null Sub Carriers Block are then defined by using
Constant Block of Matlab, then by using the Matrix
Concatenate Block we assembles all these signals into one
Matrix with the dimensions of [128x1]. UWB Symbol is now
ready to enter into the IFFT Block. Above procedure is
depicted in Fig. 4.

H. IFFT Block
It is the built in block of Matlab with following important
parameters; Twiddle Factor Computation, Input is in Bit
reversed order, Divide output by FFT Length and Inherit FFT
Length from input dimensions. By only setting their parameter
according to our requirement get desired results.

I. Zero Pad Block
From IFFT Block, we get [128x1] Matrix since our desired
UWB Symbol consists of [165x1] symbols; therefore to create
a [37x1] matrix of complex values we use complex command
of Matlab which generates [37x1] matrix of complex zeros
values.


Figure 4. Construction of IFFT Signal Block
J. Assembler Block
Matrix Concatenate Block is used to concatenate [128x1]
Matrix which comes from IFFT and [37x1] Matrix which
comes from Zero Pad Block to create a [165x1] Matrix of an
UWB Symbol.

K. Separation of Real and Complex Value Block
Complex to Real-Imag Block are used to separate the complex
values matrix into Real and Imaginary Matrix so we can easily
match our result from standards. Fig. 5 shows the model UWB
Layer.

L. Results
Simout Block is used to get the simulation result in the Matlab
Workspace from where this data is matched from the output
data given in [2]. Since our result is matched with the output
result of [2] which verifies the modeling of a System.

IV. CONCLUSION
By only changing the parameters of a system, we can modeled
this layer for many data rates which UWB supports. Also the
modeling of UWB System gives opportunity to observe
various factors which become helpful in the ASIC deployment
of a System in near future.

REFRENCES
[1] ECMA 368-High Rate Ultra Wideband PHY and MAC Standard. -
[s.l.] : ECMA. - Vol. 3rd Edition.
[2] High Level Modeling of an Ultra Wide-Band Baseband
Transmitter in MATLAB ( in press) [Conference] / auth. Waqas
Ali Khan Talha Ali Khan, Shahid Abbas and Muhammad Arif //
ICET 2009. - Islamabad : IEEE, 2009.
[3] D. M. W. Leenaerts. (2006). Transceiver Design for Multiband
OFDM UWB. EURASIP Journal on Wireless Communications
and Networking.
[4] MATLAB 7, The Language of Technical Computing. (n.d.).
Retrieved from
http://www.mathworks.com/applications/tech_computing/technical
_literature.html
[5] A Tutorial on Convolutional Coding with Viterbi Decoding,
Spectrum Applications. (n.d.). Retrieved from
http://home.netcom.com/~chip.f/viterbi/tutorial.html
[6] A. Batra et al. (March2003). Multi-band OFDM Physical Layer
Proposal for IEEE 802.15.3 Task Group 3a.
[7] Fixed-Point Modeling in an Ultra Wideband (UWB) Wireless
Communication System. (2004, May ). MATLAB Digest .
[8] Fredrik Kristensen, Peter Nilsson, Anders Olsson. (n.d.). Flexible
Baseband transmitter for OFDM. Retrieved from
www.imec.be/pacwoman/publications/WP8- Lund-CSS03-11-07-
2003-V1.0.pdf
[9] Implementing WiMax OFDM Timing and Frequency Offset
Estimation in Lattice FPGAs. (2005). White papers .
[10] Min-Su Kim, HoJun Kim, Jong Tae Kim,. (2008). High-level
Modeling of UWB PHY for IEEE 802.15.4a. International
Conference and Hybird Information Technology.
[11] Nishant Kumar. (2004). MAC and PHY Layer Design for Ultra
Wide Band Communications. Master Thesis, Virginia Polytechnic
Institute and State University, Electrical and Computer
Engineering.

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1569241621-4

[12] Xu Jinsong, Lu Xiaochun, Wu Haitao, Bian Yujing, Zou Decai,
Zou Xialong,Wang Chaogang. (2008). Implementation of
MBOFDM Transmitter Baseband Based on FPGA. Circuits
and Systems for Communications, 2008. ICCSC 2008. 4th IEEE
International Conference, (pp. 50-54). Shanghai.












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