Closed loop control of multilevel inverters

Akash Kushwaha1, Avinash Kumar2

Akash Kushwaha, Research Scholar , Electrical and Electronics Department, COER, Roorkee, Uttarakhand
Technical University, UK , (Email: kushwaha.akash9654@gmail.com)

Avinash Kumar, Research Scholar , Electrical and Electronics Department, COER, Roorkee, Uttarakhand
Technical University, UK Abstract - Modern industries functions with high power equipments which works on the power levels of MW. Semiconductor switching circuitry presently available cannot be connected to these levels of voltages directly. Thus multilevel inverter provides a solution to work with the high voltage levels. This paper includes a study of various types of multilevel inverters i.e. Diode clamped type, capacitor clamped type (flying capacitor) and H bridge type(cascade) and the closed loop control technique(by using PI controller) for the stable output with respect to the changes in input. The use of multilevel inverter itself shifts the harmonics present in the output to higher voltage levels which are easily removable by low pass filters. Thus it maintain high quality power with high efficiency. Closed loop control keeps the output at the preset level. Modeling of the multilevel inverters is done using MATLAB/SIMULINK. Keywords - Closed loop control, Total harmonic distortion, multilevel inverter, Pulse width modulation, Simulation. I. Introduction power conversion ,without any assistance from the other circuits at any number of levels automatically. Pulse Width Modulation (PWM) is the most common method employed for the control of multilevel inverters. Fixed DC is provided as input to the inverter and the controlled AC output is obtained by controlling the on and off time periods of the inverter components. This method of control is termed as Pulse Width Modulation (PWM) control. Numerous modulation techniques have been introduced like Sinusoidal Pulse Width Modulation (SPWM), Space Vector Pulse Width Modulation (SVPWM) Selective Harmonic Elimination Pulse Width Modulation (SHE-PWM). Among all techniques Sinusoidal Pulse Width Modulation (SPWM) technique is used in this paper. II . Inveter Topologies A multilevel inverter consists basically of an array of power semiconductors and converters, which produce an output voltage of stepped shape by connecting its output terminals to more than one different voltage source. The result is a voltage waveform with lower distortion and less voltage stress across the power semiconductors.

Multilevel Inverter has become the area of interest for the research in the recent time. The various significant advantages provided by these topologies over the conventional inverters like higher voltage level working, output voltage harmonics reduction and reduction in the losses makes them preferable over the latter. Besides these benefits , it also enables the use of renewable energy sources. The attractive feature of the multilevel inverter is the staircase waveform which provides the easiest of ways to reduce the harmonics and provides greater efficiency in the high voltage power conversion[1]. The economical limit of the staircase waveform till now is of forty nine levels and above it, the complexity of the circuitry with the increase in cost because of the use of semiconductor devices doesnt allow the increase in the working levels. Various topologies used in the multilevel inverter includes diode clamped or Neutral Point Clamped (NPC), capacitor clamped (flying capacitor) and H bridge (cascade) type. The generalized multilevel topologies can balance each voltage level by itself regardless of load characteristics, reactive or active

There are various types of multilevel inverter topologies. Here we will discuss about Diode clamped, Capacitor clamped and H bridge type. A . Diode Clamped Inverter Among different topologies, Diode clamped multilevel inverter is the most commonly used. In this topology the diode is used as the clamping device to clamp the dc bus voltage to achieve steps in the output voltage waveform. An m-level diode clamped inverter typically consists of m-1 capacitors on the dc bus which produces m levels of phase voltage. The diode clamped inverter produces (m-1)/2 levels above and below the zero level. If one assumes that the rating of the diodes is much more the same as the rating of the main switches in the inverter, a problem will arise with the diode clamped inverter and the number of diodes required in the circuit will increases with the number of levels. Let us consider that the switch chain from the positive top side, to the output connection. Having half of the total number switches exist either in the top or bottom half of the switch chain as this will corresponds to m-1 switches. So if one has a chain of m-1 switches then there will be m-2 connections in between the switches. The various diode chains are being connected to all these connections points. Each of these diode chains will stop on a switch junction point in the bottom half of the inverter totem pole. Each diode chain has to bear the total capacitor voltage such as assuming that the diode voltage rating is the same as the switch rating then this would mean that each diode chain has to consist of m-1 diodes. As a result the total number of diode is: Number of diodes = (m-1) (m-2) This is also called as Neutral Point Clamped( NPC) type multilevel inverter. Here we have shown five level inverter.the basic circuit of the invereter is shown in Fig 1.The basic functioning of the inverter is same as explained above. Various combination of switches are open at various time duration to give the output pulse. For output voltage level +2Vc, switches of upper half are open i.e. mos 1, mos 2, mos 3 and mos 4. Fig. 2 Output Waveform of Five level Diode Clamped Multilevel Inverter B. Capacitor Clamped Multilevel Inverter The structure of this inverter is similar to that of the diode-clamped inverter except that instead of using clamping diodes, the inverter uses capacitors in their place. The circuit topology of the flying capacitor

Fig. 1 Diode Clamped Multilevel Inverter For output voltage level +Vc, switches mos 2, mos 3, mos 4 and mos 5 are closed. For output voltage 0V, switches mos 3, mos 4, mos 5 and mos 6 are closed. Similarly, for Vc voltage level, switches mos 4, mos 5,mos 6 and mos 7 are closed. Finally for -2Vc output voltage, switches mos 5, mos 6, mos 7 and mos 8 are closed[1]. The output waveform thus obtained after simulation is shown in Fig 2.

multilevel inverter is shown in Fig 3. This topology has a ladder structure of dc side capacitors, where the voltage on each capacitor differs from that of the next capacitor[6]. The voltage increment between two adjacent capacitor legs gives the size of the voltage steps in the output waveform.

Fig 5 Nine level H bridge Multilevel Inverter The resulting phase voltage is synthesized by the addition of the voltages generated by the different cells. Each of the single-phase full-bridge inverter generates three voltages at the output: +Vc , 0, and Vc . This is made possible by connecting the capacitors sequentially to the ac side via the four power switches. The resultant output ac voltage waveform swings from + 4Vc to -4Vc with nine levels, and the staircase waveform is nearly sinusoidal, even without filtering[2][3].

Fig 3 Simulation circuit of five level capacitor clamped Multilevel Inverter The voltage synthesis in a five-level capacitorclamped converter has more flexibility than a diodeclamped converter .The output waveform obtained in the capacitor clamped multilevel inverter is shown in Fig 4.

Fig 6 Output Waveform of Nine level H bridge Multilevel Inverter Fig. 4 Output waveform of Capacitor clamped five level Multilevel Inverter C. H Bridge type Multilevel Inverter A different inverter topology is introduced in later years, which is based on the series connection of single-phase inverters with separate dc sources. Fig 5 shows the power circuit for one phase leg of a ninelevel inverter with four cells in each phase. III . Multilevel Inverter PWM Modulation Techniques Sinusoidal PWM (SPWM) can be classified according to carrier and modulating signals. This work use the intersection of a sine wave with a triangular wave to generate firing pulses. There are many alternative strategies to implement this technique.

One such method is Phase Opposition Disposition (POD) PWM where the carriers above the zero reference point are in phase but shifted by 180 from those carriers below the zero reference point. Alternative Phase Opposition Disposition (APOD) PWM where each carrier band is shifted by 180 from the adjacent bands. In Phase Disposition (PD) PWM all the carriers are in phase. In Phase Shift PWM (PSPWM), all carrier signals have the same amplitude and frequency but they are phase shifted by 90 degrees to each other. Carrier Overlapping PWM (COPWM)has all carriers with the same frequency and same peak to peak amplitude are disposed such that the bands they occupy overlap each other. In Variable Frequency PWM (VFPWM), carriers have the variable frequency and same amplitude each other. The main difference between the above mentioned switching strategies is the shape of the undesired harmonics spectrum. In our paper, we have used In phase disposition technique of PWM which uses a triangular wave as the repeating signal and a sinusoidal waveThe Fig 7 shows the combinational triangular waves pattern of frequency 1000hz and sinysoidal wave of frequency 50 hz[4][7].

Fig. 8 Gate triggering signals in the In phase disposition PWM technique The gate signal generator circuit is shown in Fig 9.

Fig 9 Gate triggering circuit for In phase disposition PWM technique The output waveform of the multilevel inverter are shown in Fig 10(a)[8], 10(b) and 10(c)[9].

Fig. 7 Sinusoidal and triangular waveform used for the In phase disposition techniques PI controller is used for the closed loop control in this paper. A PI Controller (proportional-integral controller) is a special case of the PID controller in which the derivative (D) of the error is not used. PI controllers are used widely for motion control systems. They consist of a proportional gain that produces an output proportional to the input error and an integration to make the steady state error zero for a step change in the input. The resultant gate waveform obtained from the comparison between the two waves is shown in fig 8[5]. Fig 10(b) Output waveform of capacitor Clamped multilevel inverter

Fig 10(a) Output waveform of Diode clamped multilevel inverter

Conference on Advanced Engineering & Technology, 10th March Chennai, ISBN: 978-93-82702-20-7

[7] K.Surya Suresh, M.Vishnu Prasad , PV Cell Based Five

Level Inverter Using Multicarrier PWM , International Journal of Modern Engineering Research (IJMER) , Vol.1, Issue.2, pp-545-551 , ISSN: 2249-6645

[8] Ravi. A, Manoharan. P.S, Closed loop control of Diode

Clamped Multilevel Inverter with Integrated Maximum Power Point Tracking for Grid Connected Photovoltaic Application, PRZEGLD ELEKTROTECHNICZNY, ISSN 0033-2097, R. 89 NR 10/2013

Fig 10(c ) Output waveform of H Bridge multilevel inverter IV .

[9] P.Thirumuraugan, R.Preethi, Closed Loop Control of

Multilevel Inverter Using SVPWM for Grid Connected Photovoltaic System, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering Vol. 2, Issue 4, April 2013, ISSN (Print) : 2320 3765,ISSN (Online): 2278 8875

Conclusion

Multilevel inverter technology has emerged recently as a very important alternative in the area of high power medium- voltage energy control. In this paper the most common multilevel inverter topologies has been reviewed. Fundamental multilevel inverter structures and modulation paradigms have been discussed. Multilevel inverter modulation through pulse width modulation (PWM) technique and its closed loop control has been studied. The closed loop control of the multilevel inverter is done using a PI controller. The entire work is simulated using MATLAB/SIMULINK software.

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