Design of 16*16 bit Multiplier using Ancient Indian Mathematics For High Speed Applications

Abhijeet Kumar 1, Ashok Kumar 2, Ashish Gupta 3 2 Assoc. Prof., ACE, MIT AP!" 1, 3 #ecturer, MMEC, MM!, M!##A$A

Abstract- Multiplication is elementary mathematical operations extremely important for core

computing process. To keep pace with the technology, high speed applications require faster methods of multiplication architecture. This paper reports a new faster algorithm for multiplication based on ancient Indian mathematics, called Vedic Mathematics. The design for the architecture of 1 !1 bit multiplier is proposed and described using V"#$ hardware description language. The code description is simulated using Model%im %& '.(f and synthesi)ed using I%& *ilinx +.,i for the -./0 de1ice %partan *23%'44e5fg3,4, %peed /rade56. The synthesis showed reduced time delay for the multiplier. The proposed design is also compared with other existing methods, resulting in impro1ed efficiency in both speed and area. I. Introduction With the rapid development and wide application of computer technology, high performance applications have become extremely popular in modern computer systems, requiring enhanced computation capabilities at low cost and power consumption. Also, in contemporary signal processing and communication applications, a high throughput rate and numerical accuracy is often demanded. Since multiplication is the most critical function to be carried out by the processor which requires more number of steps for the computation, and limits the overall performance of the system. An improvement in the multiplier architecture is therefore in need for high speed applications. There are several algorithms for multiplication such as: ooth, carry! save, array, modified ooth and Wallace tree. A large number of possible architectures have been developed in accordance with these algorithms indicating good performance efficiency. "n an array multiplier, a combinational circuit is utili#ed to multiply two binary numbers. The architecture resembles an array which is also an efficient layout of combinational architecture. All of the product bits are obtained simultaneously resulting in a faster method. $owever, it requires a large number of gates and for this reason it is less economical. Another method to have improved efficiency of multiplier is the arrangement of adders, that is, tree method. This paper presents a novel architecture for %&'%& bit multiplier attempting to provide the solution of the aforesaid problems by adopting the aphorisms of (edic )athematics called *rdhva Tirya+bhyam and duplex property. This paper is organi#ed in the following way: Section "" presents related wor+ done on the implementation of (edic Sutras. Section """ provides the brief description of the (edic )athematics and its aphorisms or sutras. Section "( provides an overview of the multiplication method and architecture of the proposed multiplier. Section ( demonstrates the results from the synthesis tool and the comparative study of the proposed architecture and other existing architectures. Section (" concludes the paper. II. Related Work Similar wor+ was presented by ,hidgup+ar et. al -%. for multiplication of two decimal numbers using (edic Sutra. ut the design was implemented in assembly language on /0/1 and /0/& microprocessors for the exploration in 2igital Signal 3rocessing. Another wor+ reported in the literature by Thapliyal et. al -4. was the development of a time!area!power efficient multiplier architecture based on (edic )athematics. The design implementation was described in both at gate level and high level 5T6 code using (erilog hardware description language and tested using (eriwell Simulator. Another wor+ discussed by Singh et. al-7. gave an introduction of various (edic sutras and their specific utility and proposed a general method to perform any multiplication. This wor+ attempts to formulate an interactive general strategy for the design and hardware implementation of an /'/ bit multiplication method based on principles of (edic )athematics. III. Vedic Mathematics Vedic mathematics is the name given to the ancient system of mathematics, or, to be precise, a unique technique of calculations based on simple rules and principles with which any

mathematical problem can be solved 8 be it arithmetic, algebra, geometry or trigonometry. The system is based on %& (edic sutras or aphorisms, which are actually word formulae describing natural ways of solving a whole range of mathematical problems. (edic mathematics was rediscovered from the ancient "ndian scriptures between %9%% and %9%/ by Sri harati :rishna Tirtha;i <%//=!%9&0>, a scholar of Sans+rit, mathematics, history and philosophy -1.. $e studied these ancient texts for years and, after careful investigation, was able to reconstruct a series of mathematical formulae called sutras. (edic mathematics is the easy and natural way to do mathematics. "t helps increase speed, accuracy and analytical power and answers appear in one line The Multiplication Method ?ne of the aphorisms of (edic )athematics implied for multiplication is *rdhva Tirya+bhyam <(ertical and ,rosswise> which is also the foundation of the proposed design. "t is based on a novel concept through which the generation of all partial products can be done with the concurrent addition of these partial products. The parallelism in generation of partial products and their summation is obtained by vertical and crosswise multiplication and addition. According to this algorithm, ='= bit multiplication can be carried out in the following way: @irstly, least significant bits are multiplied which give s the least significant bit of the product <vertical>. Then, the 6S of the multiplicand is multiplied with the next higher bit of the multiplier and added with the product of 6S of multiplier and next higher bit of the multiplicand <crosswise>. The sum gives second bit of the product and the carry is added in the output of next stage sum obtained by the crosswise and vertical multiplication and addition of three bits of the two numbers from least significant position. Aext, all the four bits are processed with crosswise multiplication and addition to give the sum and carry. The sum is the corresponding bit of the product and the carry is again added to the next stage multiplication and addition of three bits except the 6S . The same operation continues until the multiplication of the two )S s to give the )S of the product. To ma+e the methodology more clear, an alternate illustration is given with the help of line diagrams in figure % where the dots represent bit B0C or B%C. According to this example, the digits on the two sides of line are multiplied and the result is added in the previous carry. When more than one line is in the step, all the results are added with the previous carry and the process is thus continued. "nitially, the previous carry is equal to #ero. A unit place digit of addition result is one of the digits in the answerD this is derived from full multiplication, while the remaining digits act as a carry. "f the numbers of the digits are not same in the multiplier and multiplicand, then the bigger number has to be determined. The number of digits then needs to be counted. The smaller number should be pre!pended with 0s so that both numbers will be of the same digits -&.. Proposed Architecture @rom the previous discussion, it is clear that the basic building bloc+s of this multiplier are one bit multipliers and adders. ?ne bit multiplication can be performed through two input AA2 gate and for addition, full adder can be utili#ed. The /x / bit multiplier can be structured using =E= bit bloc+s as shown in figure 4. "n this figure the / bit multiplicand A can be decomposed into pair of = bits A$!A6. Similarly multiplicand can be decomposed into $! 6. The %& bit product can be written as: 3F A x F <A$!A6> x < $! 6> F A$ x $GA$ x 6 G A6 x $G A6 x 6 The outputs of =E= bit multipliers are added accordingly to obtain the final product. Thus, in the final stage two adders are also required. Architecture for 16x 16 bit multiplier The %&E%& bit multiplier can be structured using /E/ bit bloc+s as shown in @ig 7. "n this @ig 7 the %& bit multiplicand A can be decomposed into pair of / bits A$!A6. Similarly multiplicand can be decomposed into $! 6. The outputs of /E/ bit multipliers are added accordingly to obtain the 74 bits final product. Thus, in the final stage two adders are also required. V. Results and omparisons The main ob;ective of any design to be implemented on @3HA is the minimum chip area together with reasonable speed. "n this study, the algorithm for the proposed design is described in ($26 $ardware 2escription 6anguage and the logic is tested in )odelSim SI 1.Jf simulator. The simulated design is synthesi#ed to gate level, and optimi#ed for speed and area using Eilinx

family for the device E"6"AE: S3A5TAA 7I:E,7S100e fg740D Speed Hrade: !=. The proposed architecture shows a faster response than ooth, Array and Wallace tree multipliers which are implemented on the same device. The results for %&E%& bit multipliers are shown in the table. "t has been found that for %&E%& bit multiplication, (edic multiplier is the fastest. @or the Eilinx, Spartan 7I family the maximum combinational path delay is found to be 74./10 ns while it is =7.9=& ns for array, =J.0=& ns for Wallace tree, and 7J.0=% ns for ooth. As far as the device chip area is concerned, the proposed (edic multiplier demonstrates a good reasonable area utili#ed of the @3HA device. The implementation ta+es a total of J99 logic cells which is better evidence to an efficient implementation. A comparison histogram of timing delays of the multiplier for %&E%& bit is given in fig =. The result shows that (edic multiplier dominates over Array, ooth and Wallace tree multipliers. VI. onclusions The need for high speed processing has been increasing as a result of expanding signal processing and computer applications. Since in performing multiplication a computer spends a considerable amount of its processing time, an improvement in the speed for performing multiplication is highly required. ,ompared to other conventional methods, (edic mathematical methods, derived from ancient systems of computations, are computationally faster and easy to perform. This wor+ concludes that a %&E%& multiplier based on (edic algorithms is more efficient in performance than the array, Wallace tree and ooth multipliers. The performance parameters are timing delay and the area of the target device utili#ed in the design. The speed improvements are gained by paralleli#ing the generation of partial products with their concurrent summations. "t is demonstrated that this design is quite efficient in terms of silicon areaKspeed. Such a design should enable substantial savings of resources in the @3HA when used for imageKvideo processing applications. Thus, we have shown that the proposed design of the multiplier successfully implemented on @3HA.

References
-%. ,hidgup+ar, 3. 2. and :arad, ).T.,LThe "mplementation of (edic Algorithms in 2igital Signal 3rocessingL, Hlobal ,ongress on Ingineering Iducation, (ol. /, Ao.4, 400=. -4. Thapliyal, $. and Arabnia $.5., MA time!Area!3ower Ifficient )ultiplier and Square Architecture ased on Ancient "ndian (edic )athematicsL. -7. Singh, ., :umar, 6. and 5ana, 2.5., M2esign and $ardware "mplementation of / bit ' / bit )ultiplication AlgorithmL. -=. S;oholm, S. and 6indh, 6., M($26 for 2esigners, 3rentice!$all 3T5 <%99J>. -1. Nagadguru Swami Sri harati :risna Tirtha;i )ahara;a, Vedic Mathematics7 %ixteen %imple Mathematical -ormulae from the Veda. 2elhi <%9&1>. -&. (edic)aths.org <400=> http:KKwww.vedicmaths.org -J. 2eschamps, Nean!3ierrie and Sutter, 2. Hustavo, %ynthesis of 0rithmetic 2ircuits, -./0, 0%I2 and &mbedded %ystems, Nohn Wiley O sons "nc. 3ublication <400&>. -/. 3erry, 2ouglas, V"#$ .rogramming by &xample, )cHraw $ill 3ublication <4004>. -9..2e )ori,5., and ,ardin, 5.:P "terative 3arallel )ultipliers ased ?n )ultiplexersP, Signal 3rocessing,%9/=,&,pp,4%7!447. -%0. 2e )ori,5., and ,ardin, 5.:P A 5ecursive Algorithm for inary )ultiplication and "ts "mplementationP, A,) Trans. ,omput. Syst., %9/1, 7, <=>, pp, 49=!7%=. -%%. (ishal (erma and $imanshu Thapliyal , M$igh Speed Ifficient A E A it )ultiplier ased ?n Ancient "ndian (edic )athematicsL,3roceedings of the 4007 "nternational ,onference on (6S" <(6S"07>, 6as (egas Aevada, Nune 4007. -%4. $imanshu Thapliyal and (ishal (erma ,M$igh Speed Ifficient SignedK*nsigned A E A it )ultiplier ased ?n Ancient "ndian (edic )athematicsL proceedings of the Jth "III (6S" 2esign O Test Wor+shop, angalore, August 4007. -%7. eiu, M)icroprocessor and a digital signal processor including adder and multiplier circuits employing logic gates having discrete and weighted inputs8, *nited States 3atent, &,1%&,77%, @ebruary =, 4007. -%=. A.3. Aicholas, :.5 Williams, N. 3ic+les, Application of *rdhava Sutra, Spiritual Study Hroup, 5oor+ee <"ndia>, %9/=. -%1. A.3. Aicholas, :.5 Williams, N. 3ic+les, 6ectures on (edic )athematics,Spiritual Study Hroup, 5oor+ee <"ndia>,%9/4.

!i"ure 1# $ine %ia"rams for four bits.

!i"ure &# ' ( ' bit %ecomposed Vedic Multiplier

50 40 30 20 10 0 Delay

Vedic Mult Array Mult Wallace Tree Booth Mult

!i"ure )# omparison of multipliers *ith respect to time dela+ in ,partan -. !P/A

!i"ure -# 16 ( 16 0its %ecomposed Vedic Multiplier Table I omparison Results of the Multiplier
3arameters )aximum combinational path delay <ns> Aumber of Slices Aumber of = input 6*Ts ,ell *sage J99 119 J&4 901 (edic )ultiplier 74./10 Array )ultiplier =7.9=& Wallace Tree )ultiplier =J.0=& ooth )ultiplier 7J.0=%

77/ &4/

41& =91

7%0 1J4

70% 194