Influence of metal coverage on transistor mismatch and variability

in copper damascene based CMOS technologies

Nicole Wils, Hans Tuinhout, Maurice Meijer
NXP Semiconductors Central R&D/Research
High Tech Campus 37, 5656AE Eindhoven, The Netherlands
Abstract
This paper summarizes a comprehensive study on the effect
of asymmetrical metal coverage on matching performance
for a 45 nm copper damascene based CMOS process. We
demonstrate that random mismatch fluctuations are not
affected by metal layout asymmetries and we provide
valuable new insights about the magnitude of systematic
mismatches that can be expected due to asymmetrical
layouts and CMP tiling. For the first time we also present
results on the impact of temperature increases on both
systematic as well as random drain current mismatches.
Introduction
Matched devices (supposedly identical IC elements) are
essential for accurate analogue and mixed signal circuits.
Design for good matching not only requires that the
transistor area is optimized to obtain required matching, but
also the complete layout of the devices should be identical
in order to avoid systematic mismatch effects (e.g. due to a
difference in well proximity effect or STI stress effect in
case of MOS transistors [1,2]). Moreover, the environment
near matched devices should be as symmetrical as possible.
For aluminium based metallization processes it has been
shown that asymmetric metal coverage of matched MOS
devices can result in significant drain current mismatch on
the order of a few percent [3]. This was attributed to local
mechanical stress differences. In advanced CMOS processes
(120 nm and beyond), Al-metallization is replaced by
copper damascene metallization, which is essentially
different in terms of deposition temperatures and material
characteristics. This could potentially result in a
substantially different impact on mismatch and variability.
This study presents a dedicated set of matched pair test
structures to study the effect on matching of Cu-damascene
based metallization in a 45 nm state-of-the-art technology.
The effect on both systematic as well as on random drain
current mismatch is investigated. Furthermore we tested the
impact of temperature increase on these mismatches to
further assess a possible mechanical stress effect.
Test structures and analysis
Test structure layout
Our study is based on a new set of 45 nm CMOS technology
node matched pair test structures. The layout of the basic
matched pair test structure and probe pad configuration is
shown in Figure 1. Extreme care was taken to assure that all
possible (undesired) effects due to asymmetric metallization
layout and unequal access resistances are avoided. Also note
the relatively large separation between the STI edge and the
gated area to mitigate STI stress effects [1]. A special set of
matched pair test structures is used for this metal coverage
study. MOS transistor dimensions are chosen relatively
large (W/L=2.4/4), for two reasons: 1) large transistors are
representative for relatively well matching device pairs in
high precision analogue MOS circuits, and 2) dimensions
should be large enough to avoid that natural random dopant
fluctuations overshadow the investigated systematic
mismatch effect. An intentional asymmetry in the metal
coverage between both transistors of the pair is applied
(Figure 2): the left transistor of the pair (T
1
) has no metal
coverage, while the right transistor (T
2
) is partly or
completely covered with metal. To avoid undesired metal
coverage on top of the transistors due to CMP dummy tile
insertion, no-tile masks are placed over the transistor
areas. Note that the metal plate is connected to the source; a
dummy metal bar is also added to T
1
to improve the layout
environment symmetry. The metal on top of T
2
has been
varied in shape (plate, lines, tiles) as well as in level (metal
1, 2, 3 or 4), see Table 1. For one variant, the no-tile masks
were omitted to assess the impact of automatic tiling. As
reference, a completely symmetrical matched pair without
metal coverage is available. As with any properly designed
matched pair, the effects of parametric wafer gradients and
other process spreads are mitigated due to the relatively
close spacing. This allows for independent assessment of
microscopic device architecture fluctuations and systematic
mismatch effects due to intentional environmental
asymmetries.
182
8.2
2010 IEEE International Conference on Microelectronic Test Structures, March 22-25, Hiroshima, Japan.
978-1-4244-6915-4/10/$26.00 2010 IEEE
Figure 1: ideal MOSFET matched pair layout.
Figure 2: example of matched pair with intentional asymmetry in
metal coverage: T
2
has been covered with a metal-2 plate which is
connected to the source.
Analysis
For quick qualitative as well as proper quantitative
evaluation of our 45 nm CMOS mismatch performances we
measure complete linear region (V
ds
=50 mV) I
d
-V
gs
curves
simultaneously on both transistors of each pair. The number
of measured pairs on the wafer (population size) was 119. A
complete voltage sweep allows us to generate so called
mismatch sweeps, showing the relative drain current
mismatch median and standard deviation (_AI
d
/I
d
and
o_AI
d
/I
d
) as a function of gate voltage [1]. These sweeps
immediately reveal a possible effect on the drain current
(offset as well as fluctuations) in different operating regions,
going from weak to strong inversion. The main transistor
parameters V
t
and | were derived from the original linear
region I
d
-V
gs
curves using fixed overdrive three-point-
extractions [4]. Subsequently for each pair the V
t
difference
(AV
t
) and the relative current factor difference (A|/|) were
calculated. The median of the V
t
difference (AV
t
) and
relative current factor difference (A|/|) between TT
1
and
TT
2
are indicative for the amount of systematic mismatch
between the two transistors of the pair and thus for the
influence of metal coverage (since this is the only layout
difference between the two). The standard deviations of the
V
t
difference and the current factor difference (oAV
t
and
oA|/|) are a measure for the random mismatch
fluctuations. For intentionally asymmetric pairs, the
standard deviation may also include a component related to
the (deterministic) change of the impact of the asymmetry.
If the mechanical stress associated with the metal coverage
is not constant across the wafer, this would increase the
observed mismatch standard deviation for these pairs.
G
2
G
1
S D
2
w
e
l
l
D
1
G
2
G
1
S D
2
w
e
l
l
D
1
variant name T
2
covered with source connection
reference - -
M1 plate metal 1 plate yes
M2 plate metal 2 plate yes
M3 plate metal 3 plate yes
M4 plate metal 4 plate yes
M1 lines width = space = 70 nm yes
M2 lines width = space = 70 nm yes
M3 lines width = space = 70 nm yes
M4 lines width = space = 70 nm yes
M3/M4 grid grid of metal 3 and metal 4 lines yes
tiles small metal 1 tiles (20 X 0.40 x 0.40) no
tiles large metal 1 tiles (4 X 1.3 x 1.3) no
automatic tiling automatic tiling allowed no
Table1: list of different variants.
variant name T
2
covered with source connection
reference - -
M1 plate metal 1 plate yes
M2 plate metal 2 plate yes
M3 plate metal 3 plate yes
M4 plate metal 4 plate yes
M1 lines width = space = 70 nm yes
M2 lines width = space = 70 nm yes
M3 lines width = space = 70 nm yes
M4 lines width = space = 70 nm yes
M3/M4 grid grid of metal 3 and metal 4 lines yes
tiles small metal 1 tiles (20 X 0.40 x 0.40) no
tiles large metal 1 tiles (4 X 1.3 x 1.3) no
automatic tiling automatic tiling allowed no
Table1: list of different variants.
source connection
Gate
1
Drain
1
T
1
Gate
2
Drain
2
T
2
Metal 2
Metal 1
Poly silicon
Active
source connection
Gate
1
Drain
1
T
1
Gate
2
Drain
2
T
2
Metal 2
Metal 1
Poly silicon
Active
source connection
Gate
1
Drain
1
T
1
Gate
2
Drain
2
T
2
Metal 2
Metal 1
Metal 2
Metal 1
Poly silicon
Active
Poly silicon
Active
Results
Results at room temperature
Figure 3 shows the relative drain current mismatch
fluctuation sweeps for the reference and for the pair where
T
2
was covered with metal-1 lines. 3o error bars obtained
from bootstrapping indicate the statistical uncertainty due to
the limited population size (N=119). It is clear that over the
complete voltage range there is no significant difference
between the reference and the pair with asymmetric metal
coverage.
0.1
1
10
100
0.00 0.25 0.50 0.75 1.00 1.25
Vgs [V]
Figure 3: example of mismatch fluctuation sweeps (oAI
d
/I
d
as a
function of V
gs
) for the reference matched pair (no metal coverage)
and the matched pair where T
2
is covered with metal-1 lines. 3o
error bars indicate statistical uncertainty.
V
t
and | mismatch fluctuation values (oAV
t
and oA|/|)
for the different NMOS variants (table 1) are shown in
Figure 4. For the reference matched pair an extra data point
o

A
I
/
I
d
d
2.4/4 NMOS
V
ds
=50 mV
[
%
]
reference
M1 lines on T
2
Id(T
1
) Id(T
2
)
AI
d
/I
d
[%] =
x 200
Id(T
1
) + Id(T
2
)
0.1
1
10
100
0.00 0.25 0.50 0.75 1.00 1.25
Vgs [V]
d
d
o

A
I
/
I
[
%
]
0.1
1
10
100
0.00 0.25 0.50 0.75 1.00 1.25
Vgs [V]
d
d
2.4/4 NMOS
V
ds
=50 mV
o

A
I
/
I
[
%
]
reference
M1 lines on T
2
reference
M1 lines on T
2
Id(T
1
) Id(T
2
)
AI
d
/I
d
[%] =
x 200
Id(T
1
) + Id(T
2
)
Id(T
1
) Id(T
2
)
AI
d
/I
d
[%] =
x 200
Id(T
1
) + Id(T
2
)
183
(open triangle) has been added to show the repeatability of
the measurement (same population). From these figures we
can conclude that there is no statistically significant
influence of metal coverage on random fluctuations. This
implies that -a mechanical stress related- systematic
mismatch (if present), is homogeneous across the wafer.
Figure 4: mismatch fluctuations as a function of variant (table1).
Top: threshold voltage mismatch fluctuations (oAV
t
) and bottom:
relative current factor mismatch fluctuations (oA|/|). 3o error
bars indicate statistical uncertainty. The extra point (open triangle)
for the reference indicates the repeatability of the measurement.
The drain current mismatch median sweeps for the
reference and for the asymmetrically covered pairs with
metal-1 or metal-3 lines are shown in Figure 5. In weak
inversion, possible effects of the metal coverage on drain
current fluctuations are overshadowed by the random
fluctuations and the associated statistical uncertainty. In
strong inversion however, the metal-1 lines cause a
significant drain current offset of 0.6%. There is no
significant influence of the metal-3 lines. These results are
reflected in the current factor mismatch values. The
medians of the relative | mismatch values (A|/|) for the
different NMOS variants (table1) are presented in Figure 6.
For some variants the metal covered (right) transistor T
2
has
a significantly lower current factor | compared to the left
transistor T
1
. In particular, the first metal can cause a |
offset of up to 1.5% (metal-1 lines), but for the third and
fourth metal we must consider the effect not statistically
significant.
[
%
]
I
/
I
A

Figure 5: example of mismatch median sweeps (AI

d
/I
d
as a
function of V
gs
) for the reference matched pair (no metal coverage)
and the matched pair where T
2
is covered with metal-1 lines or
metal-3 lines. 3o error bars indicate statistical uncertainty. The
inset shows the right part of the characteristic with adjusted y-axis.
Figure 6: median of relative current factor mismatch (A|/|) as
a function of variant. 3o error bars indicate statistical
uncertainty. The extra point (open triangle) for the reference
indicates the repeatability of the measurement.
Large metal tiles have an impact comparable to the full
metal plate, which is no surprise since the four large tiles
almost completely cover the transistor area, whereas the
total coverage of the small tiles is substantially less (Figure
7). From Figure 8, which shows the median of the threshold
voltage mismatch (AV
t
) as a function of variants, we
conclude that the effect of metal coverage on the threshold
voltage of NMOS devices can be neglected for all variants.
The maximum offset (median) that is observed is limited to
1.5 mV (_V
t
=437 mV), which is significantly different
from zero, but it is still less than the random mismatch
fluctuations of 2 mV (figure 4, top).
d
d
-10
-5
0
5
10
0.00 0.25 0.50 0.75 1.00 1.25
Vgs [V]
-1.0
-0.5
0.0
0.5
1.0
0.50 0.75 1.00 1.25
reference
M1 lines on T
2
M3 lines on T
2
d
d

A
I
/
I
[
%
]
-10
-5
0
5
10
0.00 0.25 0.50 0.75 1.00 1.25
Vgs [V]
d
d
-10
-5
0
5
10
0.00 0.25 0.50 0.75 1.00 1.25
Vgs [V]
-1.0
-0.5
0.0
0.5
1.0
0.50 0.75 1.00 1.25
-1.0
-0.5
0.0
0.5
1.0
0.50 0.75 1.00 1.25

A
I
/
I
[
%
]
reference
M1 lines on T
2
M3 lines on T
2
reference
M1 lines on T
2
M3 lines on T
2
AV
t
= V
t
(T
1
) V
t
(T
2
)
2.4/4 NMOS
V
ds
=50 mV
r
e
f
e
r
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n
c
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M
1

p
l
a
t
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M
2

p
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o

A
V
t
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
AV
t
= V
t
(T
1
) V
t
(T
2
) AV
t
= V
t
(T
1
) V
t
(T
2
) AV
t
= V
t
(T
1
) V
t
(T
2
)
2.4/4 NMOS
V
ds
=50 mV
r
e
f
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n
c
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M
1

p
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M
2

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3

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A
V
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
r
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f
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n
c
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M
1

p
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2

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3

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4

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1

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2

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3

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4

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1

p
l
a
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2

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3

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a
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4

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a
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1

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2

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t
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
o

A
V
[
m
V
]
r
e
f
e
r
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n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
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M
3

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a
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4

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a
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1

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2

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o

A
|
/
|
[
%
]
0.0
0.2
0.4
0.6
0.8
1.0
r
e
f
e
r
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n
c
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M
1

p
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a
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2

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0.0
0.2
0.4
0.6
0.8
1.0
0.0
0.2
0.4
0.6
0.8
1.0
o

A
|
/
|
[
%
]
-0.5
0.0
0.5
1.0
1.5
2.0
r
e
f
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r
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c
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M
1

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t
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a
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c

A|/| [%] =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)

A
|
/
|
[
%
]
2.4/4 NMOS
-0.5
0.0
0.5
1.0
1.5
2.0
r
e
f
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r
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n
c
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M
1

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a
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i
c

A|/| [%] =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)

A
|
/
|
[
%
]
-0.5
0.0
0.5
1.0
1.5
2.0
r
e
f
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r
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n
c
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M
1

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A
|
/
|
[
%
]
-0.5
0.0
0.5
1.0
1.5
2.0
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M
1

l
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n
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s
M
2

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i
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a
u
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o
m
a
t
i
c

A
|
/
|
[
%
]
-0.5
0.0
0.5
1.0
1.5
2.0
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

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l
a
t
e
M
3

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a
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e
M
4

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M
1

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M
2

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m
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i
c

r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

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l
a
t
e
M
3

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l
a
t
e
M
4

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l
a
t
e
M
1

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s
M
2

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i
c

A|/| [%] =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
A|/| [%] =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
A|/| [%] =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)

A
|
/
|
[
%
]
2.4/4 NMOS
184
Figure 7: detail of large (left) and small (right) tiles in metal-1.
The total coverage of the small (0.4x0.4) tiles is about 50% of that
of the large (1.3x1.3) tiles. The light gray areas represent the
transistor poly silicon gate.
These results indicate that local mechanical stress reduces
the mobility of the device that is covered with metal. We
expect that the stress originates from the difference in
thermal expansion between copper and the surrounding
oxide, which takes effect during cooling down after inter-
layer dielectric deposition.
Figure 8: median of threshold voltage mismatch (AV
t
) as a
function of variant. 3o error bars indicate statistical uncertainty.
The extra point (open triangle) for the reference indicates the
repeatability of the measurement.
Results at elevated temperature
To investigate a possible impact of stress reduction at higher
chip operation temperatures, all populations were re-
measured at 125C. In Figure 9 the effect of the metal
coverage on the current factor is compared between 25C
(results from figure 6) and 125C. These results reveal that,
if there is a significant offset at room temperature, the offset
is reduced to a much lower level at 125C. In case of metal-
1 plate coverage, results at 125C even indicate a slightly
higher mobility for T
2
(metal covered) compared to T
1
(uncovered). The higher temperature clearly changes the
mechanical stress difference between both transistors of the
pair.
The influence of the higher temperature on mismatch
fluctuations for NMOS devices is presented in Figure 10
(oAV
t
) and 11 (oA|/|). For all variants including the
reference, the standard deviations of both V
t
mismatch
(figure 10) and relative | mismatch (figure 11) reduce at
elevated temperature. This is in line with results found for
65 nm devices [5].
Figure 9: median of relative current factor mismatch (A|/|) as
a function of variant. Results for T=25 and T=125C are
compared.
Figure 10: threshold voltage mismatch fluctuations as a function of
variant (NMOS). Results for T= 25C and T=125C are compared.
3o error bars indicate statistical uncertainty.
Figure 11: relative current factor mismatch fluctuations as a
function of variant (NMOS). Results for T= 25C and T=125C are
compared. 3o error bars indicate statistical uncertainty.
T=125C
T=25C
AV
t
= V
t
(T
1
) V
t
(T
2
)
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
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e
M
3

p
l
a
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e
M
4

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a
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M
1

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M
2

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3

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4

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3
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4

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a
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c

o

A
V
t
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.4/4 NMOS
T=125C
T=25C
AV
t
= V
t
(T
1
) V
t
(T
2
)
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

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l
a
t
e
M
1

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M
2

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3

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4

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3
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4

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i
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a
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o
m
a
t
i
c

t
o

A
V
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T=125C
T=25C
T=125C
T=25C
AV
t
= V
t
(T
1
) V
t
(T
2
) AV
t
= V
t
(T
1
) V
t
(T
2
)
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

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l
a
t
e
M
3

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l
a
t
e
M
4

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l
a
t
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M
1

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i
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s
M
2

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3

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4

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3
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a
u
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o
m
a
t
i
c

t
o

A
V
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
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M
3

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l
a
t
e
M
4

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l
a
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M
1

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2

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e
f
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n
c
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M
1

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l
a
t
e
M
2

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l
a
t
e
M
3

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l
a
t
e
M
4

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l
a
t
e
M
1

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i
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s
M
2

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3

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4

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3
/
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a
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o
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a
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t
o

A
V
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.4/4 NMOS
T=125C
T=25C

A
|
/
|
[
%
]
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

p
l
a
t
e
M
1

l
i
n
e
s
M
2

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n
e
s
M
3

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4

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M
3
/
M
4

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a
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t
i
l
e
s
a
u
t
o
m
a
t
i
c

-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
2.4/4 NMOS
T=125C
T=25C
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

p
l
a
t
e
M
1

l
i
n
e
s
M
2

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i
n
e
s
M
3

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4

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3
/
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4

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t
i
l
e
s
a
u
t
o
m
a
t
i
c

A
|
/
|
[
%
]
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
T=125C
T=25C
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

p
l
a
t
e
M
1

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i
n
e
s
M
2

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M
3

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4

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3
/
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4

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t
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a
u
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o
m
a
t
i
c

A
|
/
|
[
%
]
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
T=125C
T=25C
T=125C
T=25C
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

p
l
a
t
e
M
1

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i
n
e
s
M
2

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3

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4

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3
/
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4

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g
e

t
i
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e
s
a
u
t
o
m
a
t
i
c

r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

p
l
a
t
e
M
1

l
i
n
e
s
M
2

l
i
n
e
s
M
3

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s
M
4

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M
3
/
M
4

g
r
i
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s
m
a
l
l

t
i
l
e
s
l
a
r
g
e

t
i
l
e
s
a
u
t
o
m
a
t
i
c

A
|
/
|
[
%
]
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
2.4/4 NMOS
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

p
l
a
t
e
M
1

l
i
n
e
s
M
2

l
i
n
e
s
M
3

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M
4

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3
/
M
4

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r
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t
i
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s
l
a
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g
e

t
i
l
e
s
a
u
t
o
m
a
t
i
c

AV
t
= V
t
(T
1
) V
t
(T
2
)

A
V
t
[
m
V
]
2.4/4 NMOS
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

p
l
a
t
e
M
1

l
i
n
e
s
M
2

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n
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s
M
3

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4

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3
/
M
4

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i
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a
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g
e

t
i
l
e
s
a
u
t
o
m
a
t
i
c

V
t
[
m
V
]
AV
t
= V
t
(T
1
) V
t
(T
2
)

A
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

p
l
a
t
e
M
1

l
i
n
e
s
M
2

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3

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4

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3
/
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4

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a
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g
e

t
i
l
e
s
a
u
t
o
m
a
t
i
c

V
t
[
m
V
]

A
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

p
l
a
t
e
M
1

l
i
n
e
s
M
2

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3

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4

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3
/
M
4

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a
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g
e

t
i
l
e
s
a
u
t
o
m
a
t
i
c

V
t
[
m
V
]

A
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

p
l
a
t
e
M
1

l
i
n
e
s
M
2

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3

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4

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3
/
M
4

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g
e

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i
l
e
s
a
u
t
o
m
a
t
i
c

r
e
f
e
r
e
n
c
e
M
1

p
l
a
t
e
M
2

p
l
a
t
e
M
3

p
l
a
t
e
M
4

p
l
a
t
e
M
1

l
i
n
e
s
M
2

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n
e
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M
3

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4

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3
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e

t
i
l
e
s
a
u
t
o
m
a
t
i
c

V
t
[
m
V
]
AV
t
= V
t
(T
1
) V
t
(T
2
) AV
t
= V
t
(T
1
) V
t
(T
2
)

A
2.4/4 NMOS
T=125C
T=25C
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
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0.0
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0.4
0.6
0.8
1.0
2.4/4 NMOS
T=125C
T=25C
T=125C
T=25C
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
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|
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0.2
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0.6
0.8
1.0
2.4/4 NMOS
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
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0.0
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1.0
2.4/4 NMOS
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1.0
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0.0
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0.8
1.0
0.0
0.2
0.4
0.6
0.8
1.0
2.4/4 NMOS
o

A
|
/
|
[
%
]
185
For PMOS devices, similar observations as found for
NMOS devices were encountered, albeit substantially
smaller in magnitude. This is illustrated in Figure 12, where
the median of the current factor mismatch is shown as a
function of the different PMOS variants (table1), for
T=25C and T=125C. In all cases the median offset is less
than 0.5%. Also note that, although small, the effect is
opposite to the effect observed for the NMOS devices: in
case of PMOS the strained device (T
2
) has a higher current
factor (higher mobility) than the unstrained device (T
1
).
Note the similarity with the impact of STI stress [1].
Furthermore, the effect is reduced or again even reverses
sign at 125C.
Figure 12: median of relative current factor mismatch (A|/|) as
a function of variant (PMOS). Results for T=25 and T=125C are
compared. Note that the scale is different from figure 9 (NMOS).
Comparable to the NMOS devices, no statistically
significant effects of the metal coverage on the mismatch
fluctuations of the PMOS devices are seen. This is
illustrated in Figure 13 and 14, where respectively the
threshold voltage mismatch fluctuations and the relative
current factor mismatch fluctuations are shown for the
different PMOS variants. In the same graphs the results of
measurements at T=125C can be found: also for the PMOS
devices a slight reduction in fluctuations is seen at higher
temperature.
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A
V
t
[
m
V
]
T=125C
T=25C
0.4
0.6
0.8
1.0
1.2
1.4
2.4/4 PMOS
AV
t
= |V
t
(T
1
)| |V
t
(T
2
)|
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o

A
V
t
[
m
V
]
T=125C
T=25C
T=125C
T=25C
0.4
0.6
0.8
1.0
1.2
1.4
2.4/4 PMOS
AV
t
= |V
t
(T
1
)| |V
t
(T
2
)| AV
t
= |V
t
(T
1
)| |V
t
(T
2
)|
Figure 13: threshold voltage mismatch fluctuations (oAV
t
) as a
function of variant (PMOS). Results for T= 25C and T=125C are
compared. 3o error bars indicate statistical uncertainty. The extra
points (triangles) for the reference indicate the repeatability of the
measurements.
2.4/4 PMOS
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|
Figure 14: relative current factor mismatch fluctuations (oA|/|)
as a function of variant (PMOS). Results for T= 25C and
T=125C are compared. 3o error bars indicate statistical
uncertainty.
T=125C
T=25C
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A
|
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[
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]
0.10
0.14
0.18
0.22
0.26
0.30
0.34
2.4/4 PMOS
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|
T=125C
T=25C
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A
|
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[
%
]
0.10
0.14
0.18
0.22
0.26
0.30
0.34
2.4/4 PMOS
T=125C
T=25C
T=125C
T=25C
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0.34
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A
|
/
|
[
%
]
0.10
0.14
0.18
0.22
0.26
0.30
0.34
2.4/4 PMOS
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|

A
|
/
|
[
%
]
r
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1

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2

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3

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4

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c
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
T=125C
T=25C
2.4/4 PMOS
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|
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2

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3

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4

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i
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e
s
a
u
t
o
m
a
t
i
c
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6

A
|
/
|
[
%
]
T=125C
T=25C
T=125C
T=25C
186
Conclusions
We present a comprehensive set of carefully designed
matched pair test structures for studying metal coverage
effects in a 45 nm state-of-the-art CMOS technology with
Cu damascene processing. We report substantial offsets in
drain currents of up to 1.5% for NMOS devices. These
offsets are attributed to mobility differences associated with
mechanical stress. At higher wafer temperatures (125 C)
this stress effect apparently reduces significantly. To the
best of our knowledge this has not been reported before.
For most digital ULSI applications, an offset of a few
percents is generally considered negligible compared to the
total process variability. It is therefore reassuring that this
study confirms that there will be no substantial contribution
to digital circuit variability due to (even arbitrary) placement
of metal routing and CMP tiles. For high precision analogue
and mixed signal applications however, it is (still) highly
recommendable to avoid the use of first and second metal on
top of the matching devices. At least it should be made sure
that metal coverage and dummy tiling is always as
symmetrical as possible on supposedly identical devices.
References
[1] N. Wils, H. Tuinhout and M. Meijer, Characterization of STI
Edge Effects on CMOS Variability; IEEE Transactions on
Semiconductor Manufacturing 2009, vol.22, no.1, pp.59-65
[2] P.G. Drennan et al, Implications of Proximity Effects for
Analog Design; Proceedings IEEE CICC 2006, pp.169-176
[3] H.P. Tuinhout and M. Vertregt, Test structures for
investigation of metal coverage effects on MOSFET matching;
Proc.IEEE ICMTS 1997, pp.179-183
[4] J.A. Croon et al, A comparison of extraction techniques for
threshold voltage mismatch; Proceedings IEEE ICMTS 2002,
pp.235-240
[5] P. Andricciola and H.P. Tuinhout, The temperature
dependence of mismatch in deep-submicron bulk MOSFETs;
IEEE Electron Device Letters 2009, vol.30, no.6, pp.690-692
187