20nm CMOS DRC

CPO width 0.048 0.021

Length of Gate (PO)

Poly

0.02
Active (od)

Via0 MP CPO

0.054

W=Width of device

0.03 MP

0.016 CPO width 0.048 Fig.01. MOS Device

Minimum PO width 0.02 Minimum OD width 0.10 PO to OD Extension 0.054 Minimum OD to CPO space 0.021 Minimum OD to MP space 0.030 Minimum MP to CPO space 0.16

MD1 0.006 MD2 0.022 0.025

0.019 0.003 0.026

Minimum Via0 to OD Enclosure 0.003 (at OD end side) Minimum MD1 to OD Enclosure 0.006 Minimum MD2 to OD Enclosure 0.006 PO to OD Extension 0.054 Minimum PO to MD1 space 0.022 Minimum PO to MD2 space 0.022 Minimum MD1, MD2 width 0.026 Minimum PO to via0 space 0.019(Inside OD) MD1 can be 0.006 less from OD in Vertical Direction Via0 Enclosure of MD2 should be 0.025 on two opposite sides.

0.040

Minimum MP to PO 0.040 Minimum Horizontal MD1 to MD1 0.087 Minimum Vertical MD1 to MD1 0.064 Minimum space between MD2 to MD2 0.064 Via size 0.032 X 0.032 (or)0.032 X 0.064

dddddddddddddddddddddddddd

0.040

Minimum MP to MP 0.048, but MP to PO 0.040 only Available So need to go Diagonal placement of MP Diagonal MP to MP 0.068

0.068 (

0.048

CONNECTIVITY OD-MD1-MD2-via0-Metal1-via1-Metal2- via2-Metal3-via4-Metal4 PO-MP-via0-Metal1-via1-Metal2- via2-Metal3-via4-Metal4

MP
0.009 0.106 0.004 0.009 0.037 0.009 0.037 0.004 0.040

0.009 0.050

0.050

MP Enclosure of via0 should be 0.009 all side or (0.004 on opposite sides and 0.037 on other sides)

0.048 0.068

0.085

0.085

0.068 0.016

Minimum overlap of MP over PO

Minimum Vertical space between MP to MP 0.48 Minimum Horizontal space between MP to MP 0.085 Minimum Diagonal space between MP to MP 0.068

CPO Minimum CPO width 0.068 PO to CPO Extension 0.039 SR_DPO to CPO Extension 0.039 MP to CPO space 0.016 CPO USED TO CUT PO or SR_DPO

SR_DPO
SR-DPO-> Dummy poly For Every End Device 2 dummy Poly need

 Minimum of 5 continuous poly pitch need OD should not cover any SR-DPO

Placement of two Device without share

Minimum width of SR_DPO 0.020 SR_DPO to SR_DPO space 0.07 All PO or SR_DPO should be covered by PP or NP PO or SR_DPO should be continuous poly pitch (0.07)

PP or NP

Minimum width of PP or NP 0.182 Minimum space of PP or NP 0.182 Minimum space of PP to PP or NP to NP 0.041 Minimum Enclosure of PP or NP for OD 0.041 on opposite side and 0.09 on other two sides

Minimum Enclosure of PP or NP for OD 0.041 on opposite side and 0.09 on other two sides (Or) 0.064 All sides

Metal1 DRC
Metal1 to metal1 Horizontal space is 0.032 Metal1 to metal1 vertical space is 0.032 Minimum width of metal1 is 0.032

0.032 Fig.M1.00 Metal width is 0.032

0.07 0.032

Fig.M1.01 Horizontal Metal1 to metal1 space is 0.032

0.032

Fig.M1.02 Vertical Metal1 to metal1 space is 0.032

0.048

0.048

Example:

0.032 0.032 0.032 0.032 0.032 0.032

0.048 0.032 Fig.M1.04 All the DRC of rule of metal1-as a test case

Via0-Metal1 Enclosure

Metal1 Enclosure of via0 All side 0.016

Metal1 Enclosure of via0 should be 0.036 on opposite sides

Metal1 Enclosure of via0 should be 0.036 on opposite sides and 0.009 on other two sides

(Via1-Metal1 Enclosure) or (Via1-Metal2 Enclosure) or (Via2-Metal2 Enclosure) or (Via2-Metal3 Enclosure) or (Via3-Metal3 Enclosure) or (Via3-Metal4 Enclosure) or (Via4-Metal4 Enclosure) or (Via4-Metal5 Enclosure)

via1

via2

via3 Metal1 Enclosure of via1 should be 0.016 all side or 0.036 on two opposite sides Metal2 Enclosure of via1 should be 0.016 all side or 0.036 on two opposite sides Metal2 Enclosure of via2 should be 0.016 all side or 0.036 on two opposite sides Metal3 Enclosure of via2 should be 0.016 all side or 0.036 on two opposite sides Metal3 Enclosure of via3 should be 0.016 all side or 0.036 on two opposite sides Metal4 Enclosure of via3 should be 0.016 all side or 0.036 on two opposite sides

Metal1 Enclosure of via1 should be 0.016 all side or 0.036 on two opposite sides

0.068

Minimum Via1 to via1 space 0.068 Minimum Via2 to via1 space 0.068 Minimum Via3 to via1 space 0.068

Metal1 can be either vertical or horizontal Direction Metal2 should be Horizontal Direction Metal3 should be vertical Direction Metal4 should be Horizontal Direction

************(40nm

CMOS DRC Developed for Vertical Poly)*********

PMET should cover OD of all P Device Poly pitch should be continuous All PO and SR_DPO should be cover by PP or NP OD should not come on SR_DPO

Layer select window

Psub nwell od np pp md1 md2 mp cpo sr_dpo P Substrate Active N implantation P implantation via0 meatl1 via1 melat2 via2 meatal3 via3 meatal4 pmet bdr sr_dod sr_dmd1 sr_dmd2 sr_dmy4 m1txt m2txt m3txt m4txt nwtxt psubtxt P Device should cover by pmet Boundary

only for 88nm pitch Device

Cut Poly Dummy poly

text on nwell with NP text on PP

CMOS INV

Metal3-VSS Metal2 Via1 MD2

Metal3-OUT

Metal3-VDD Via2 Metal1 Via0

MP

MP

MD1

IN NP P Sub PP

poly Nwell