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IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 56, NO. 6, DECEMBER 2009

A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability
Shah M. Jahinuzzaman, Member, IEEE, David J. Rennie, Member, IEEE, and Manoj Sachdev, Senior Member, IEEE
AbstractWe propose a quad-node ten transistor (10T) soft error robust SRAM cell that offers differential read operation for robust sensing. The cell exhibits larger noise margin in sub-0.45 V regime and 26% less leakage current than the traditional soft error tolerant 12T DICE SRAM cell. When compared to a conventional 6T SRAM cell, the proposed cell offers similar noise margin as the 6T cell at half the supply voltage, thus signicantly saving the leakage power. In addition, the cell exhibits 98% lower soft error rate than the 6T cell in accelerated neutron radiation tests carried out at TRIUMF on a 32-kb SRAM implemented in 90-nm CMOS technology. Index TermsDifferential read, single event effects, soft error rates, SRAMs, standard process.
Fig. 1. Particle-induced single event transient in a latch.

I. INTRODUCTION

UE to low signal charge and reduced noise margin, nanoscale integrated circuits are extremely susceptible to particle-induced single event transients (SETs) [1], [2]. Primarily, SETs are caused by alpha particles and cosmic neutrons, which originate from packaging materials and intergalactic rays, respectively. Through direct or indirect ionization in silicon, these particles generate extra charge, which gets collected by sensitive nodes and creates voltage transients at those nodes [3]. Fig. 1 illustrates such an event in a latch consisting of a cross-coupled inverter pair. When the amplitude and duration of the transient is large, it alters the stored value in the latch, causing a single event upset (SEU). A SEU is also referred to as a soft error as it does not permanently damage the device. However, soft error can lead to system malfunctions and as such, state-of-the-art microprocessors require soft error protection [4]. While both logic circuits and memory are vulnerable to soft errors, the latter is more susceptible because of high packing density and lack of error masking mechanisms [5]. Particularly, static random access memory (SRAM) is more prone to soft errors due to larger sensitive volume per bit and lower node capacitance than its dynamic counterpart [6]. In addition, the soft error

Manuscript received May 08, 2009; revised August 24, 2009. Current version published December 09, 2009. This work was supported by the Discovery Grant of the National Science and Engineering Research Council (NSERC) of Canada. S. M. Jahinuzzaman is with the Department of Electrical and Computer Engineering, Concordia University, Montreal, QC H3G 1M8, Canada (e-mail: shah@ece.concordia.ca). D. J. Rennie and M. Sachdev are with the Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON N2L 3G1, Canada (e-mail: djrennie@engmail.uwaterloo.ca; msachdev@uwaterloo.ca). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TNS.2009.2032090

rate (SER) in SRAMs is increasing as the technology scales in the nanometre regime [2], [7]. In order to limit the SRAM SER, error correction codes (ECC) or soft error hardened memory cells are used. However, due to the limited multiple-bit error correction capability of ECC coupled with the increasing probability of neutron-induced multiple-bit upset [8], the hardened cells appear to be more attractive. The most widely used hardened cell is the ten transistor (10T) dual interlocked cell (DICE) [9]. While this cell is fully compatible with the standard CMOS process, it requires 12 transistors to facilitate the differential read operation (see Fig. 2(a)). Differential read is critical for bit line noise immunity under the process-voltage-temperature (PVT) variations. Olson et al. reported another process-compatible differential 10T SRAM cell that lowered the SER [10]. However, due to an extra series NMOS transistor on the read current path, the cell exhibits a signicantly reduced read current under area constraints. An area-efcient 6T SRAM cell with cross-coupled node capacitor (see Fig. 2(b)) shows a considerable reduction on the SER [11]. However, the cell requires special process steps to realize the metal-insulator-metal (MIM) type capacitor on top of the cell. Similarly, two special-process DRAM-like capacitors are often added to a 6T cell to reduce the SER [12]. In this paper, we present a 10T soft error robust SRAM cell that is compatible with standard CMOS process and offers differential read operation with large noise margin. The cell is referred to as the Quatro-10T cell and was tested under accelerated neutron radiation by implementing a 32-kb SRAM macro in 90-nm CMOS technology. The paper is organized as follows. Section II presents the proposed Quatro-10T cell. Section III describes the read and write operations and the pertinent sizing requirements. Section IV analyzes the soft error robustness of the cell. Section V presents the radiation test results while Section VI draws the conclusion.

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Fig. 2. a) 12T DICE cell for differential read/write and b) standard 6T cell with cross-coupled node capacitor.

Fig. 4. a) Quatro-10T cell with DC noise inserted at storage nodes and b) voltage transfer characteristics during read access.

of the transients. The worst case happens when two nodes of the same potential (nodes A and D or nodes B and C) are affected. Therefore, in order to reduce the possibility of upsets due to charge sharing, the Quatro-10T is laid out by keeping the same potential nodes as physically apart as possible. III. OPERATION OF QUATRO-10T CELL In a read operation, as the word line (WL) signal turns on N5 and N6, the pull-down transistor N1 (N3) discharges BL (1). The resulting differential bitline voltage (BLB) if ensures reliable sensing under the worst-case bitline leakage. The logic-0 degradation is similar to that of a 6T cell for the same driver-to-access (N1/N5) ratio. However, a larger read disturbance at logic-0 node is required to ip the Quatro-10T cell. This is because, unlike the 6T cell, the accessed node does not directly drive any PMOS transistor. Fig. 4 shows the voltage transfer characteristics (VTC) of the Quatro-10T cell for equal and opposite DC noises at nodes A and B. For a stable read operation, the static noise margin (SNM) depends on the aspect ratio of N1 and N5 (or N3 and N6). Equating the dc currents through N1 and N5, the degradation of logic-0 voltage can be expressed as (1), (See equation at is the drain-to-source bottom of page) [14] where is voltage that causes the carrier velocity saturation, the threshold voltage of the NMOS, and is the cell ratio . The value of should dened as be typically 1.5 1.7 for a good read SNM. Fig. 5(a) compares the SNM, which is dened as the side of the largest square inside the eyes of the VTC of the Quatro-10T, DICE, and standard 6T cells. The VTCs are obtained by inserting equal and opposite DC noises at the two storage nodes that hold 0 and 1. The resulting SNM of Quatro-10T cell is much larger than that of the 6T cell for all supply voltages . However, the Quatro-10T cell shows a higher SNM than . This makes the Quatro the DICE cell only for sub-0.45 V cell very attractive for low-voltage operations. In addition, the

Fig. 3. Proposed soft error robust Quatro-10T cell.

II. PROPOSED QUATRO-10T CELL The proposed quad-node 10T or Quatro-10T cell is shown in Fig. 3. Two access transistors, N5 and N6, connect the bit lines (BL and BLB) to the storage nodes A and B. If the stored bit is 0, the logic values at nodes A, B, C, and D are 0, 1, 1, and 0, respectively. Each of these nodes is driven by an NMOS and a PMOS transistor, their gates being connected to two different nodes. As a result, if an SET pulls down (up) a node voltage, the node voltage is restored by the ON PMOS (NMOS) transistor connected to the node and driven by an unaffected node. If the SET turns on a PMOS (NMOS) transistor, the transistor has to work against an unaffected ON NMOS (PMOS) transistor to pull up (down) its drain voltage. Thus, a negative feedback prevents any accidental ipping of the cell. On the other hand, in a standard 6T cell (Fig. 2(b) excluding Cc), a positive feedback comes into play when an SET changes a node voltage, thus helping to ip the cell. Accordingly, if the 6T cell is sized up to occupy the same area as the Quatro-10T cell, the 6T cell will still remain more vulnerable to soft errors. It should be noted that if an SET simultaneously affects multiple nodes through charge sharing [13], the proposed Quatro-10T cell may ip like the DICE cell. The probability of such a failure depends on the location, magnitude, and duration

(1)

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Fig. 5. Comparisons of a) SNM and b) leakage current at different supply voltages in the simulation.

Fig. 7. Simplied view of Quatro-10T cell at the beginning of a write access.

Fig. 6. SNM and leakage current of Quatro-10T and standard 6T cells in simulations.

Quatro-10T cell consumes 26% less leakage current than the 12T DICE cell and 53% higher leakage current than the 6T cell when simulated at 1 V (see Fig. 5(b)). However, a trade-off between the leakage current and SNM can be made. For example, with an SNM the Quatro-10T cell can operate at of 125 mV and a leakage current of 893 pA at 27 , as shown , in Fig. 6. For the same SNM, the 6T cell requires which results in a cell leakage of 1.1 nA. Thus, the Quatro-10T cell can save 19% cell leakage without compromising the read SNM. In a write operation, the Quatro-10T cell is driven to the new logic value by both bit lines. For writing 0, BL and BLB are

pre-charged to 0 and 1 respectively, and the WL is activated. A simplied view of the cell at the activation of WL is shown in Fig. 7. Once WL is high, BL pulls down the potential at node A, , below to turn off N3 (see Fig. 7). In order to achieve this, N5 has to be stronger than P1. To nd the pertinent condition, we equate the DC currents through P1 and N5 and express the voltage at node A as (2) (See equation at bottom of page) and are electron and hole mobilities, respecHere, is referred to as pull-up ratio-1 dened as tively, and . Since the NMOS has a higher carcan be 1 to enable pulling down . As rier mobility, is pulled below to turn off N3, BLB pulls up through . The resulting overdrive of N4 has to N6 towards can be pulled be strong enough to ght against P4 so that down to ip the cell. Equating the DC currents through P4 (saturation) and N4 (linear), the voltage at node D can be expressed is referred as (3) (See equation at bottom of page) where . to as pull-up ratio-2 dened as has to be pulled below To complete writing into the cell, so that P2 and P3 can be turned on. A of 0.75 or smaller can reliably do this job as shown in Fig. 8. Since the Quatro-10T cell is symmetric, all of its constituent , , transistors can thus be easily sized by choosing the and . IV. SOFT ERROR ROBUSTNESS OF QUATRO-10T CELL The soft error robustness of the Quatro-10T cell is veried in SPICE by injecting an exponential current at nodes A, B, C, and

(2)

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Fig. 10. Simulation showing ipping of the cell for an injected current mimicking a 0 1 SET at node A. Fig. 8. Simulation waveforms of storage nodes, word line, and bit lines in a write cycle.

, is When node A stores 0 and an exponential current, injected into the node, the resulting transient can be described by the following equation:

(4) is the effective node capacitance, is the ON resiswhere tance of transistor N1 operating in the linear region, the total charge injected by the noise current, and the time constant of the noise current. Such single time constant noise current is used because the rising time constant of a typical SET is very small compared to the falling time constant, and it simplies mathematical operations [15]. The solution of (4) can be derived as:

(5)
Fig. 9. Simulation showing recovery of the cell for an injected current mimicking a 1 0 SET at node A.

By differentiating (5) and equating the result to zero, we can reaches a maximum: nd the time when

D to mimic a particle-induced SET. Results show that all nodes 0 SET. Fig. 9 illustrates are capable of recovering from 1 0 SET at node A. On the other hand, such a recovery for a 1 1 SETs; however, nodes C and D are able to recover from 0 1 SET at node A or B has the potential a sufciently large 0 and a large 0 1 SET occurs at node to ip the cell. If while N3 can turn A, N2 can turn on P1 and P4 by lowering off N4 by lowering . Consequently, the cell ips as shown in Fig. 10. However, the critical charge for such a case is very large ( 7.9 fC or 3 compared to 6T cell), meaning a very high energy neutron is required to cause the upset. Since the ground level neutron ux exponentially decreases with increasing en1 SET ergy, the upset probability is low. Furthermore, the 0 is less likely to occur at the drain of the OFF PMOS since it 0 SET does due requires a higher energy neutron than a 1 to the n-well-to-p-substrate junction collecting a sizable portion of the deposited charge. However, the storage nodes (A and B) 1 of the Quatro-10T cell can be made more robust against 0 SET by appropriately sizing some of the transistors. To identify those transistors, we consider the transient response of the node storing logic-0 when the exponential current pulse is injected.

(6) Substituting (6) into (5) yields the maximum voltage caused at node A due to the injected current (see Fig. 11):

(7) In order to prevent any upset due to the injected current, has to be less than . Thus, using (7) we get

Or

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Fig. 13. a) Die photograph of the test chip and b) measured power components of the Quatro-10T-based 32-kb SRAM. Fig. 11. Simulation showing recovery of the cell for an injected current mim1 SET at node A. icking a 0

Fig. 14. a) Energy spectrum of TRIUMFs neutron beam used to irradiate the chip and b) measured soft error rate comparisons.

Fig. 12. Simulation results showing logic 0 degradation on a read access and 0 1 critical charge of logic 0 node as a function of driver transistor width.

The sizing of the driver transistors (N1 and N3) has to be such is small enough to satisfy the inequality given by (8). that Fig. 12 shows the critical charge increase with increasing width of the driver transistors. Fig. 12 also shows that increasing the width of the driver transistors also reduces the logic-0 degradaon read access, thus improving read stability. The tion designer should choose the transistor size such that the required soft error robustness is achieved within the given area constraint. Noted that increasing the size of the driver transistors does not noticeably affect the write time. This is because the driver transistor is shut off by the storage node that is pulled down by one of the bit lines during the write operation. V. RADIATION TEST RESULTS OF A 32-kb SRAM A test chip containing a 32-kb (256 128) Quatro-10T-based SRAM and a 64-kb (256 256) standard 6T-based SECDEDECC-protected SRAM was fabricated in 90-nm CMOS technology (see Fig. 13(a)). The word size for both of the SRAMs was 32-bits. The area consumption of the 32-kb Quatro-10T SRAM was similar to the 64-kb ECC-protected SRAM since the laid out area of the Quatro cell was 2.57 times the area of the 6T cell. The measured power components of the Quatro SRAM are shown in Fig. 13(b). Power measurements were done at 100

MHz with a supply of 0.8 V due to the limitations of test equipment; however, the SRAM was designed to operate at 300 MHz at 1 V. Accelerated neutron radiation tests on the test chip were performed according to the JEDEC standards at TRIUMF in Vancouver, BC, Canada. The average neutron beam uence was , which was approximately times the neutron uence at the sea level in New York City (NYC). The energy spectrum of the beam was similar to that of the atmospheric neutrons as shown in Fig. 14(a). In the radiation tests, the Quatro-10T cell showed 98% less SER than the 6T cell and 14% less SER than the ECC-protected SRAM, as shown in Fig. 14(b). The few errors that occurred in the Quatro-10T SRAM cell can be attributed to SETs affecting multiple nodes [10], [13]. Such SETs can also upset a DICE cell [13], which consists of 12 transistors and hence, occupies larger area than the Quatro cell. Thus, the proposed Quatro-10T cell manifests itself as a lower cost alternative to the DICE cell for realizing soft error robust SRAMs. VI. CONCLUSION We have presented a 10T SRAM cell that reduces soft errors by 98% and facilitates a differential read access. Differential read is critical for easier design of the sense amplier and for reliable sense operation under the worst case conditions. The high SNM of the proposed cell enables operating in sub-0.4 V regime to save leakage power while offering better data stability compared to the 6T cell as well as the DICE cell. In addition, the cell can be used as a latch to design soft error robust register les and ip-ops. Research along this line is currently in progress.

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ACKNOWLEDGMENT The authors are grateful to Dr. Sharifkhani for numerous stimulating discussions, to Pierce Chuang for PCB design, and to Dr. Ewart Blackmore at TRIUMF for help in radiation tests. REFERENCES
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